Instead of using RawObject* as keys, use Object*. Using handles eliminates any assumption
about the underlying GC implementation (e.g. requiring that old objects don't move).
Remove special handling of null_object by making HashMap more generic and
allowing the trait to specify the value used to indicate an empty element.
The goal is to use one unified, efficient implementation of the constant
pool on all architectures that require one (x64, arm64, mips).
R=vegorov@google.com, zra@google.com
Review URL: https://codereview.chromium.org//848703002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42901 260f80e4-7a28-3924-810f-c04153c831b5
In addition to tracking input and output ranges in the IC-stubs with a Smi fastpath (SmiAdd and SmiSub, currently) this CL also introduces two IC stubs that have no fast-path by still track ranges and update the range feedback.
We are able to distinguish between the following ranges (encoding of the lattice is shown in the parens):
- u-smi (0000)
- smi (0001)
- uint31 (0010)
- int32 (0011)
- uint32 (0100)
- int64 (1xxx) and (x1x1)
BUG=
R=fschneider@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//735543003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42370 260f80e4-7a28-3924-810f-c04153c831b5
First steps towards general pretenuring support.
* Generalize Heap::Top/EndAddress.
* Add testing flag to exercise new code paths.
* Also update the slow-case runtime calls, to ensure a fresh block will be allocated in old.
Next steps are general invalidation of the generated code and adding a policy that doesn't blow up the store buffers), and freelist allocation.
Review URL: https://codereview.chromium.org//578443003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40530 260f80e4-7a28-3924-810f-c04153c831b5
1. Deopts on division when neither vfp nor idiv are present.
In a subsequent CL, I can add a leaf runtime call for this.
2. Uses a different PC read offset in STR and STM instructions.
On ARMv5 and earlier, the PC read offset is 8 except in STR
and STM instructions, where it is implementation defined. On
lego mindstorm it is 12. This requires changing
kEntryPointToPcMarkerOffset to be a function.
3. Uses a dummy struct to compute the size of a compressed
pc descriptor to avoid alignment issues. sizeof(PcDescriptorRec)
is 16 on ia32 and arm. Subtracting sizeof(int16_t) gives 14,
which creates alignment problems on ARM, i.e. poor performance on
ARMv6 and later, and wrong results on ARMv5 and earlier.
R=regis@google.com
Review URL: https://codereview.chromium.org//467103005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@39250 260f80e4-7a28-3924-810f-c04153c831b5
This change generate inline code for context allocation and makes
the stores to initialize the parent pointer and the context variables
explicit in the optimized flow graph. This allows dead store elimination
to eliminate those stores.
Before, we only had inlined context allocation for ia32.
Furthermore:
* Added an assertion that the exit label of slow-path code
is bound when emitting deferred code. This used to cause random crashes
if forgotten.
* Fixed a bug in allocation stats on ARM.
BUG=dartbug.com/17238
R=srdjan@google.com
Review URL: https://codereview.chromium.org//346823003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@39202 260f80e4-7a28-3924-810f-c04153c831b5
On these architectures it's preferable to load Scavenger address into the register and then access top/end fields through this register instead of loading addresses of those fields as immediates --- which takes either two instructions or a memory load through a pool pointer.
Cleanup boxing slow-paths in the optimizing compiler. We had tons of duplicated code that was essentially doing the same thing.
BUG=
R=johnmccutchan@google.com, regis@google.com
Review URL: https://codereview.chromium.org//410333003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38539 260f80e4-7a28-3924-810f-c04153c831b5
Change executable pages to be read/execute but not writable by default.
All pages are made temporarily writable just before a full GC, because both
the mark and sweep phases write to the pages. When allocating in a page and
when patching code, the pages are made temporarily writable.
The order of allocation of Code and Instructions objects is changed so that
a GC will not occur after Instructions is allocated. (A full GC would
render the Instructions unwritable.) A scoped object is used to make memory
protection simpler.
Original CL: https://codereview.chromium.org/106593002/
I added a cc test that is expected to crash.
R=srdjan@google.com
Review URL: https://codereview.chromium.org//136563002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32493 260f80e4-7a28-3924-810f-c04153c831b5
This change adds a flag --mips-far-branches, which when set causes
relative branches to be converted to absolute branches by determining
the PC, adding the branch offset to it, and using the jr or jalr
instruction to jump if the branch test passes.
This procedure clobbers the assembler temporary TMP, so TMP can no
longer be used in a branch test or in the branch delay slot of a
relative branch. Because TMP can't be used in a branch test, a
new temporary is introduced CMPRES2. This change replaces TMP with
CMPRES1 or another register where TMP can no longer be used.
Tests that were failing due to a too-far relative have the
--mips-far-branches flag set.
R=regis@google.com
Review URL: https://codereview.chromium.org//20369003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25543 260f80e4-7a28-3924-810f-c04153c831b5
number (or bad name) of arguments is passed.
The frame of the wrong method (the one invoked with the wrong number or name of
arguments) is not left on the stack and therefore not visible in the stack trace
anymore, which is much cleaner, especially since the leftover frame was not
fully initialized.
This change was already done on ARM.
R=zra@google.com
Review URL: https://codereview.chromium.org//17857008
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24485 260f80e4-7a28-3924-810f-c04153c831b5
- Exposes double precision rather than single precision floating point registers
to architecture generic code. This entails a mechanical change in the assembler
to floating point instructions.
- Adds slti, sltiu instructions for comparison with small immediates, and uses
them in the Branch(Un)Signed* macros.
- Fixes a bug in the intermediate language comparison/branching instructions
caused by using subu for comparison. Now it uses two slt instructions.
- Fixes register use bugs in intermediate language.
- More uses of NULLREG instead of loading Object::null()
R=regis@google.com
Review URL: https://codereview.chromium.org//16022011
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23190 260f80e4-7a28-3924-810f-c04153c831b5
fschneider@google.com