regis@google.com
d79c7c1969
Implement error and exception handler stubs on ARM. Hook up simulator for object tests. Enable codegen and object tests on ARM. Review URL: https://codereview.chromium.org//14309004 git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21680 260f80e4-7a28-3924-810f-c04153c831b5
550 lines
16 KiB
C++
550 lines
16 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#include "vm/globals.h"
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#if defined(TARGET_ARCH_MIPS)
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#include "vm/assembler.h"
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#include "vm/runtime_entry.h"
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#include "vm/simulator.h"
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#include "vm/stub_code.h"
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namespace dart {
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DEFINE_FLAG(bool, print_stop_message, false, "Print stop message.");
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void Assembler::InitializeMemoryWithBreakpoints(uword data, int length) {
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ASSERT(Utils::IsAligned(data, 4));
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ASSERT(Utils::IsAligned(length, 4));
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const uword end = data + length;
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while (data < end) {
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*reinterpret_cast<int32_t*>(data) = Instr::kBreakPointInstruction;
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data += 4;
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}
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}
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void Assembler::Bind(Label* label) {
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ASSERT(!label->IsBound());
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int bound_pc = buffer_.Size();
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while (label->IsLinked()) {
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const int32_t position = label->Position();
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const int32_t next = buffer_.Load<int32_t>(position);
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// Relative destination from an instruction after the branch.
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const int32_t dest = bound_pc - (position + Instr::kInstrSize);
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const int32_t encoded = Assembler::EncodeBranchOffset(dest, next);
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buffer_.Store<int32_t>(position, encoded);
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label->position_ = Assembler::DecodeBranchOffset(next);
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}
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label->BindTo(bound_pc);
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delay_slot_available_ = false;
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}
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int32_t Assembler::EncodeBranchOffset(int32_t offset, int32_t instr) {
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ASSERT(Utils::IsAligned(offset, 4));
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ASSERT(Utils::IsInt(18, offset));
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// Properly preserve only the bits supported in the instruction.
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offset >>= 2;
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offset &= kBranchOffsetMask;
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return (instr & ~kBranchOffsetMask) | offset;
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}
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int Assembler::DecodeBranchOffset(int32_t instr) {
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// Sign-extend, left-shift by 2.
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return (((instr & kBranchOffsetMask) << 16) >> 14);
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}
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void Assembler::LoadWordFromPoolOffset(Register rd, int32_t offset) {
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ASSERT(rd != PP);
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if (Address::CanHoldOffset(offset)) {
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lw(rd, Address(PP, offset));
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} else {
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const int16_t offset_low = Utils::Low16Bits(offset); // Signed.
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offset -= offset_low;
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const uint16_t offset_high = Utils::High16Bits(offset); // Unsigned.
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if (offset_high != 0) {
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lui(rd, Immediate(offset_high));
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addu(rd, rd, PP);
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lw(rd, Address(rd, offset_low));
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} else {
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lw(rd, Address(PP, offset_low));
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}
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}
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}
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void Assembler::AdduDetectOverflow(Register rd, Register rs, Register rt,
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Register ro) {
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ASSERT(rd != ro);
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ASSERT(rd != TMP1);
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ASSERT(ro != TMP1);
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ASSERT(ro != rs);
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ASSERT(ro != rt);
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if ((rs == rt) && (rd == rs)) {
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ASSERT(rd != TMP2);
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ASSERT(ro != TMP2);
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ASSERT(rs != TMP2);
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ASSERT(rt != TMP2);
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mov(TMP2, rt);
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rt = TMP2;
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}
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if (rd == rs) {
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mov(TMP1, rs); // Preserve rs.
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addu(rd, rs, rt); // rs is overwritten.
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xor_(TMP1, rd, TMP1); // Original rs.
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xor_(ro, rd, rt);
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and_(ro, ro, TMP1);
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} else if (rd == rt) {
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mov(TMP1, rt); // Preserve rt.
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addu(rd, rs, rt); // rt is overwritten.
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xor_(TMP1, rd, TMP1); // Original rt.
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xor_(ro, rd, rs);
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and_(ro, ro, TMP1);
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} else {
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addu(rd, rs, rt);
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xor_(ro, rd, rs);
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xor_(TMP1, rd, rt);
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and_(ro, TMP1, ro);
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}
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}
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void Assembler::SubuDetectOverflow(Register rd, Register rs, Register rt,
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Register ro) {
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ASSERT(rd != ro);
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ASSERT(rd != TMP1);
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ASSERT(ro != TMP1);
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ASSERT(ro != rs);
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ASSERT(ro != rt);
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ASSERT(rs != TMP1);
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ASSERT(rt != TMP1);
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// This happens with some crankshaft code. Since Subu works fine if
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// left == right, let's not make that restriction here.
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if (rs == rt) {
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mov(rd, ZR);
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mov(ro, ZR);
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return;
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}
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if (rd == rs) {
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mov(TMP1, rs); // Preserve left.
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subu(rd, rs, rt); // Left is overwritten.
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xor_(ro, rd, TMP1); // scratch is original left.
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xor_(TMP1, TMP1, rs); // scratch is original left.
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and_(ro, TMP1, ro);
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} else if (rd == rt) {
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mov(TMP1, rt); // Preserve right.
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subu(rd, rs, rt); // Right is overwritten.
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xor_(ro, rd, rs);
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xor_(TMP1, rs, TMP1); // Original right.
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and_(ro, TMP1, ro);
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} else {
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subu(rd, rs, rt);
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xor_(ro, rd, rs);
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xor_(TMP1, rs, rt);
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and_(ro, TMP1, ro);
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}
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}
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void Assembler::LoadObject(Register rd, const Object& object) {
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// Smis and VM heap objects are never relocated; do not use object pool.
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if (object.IsSmi()) {
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LoadImmediate(rd, reinterpret_cast<int32_t>(object.raw()));
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} else if (object.InVMHeap()) {
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// Make sure that class CallPattern is able to decode this load immediate.
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int32_t object_raw = reinterpret_cast<int32_t>(object.raw());
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const uint16_t object_low = Utils::Low16Bits(object_raw);
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const uint16_t object_high = Utils::High16Bits(object_raw);
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lui(rd, Immediate(object_high));
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ori(rd, rd, Immediate(object_low));
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} else {
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// Make sure that class CallPattern is able to decode this load from the
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// object pool.
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const int32_t offset =
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Array::data_offset() + 4*AddObject(object) - kHeapObjectTag;
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LoadWordFromPoolOffset(rd, offset);
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}
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}
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int32_t Assembler::AddObject(const Object& obj) {
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ASSERT(obj.IsNotTemporaryScopedHandle());
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ASSERT(obj.IsOld());
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if (object_pool_.IsNull()) {
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// The object pool cannot be used in the vm isolate.
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ASSERT(Isolate::Current() != Dart::vm_isolate());
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object_pool_ = GrowableObjectArray::New(Heap::kOld);
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}
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for (int i = 0; i < object_pool_.Length(); i++) {
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if (object_pool_.At(i) == obj.raw()) {
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return i;
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}
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}
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object_pool_.Add(obj, Heap::kOld);
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return object_pool_.Length() - 1;
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}
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void Assembler::PushObject(const Object& object) {
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LoadObject(TMP1, object);
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Push(TMP1);
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}
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void Assembler::CompareObject(Register rd, Register rn, const Object& object) {
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ASSERT(rn != TMP1);
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LoadObject(TMP1, object);
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subu(rd, rn, TMP1);
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}
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// Preserves object and value registers.
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void Assembler::StoreIntoObjectFilterNoSmi(Register object,
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Register value,
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Label* no_update) {
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COMPILE_ASSERT((kNewObjectAlignmentOffset == kWordSize) &&
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(kOldObjectAlignmentOffset == 0), young_alignment);
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// Write-barrier triggers if the value is in the new space (has bit set) and
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// the object is in the old space (has bit cleared).
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// To check that, we compute value & ~object and skip the write barrier
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// if the bit is not set. We can't destroy the object.
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nor(TMP1, ZR, object);
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and_(TMP1, value, TMP1);
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andi(TMP1, TMP1, Immediate(kNewObjectAlignmentOffset));
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beq(TMP1, ZR, no_update);
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}
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// Preserves object and value registers.
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void Assembler::StoreIntoObjectFilter(Register object,
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Register value,
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Label* no_update) {
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// For the value we are only interested in the new/old bit and the tag bit.
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// And the new bit with the tag bit. The resulting bit will be 0 for a Smi.
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sll(TMP1, value, kObjectAlignmentLog2 - 1);
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and_(TMP1, value, TMP1);
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// And the result with the negated space bit of the object.
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nor(TMP2, ZR, object);
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and_(TMP1, TMP1, TMP2);
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andi(TMP1, TMP1, Immediate(kNewObjectAlignmentOffset));
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beq(TMP1, ZR, no_update);
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}
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void Assembler::StoreIntoObject(Register object,
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const Address& dest,
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Register value,
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bool can_value_be_smi) {
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ASSERT(object != value);
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sw(value, dest);
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Label done;
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if (can_value_be_smi) {
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StoreIntoObjectFilter(object, value, &done);
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} else {
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StoreIntoObjectFilterNoSmi(object, value, &done);
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}
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// A store buffer update is required.
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if (value != T0) Push(T0); // Preserve T0.
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if (object != T0) {
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mov(T0, object);
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}
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BranchLink(&StubCode::UpdateStoreBufferLabel());
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if (value != T0) Pop(T0); // Restore T0.
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Bind(&done);
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}
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void Assembler::StoreIntoObjectNoBarrier(Register object,
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const Address& dest,
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Register value) {
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sw(value, dest);
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#if defined(DEBUG)
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Label done;
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StoreIntoObjectFilter(object, value, &done);
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Stop("Store buffer update is required");
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Bind(&done);
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#endif // defined(DEBUG)
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// No store buffer update.
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}
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void Assembler::StoreIntoObjectNoBarrier(Register object,
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const Address& dest,
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const Object& value) {
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ASSERT(value.IsSmi() || value.InVMHeap() ||
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(value.IsOld() && value.IsNotTemporaryScopedHandle()));
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// No store buffer update.
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LoadObject(TMP1, value);
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sw(TMP1, dest);
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}
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void Assembler::LoadClassId(Register result, Register object) {
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ASSERT(RawObject::kClassIdTagBit == 16);
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ASSERT(RawObject::kClassIdTagSize == 16);
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const intptr_t class_id_offset = Object::tags_offset() +
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RawObject::kClassIdTagBit / kBitsPerByte;
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lhu(result, FieldAddress(object, class_id_offset));
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}
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void Assembler::LoadClassById(Register result, Register class_id) {
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ASSERT(result != class_id);
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lw(result, FieldAddress(CTX, Context::isolate_offset()));
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const intptr_t table_offset_in_isolate =
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Isolate::class_table_offset() + ClassTable::table_offset();
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lw(result, Address(result, table_offset_in_isolate));
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sll(TMP1, class_id, 2);
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addu(result, result, TMP1);
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lw(result, Address(result));
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}
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void Assembler::LoadClass(Register result, Register object) {
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ASSERT(TMP1 != result);
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LoadClassId(TMP1, object);
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lw(result, FieldAddress(CTX, Context::isolate_offset()));
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const intptr_t table_offset_in_isolate =
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Isolate::class_table_offset() + ClassTable::table_offset();
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lw(result, Address(result, table_offset_in_isolate));
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sll(TMP1, TMP1, 2);
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addu(result, result, TMP1);
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lw(result, Address(result));
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}
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void Assembler::EnterStubFrame(bool uses_pp) {
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if (uses_pp) {
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addiu(SP, SP, Immediate(-4 * kWordSize));
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sw(ZR, Address(SP, 3 * kWordSize)); // PC marker is 0 in stubs.
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sw(RA, Address(SP, 2 * kWordSize));
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sw(PP, Address(SP, 1 * kWordSize));
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sw(FP, Address(SP, 0 * kWordSize));
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mov(FP, SP);
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// Setup pool pointer for this stub.
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Label next;
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bal(&next);
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delay_slot()->mov(T0, RA);
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const intptr_t object_pool_pc_dist =
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Instructions::HeaderSize() - Instructions::object_pool_offset() +
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CodeSize();
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Bind(&next);
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lw(PP, Address(T0, -object_pool_pc_dist));
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} else {
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addiu(SP, SP, Immediate(-3 * kWordSize));
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sw(ZR, Address(SP, 2 * kWordSize)); // PC marker is 0 in stubs.
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sw(RA, Address(SP, 1 * kWordSize));
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sw(FP, Address(SP, 0 * kWordSize));
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mov(FP, SP);
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}
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}
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void Assembler::LeaveStubFrame(bool uses_pp) {
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mov(SP, FP);
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if (uses_pp) {
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lw(RA, Address(SP, 2 * kWordSize));
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lw(PP, Address(SP, 1 * kWordSize));
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lw(FP, Address(SP, 0 * kWordSize));
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addiu(SP, SP, Immediate(4 * kWordSize));
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} else {
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lw(RA, Address(SP, 1 * kWordSize));
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lw(FP, Address(SP, 0 * kWordSize));
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addiu(SP, SP, Immediate(3 * kWordSize));
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}
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}
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void Assembler::CallRuntime(const RuntimeEntry& entry) {
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entry.Call(this);
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}
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void Assembler::EnterDartFrame(intptr_t frame_size) {
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const intptr_t offset = CodeSize();
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addiu(SP, SP, Immediate(-4 * kWordSize));
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sw(RA, Address(SP, 2 * kWordSize));
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sw(FP, Address(SP, 1 * kWordSize));
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sw(PP, Address(SP, 0 * kWordSize));
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Label next;
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// Branch and link to the instruction after the delay slot to get the PC.
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bal(&next);
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// RA is the address of the sw instruction below. Save it in T0.
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delay_slot()->mov(T0, RA);
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// Calculate the offset of the pool pointer from the PC.
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const intptr_t object_pool_pc_dist =
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Instructions::HeaderSize() - Instructions::object_pool_offset() +
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CodeSize();
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// This sw instruction is the return address for the bal, so T0 holds
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// the PC at this sw instruction.
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Bind(&next);
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// Save PC in frame for fast identification of corresponding code.
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if (offset == 0) {
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sw(T0, Address(SP, 3 * kWordSize));
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} else {
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// Adjust saved PC for any intrinsic code that could have been generated
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// before a frame is created.
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AddImmediate(T1, T0, -offset);
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sw(T1, Address(SP, 3 * kWordSize));
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}
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// Set FP to the saved previous FP.
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addiu(FP, SP, Immediate(kWordSize));
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// Load the pool pointer.
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lw(PP, Address(T0, -object_pool_pc_dist));
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// Reserve space for locals.
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AddImmediate(SP, -frame_size);
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}
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void Assembler::LeaveDartFrame() {
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addiu(SP, FP, Immediate(-kWordSize));
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lw(RA, Address(SP, 2 * kWordSize));
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lw(FP, Address(SP, 1 * kWordSize));
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lw(PP, Address(SP, 0 * kWordSize));
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// Adjust SP for PC pushed in EnterDartFrame.
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addiu(SP, SP, Immediate(4 * kWordSize));
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}
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void Assembler::ReserveAlignedFrameSpace(intptr_t frame_space) {
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// Reserve space for arguments and align frame before entering
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// the C++ world.
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AddImmediate(SP, -frame_space);
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if (OS::ActivationFrameAlignment() > 0) {
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LoadImmediate(TMP1, ~(OS::ActivationFrameAlignment() - 1));
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and_(SP, SP, TMP1);
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}
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}
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void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
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const intptr_t kPushedRegistersSize =
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kDartVolatileCpuRegCount * kWordSize +
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2 * kWordSize + // FP and RA.
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kDartVolatileFpuRegCount * kWordSize;
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if (prologue_offset_ == -1) {
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prologue_offset_ = CodeSize();
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}
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// Save volatile CPU and FPU registers on the stack:
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// -------------
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// FPU Registers
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// CPU Registers
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// RA
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// FP
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// -------------
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// TODO(zra): It may be a problem for walking the stack that FP is below
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// the saved registers. If it turns out to be a problem in the
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// future, try pushing RA and FP before the volatile registers.
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addiu(SP, SP, Immediate(-kPushedRegistersSize));
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for (int i = kDartFirstVolatileFpuReg; i <= kDartLastVolatileFpuReg; i++) {
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// These go above the volatile CPU registers.
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const int slot =
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(i - kDartFirstVolatileFpuReg) + kDartVolatileCpuRegCount + 2;
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FRegister reg = static_cast<FRegister>(i);
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swc1(reg, Address(SP, slot * kWordSize));
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}
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for (int i = kDartFirstVolatileCpuReg; i <= kDartLastVolatileCpuReg; i++) {
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// + 2 because FP goes in slot 0.
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const int slot = (i - kDartFirstVolatileCpuReg) + 2;
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Register reg = static_cast<Register>(i);
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sw(reg, Address(SP, slot * kWordSize));
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}
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sw(RA, Address(SP, 1 * kWordSize));
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sw(FP, Address(SP, 0 * kWordSize));
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mov(FP, SP);
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ReserveAlignedFrameSpace(frame_space);
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}
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void Assembler::LeaveCallRuntimeFrame() {
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const intptr_t kPushedRegistersSize =
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kDartVolatileCpuRegCount * kWordSize +
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2 * kWordSize + // FP and RA.
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kDartVolatileFpuRegCount * kWordSize;
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|
|
|
// SP might have been modified to reserve space for arguments
|
|
// and ensure proper alignment of the stack frame.
|
|
// We need to restore it before restoring registers.
|
|
mov(SP, FP);
|
|
|
|
// Restore volatile CPU and FPU registers from the stack.
|
|
lw(FP, Address(SP, 0 * kWordSize));
|
|
lw(RA, Address(SP, 1 * kWordSize));
|
|
for (int i = kDartFirstVolatileCpuReg; i <= kDartLastVolatileCpuReg; i++) {
|
|
// + 2 because FP goes in slot 0.
|
|
const int slot = (i - kDartFirstVolatileCpuReg) + 2;
|
|
Register reg = static_cast<Register>(i);
|
|
lw(reg, Address(SP, slot * kWordSize));
|
|
}
|
|
for (int i = kDartFirstVolatileFpuReg; i <= kDartLastVolatileFpuReg; i++) {
|
|
// These go above the volatile CPU registers.
|
|
const int slot =
|
|
(i - kDartFirstVolatileFpuReg) + kDartVolatileCpuRegCount + 2;
|
|
FRegister reg = static_cast<FRegister>(i);
|
|
lwc1(reg, Address(SP, slot * kWordSize));
|
|
}
|
|
addiu(SP, SP, Immediate(kPushedRegistersSize));
|
|
}
|
|
|
|
|
|
int32_t Assembler::AddExternalLabel(const ExternalLabel* label) {
|
|
if (object_pool_.IsNull()) {
|
|
// The object pool cannot be used in the vm isolate.
|
|
ASSERT(Isolate::Current() != Dart::vm_isolate());
|
|
object_pool_ = GrowableObjectArray::New(Heap::kOld);
|
|
}
|
|
const word address = label->address();
|
|
ASSERT(Utils::IsAligned(address, 4));
|
|
// The address is stored in the object array as a RawSmi.
|
|
const Smi& smi = Smi::Handle(Smi::New(address >> kSmiTagShift));
|
|
// Do not reuse an existing entry, since each reference may be patched
|
|
// independently.
|
|
object_pool_.Add(smi, Heap::kOld);
|
|
return object_pool_.Length() - 1;
|
|
}
|
|
|
|
|
|
void Assembler::Stop(const char* message) {
|
|
if (FLAG_print_stop_message) {
|
|
UNIMPLEMENTED();
|
|
}
|
|
Label stop;
|
|
b(&stop);
|
|
Emit(reinterpret_cast<int32_t>(message));
|
|
Bind(&stop);
|
|
break_(Instr::kStopMessageCode);
|
|
}
|
|
|
|
} // namespace dart
|
|
|
|
#endif // defined TARGET_ARCH_MIPS
|
|
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