regis@google.com
5675b85979
RFC: First draft showing how generated ARM code accesses GC'ed objects and accesses patched call targets. Review URL: https://codereview.chromium.org//12224024 git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18200 260f80e4-7a28-3924-810f-c04153c831b5
645 lines
22 KiB
C++
645 lines
22 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#ifndef VM_ASSEMBLER_ARM_H_
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#define VM_ASSEMBLER_ARM_H_
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#ifndef VM_ASSEMBLER_H_
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#error Do not include assembler_arm.h directly; use assembler.h instead.
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#endif
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#include "platform/assert.h"
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#include "platform/utils.h"
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#include "vm/constants_arm.h"
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namespace dart {
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class Label : public ValueObject {
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public:
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Label() : position_(0) { }
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~Label() {
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// Assert if label is being destroyed with unresolved branches pending.
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ASSERT(!IsLinked());
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}
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// Returns the position for bound and linked labels. Cannot be used
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// for unused labels.
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int Position() const {
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ASSERT(!IsUnused());
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return IsBound() ? -position_ - kWordSize : position_ - kWordSize;
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}
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bool IsBound() const { return position_ < 0; }
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bool IsUnused() const { return position_ == 0; }
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bool IsLinked() const { return position_ > 0; }
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private:
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int position_;
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void Reinitialize() {
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position_ = 0;
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}
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void BindTo(int position) {
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ASSERT(!IsBound());
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position_ = -position - kWordSize;
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ASSERT(IsBound());
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}
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void LinkTo(int position) {
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ASSERT(!IsBound());
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position_ = position + kWordSize;
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ASSERT(IsLinked());
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}
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friend class Assembler;
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DISALLOW_COPY_AND_ASSIGN(Label);
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};
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class CPUFeatures : public AllStatic {
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public:
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static void InitOnce() { }
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static bool double_truncate_round_supported() {
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UNIMPLEMENTED();
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return false;
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}
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};
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// Encodes Addressing Mode 1 - Data-processing operands.
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class ShifterOperand : public ValueObject {
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public:
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// Data-processing operands - Uninitialized.
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ShifterOperand() : type_(-1) { }
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// Data-processing operands - Copy constructor.
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ShifterOperand(const ShifterOperand& other)
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: ValueObject(), type_(other.type_), encoding_(other.encoding_) { }
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// Data-processing operands - Assignment operator.
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ShifterOperand& operator=(const ShifterOperand& other) {
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type_ = other.type_;
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encoding_ = other.encoding_;
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return *this;
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}
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// Data-processing operands - Immediate.
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explicit ShifterOperand(uint32_t immediate) {
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ASSERT(immediate < (1 << kImmed8Bits));
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type_ = 1;
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encoding_ = immediate;
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}
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// Data-processing operands - Rotated immediate.
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ShifterOperand(uint32_t rotate, uint32_t immed8) {
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ASSERT((rotate < (1 << kRotateBits)) && (immed8 < (1 << kImmed8Bits)));
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type_ = 1;
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encoding_ = (rotate << kRotateShift) | (immed8 << kImmed8Shift);
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}
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// Data-processing operands - Register.
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explicit ShifterOperand(Register rm) {
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type_ = 0;
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encoding_ = static_cast<uint32_t>(rm);
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}
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// Data-processing operands - Logical shift/rotate by immediate.
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ShifterOperand(Register rm, Shift shift, uint32_t shift_imm) {
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ASSERT(shift_imm < (1 << kShiftImmBits));
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type_ = 0;
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encoding_ = shift_imm << kShiftImmShift |
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static_cast<uint32_t>(shift) << kShiftShift |
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static_cast<uint32_t>(rm);
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}
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// Data-processing operands - Logical shift/rotate by register.
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ShifterOperand(Register rm, Shift shift, Register rs) {
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type_ = 0;
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encoding_ = static_cast<uint32_t>(rs) << kShiftRegisterShift |
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static_cast<uint32_t>(shift) << kShiftShift | (1 << 4) |
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static_cast<uint32_t>(rm);
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}
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static bool CanHold(uint32_t immediate, ShifterOperand* shifter_op) {
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// Avoid the more expensive test for frequent small immediate values.
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if (immediate < (1 << kImmed8Bits)) {
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shifter_op->type_ = 1;
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shifter_op->encoding_ = (0 << kRotateShift) | (immediate << kImmed8Shift);
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return true;
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}
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// Note that immediate must be unsigned for the test to work correctly.
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for (int rot = 0; rot < 16; rot++) {
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uint32_t imm8 = (immediate << 2*rot) | (immediate >> (32 - 2*rot));
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if (imm8 < (1 << kImmed8Bits)) {
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shifter_op->type_ = 1;
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shifter_op->encoding_ = (rot << kRotateShift) | (imm8 << kImmed8Shift);
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return true;
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}
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}
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return false;
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}
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private:
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bool is_valid() const { return (type_ == 0) || (type_ == 1); }
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uint32_t type() const {
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ASSERT(is_valid());
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return type_;
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}
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uint32_t encoding() const {
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ASSERT(is_valid());
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return encoding_;
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}
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uint32_t type_; // Encodes the type field (bits 27-25) in the instruction.
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uint32_t encoding_;
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friend class Assembler;
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};
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enum LoadOperandType {
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kLoadSignedByte,
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kLoadUnsignedByte,
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kLoadSignedHalfword,
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kLoadUnsignedHalfword,
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kLoadWord,
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kLoadWordPair,
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kLoadSWord,
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kLoadDWord
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};
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enum StoreOperandType {
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kStoreByte,
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kStoreHalfword,
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kStoreWord,
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kStoreWordPair,
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kStoreSWord,
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kStoreDWord
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};
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// Load/store multiple addressing mode.
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enum BlockAddressMode {
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// bit encoding P U W
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DA = (0|0|0) << 21, // decrement after
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IA = (0|4|0) << 21, // increment after
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DB = (8|0|0) << 21, // decrement before
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IB = (8|4|0) << 21, // increment before
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DA_W = (0|0|1) << 21, // decrement after with writeback to base
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IA_W = (0|4|1) << 21, // increment after with writeback to base
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DB_W = (8|0|1) << 21, // decrement before with writeback to base
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IB_W = (8|4|1) << 21 // increment before with writeback to base
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};
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class Address : public ValueObject {
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public:
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// Memory operand addressing mode
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enum Mode {
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// bit encoding P U W
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Offset = (8|4|0) << 21, // offset (w/o writeback to base)
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PreIndex = (8|4|1) << 21, // pre-indexed addressing with writeback
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PostIndex = (0|4|0) << 21, // post-indexed addressing with writeback
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NegOffset = (8|0|0) << 21, // negative offset (w/o writeback to base)
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NegPreIndex = (8|0|1) << 21, // negative pre-indexed with writeback
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NegPostIndex = (0|0|0) << 21 // negative post-indexed with writeback
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};
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Address(const Address& other) : ValueObject(), encoding_(other.encoding_) { }
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Address& operator=(const Address& other) {
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encoding_ = other.encoding_;
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return *this;
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}
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explicit Address(Register rn, int32_t offset = 0, Mode am = Offset) {
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ASSERT(Utils::IsAbsoluteUint(12, offset));
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if (offset < 0) {
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encoding_ = (am ^ (1 << kUShift)) | -offset; // Flip U to adjust sign.
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} else {
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encoding_ = am | offset;
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}
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encoding_ |= static_cast<uint32_t>(rn) << kRnShift;
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}
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static bool CanHoldLoadOffset(LoadOperandType type, int offset);
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static bool CanHoldStoreOffset(StoreOperandType type, int offset);
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private:
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uint32_t encoding() const { return encoding_; }
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// Encoding for addressing mode 3.
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uint32_t encoding3() const;
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// Encoding for vfp load/store addressing.
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uint32_t vencoding() const;
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uint32_t encoding_;
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friend class Assembler;
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};
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class FieldAddress : public Address {
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public:
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FieldAddress(Register base, int32_t disp)
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: Address(base, disp - kHeapObjectTag) { }
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FieldAddress(const FieldAddress& other) : Address(other) { }
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FieldAddress& operator=(const FieldAddress& other) {
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Address::operator=(other);
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return *this;
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}
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};
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class Assembler : public ValueObject {
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public:
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Assembler()
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: buffer_(),
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object_pool_(GrowableObjectArray::Handle(GrowableObjectArray::New())),
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prologue_offset_(-1),
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comments_() { }
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~Assembler() { }
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void PopRegister(Register r) { Pop(r); }
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void Bind(Label* label);
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// Misc. functionality
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int CodeSize() const { return buffer_.Size(); }
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int prologue_offset() const { return prologue_offset_; }
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const ZoneGrowableArray<int>& GetPointerOffsets() const {
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ASSERT(buffer_.pointer_offsets().length() == 0); // No pointers in code.
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return buffer_.pointer_offsets();
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}
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const GrowableObjectArray& object_pool() const {
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return object_pool_;
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}
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void FinalizeInstructions(const MemoryRegion& region) {
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buffer_.FinalizeInstructions(region);
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ASSERT(object_pool_.Length() == 0); // TODO(regis): Otherwise, more work.
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}
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// Debugging and bringup support.
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void Stop(const char* message);
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void Unimplemented(const char* message);
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void Untested(const char* message);
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void Unreachable(const char* message);
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static void InitializeMemoryWithBreakpoints(uword data, int length);
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void Comment(const char* format, ...) PRINTF_ATTRIBUTE(2, 3);
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const Code::Comments& GetCodeComments() const;
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static const char* RegisterName(Register reg) {
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UNIMPLEMENTED();
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return NULL;
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}
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static const char* FpuRegisterName(FpuRegister reg) {
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UNIMPLEMENTED();
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return NULL;
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}
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// Data-processing instructions.
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void and_(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void eor(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void sub(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void subs(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void rsb(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void rsbs(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void add(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void adds(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void adc(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void sbc(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void rsc(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void tst(Register rn, ShifterOperand so, Condition cond = AL);
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void teq(Register rn, ShifterOperand so, Condition cond = AL);
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void cmp(Register rn, ShifterOperand so, Condition cond = AL);
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void cmn(Register rn, ShifterOperand so, Condition cond = AL);
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void orr(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void orrs(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void mov(Register rd, ShifterOperand so, Condition cond = AL);
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void movs(Register rd, ShifterOperand so, Condition cond = AL);
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void bic(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
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void mvn(Register rd, ShifterOperand so, Condition cond = AL);
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void mvns(Register rd, ShifterOperand so, Condition cond = AL);
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// Miscellaneous data-processing instructions.
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void clz(Register rd, Register rm, Condition cond = AL);
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void movw(Register rd, uint16_t imm16, Condition cond = AL);
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void movt(Register rd, uint16_t imm16, Condition cond = AL);
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// Multiply instructions.
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void mul(Register rd, Register rn, Register rm, Condition cond = AL);
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void mla(Register rd, Register rn, Register rm, Register ra,
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Condition cond = AL);
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void mls(Register rd, Register rn, Register rm, Register ra,
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Condition cond = AL);
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void umull(Register rd_lo, Register rd_hi, Register rn, Register rm,
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Condition cond = AL);
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// Load/store instructions.
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void ldr(Register rd, Address ad, Condition cond = AL);
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void str(Register rd, Address ad, Condition cond = AL);
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void ldrb(Register rd, Address ad, Condition cond = AL);
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void strb(Register rd, Address ad, Condition cond = AL);
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void ldrh(Register rd, Address ad, Condition cond = AL);
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void strh(Register rd, Address ad, Condition cond = AL);
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void ldrsb(Register rd, Address ad, Condition cond = AL);
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void ldrsh(Register rd, Address ad, Condition cond = AL);
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void ldrd(Register rd, Address ad, Condition cond = AL);
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void strd(Register rd, Address ad, Condition cond = AL);
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void ldm(BlockAddressMode am, Register base,
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RegList regs, Condition cond = AL);
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void stm(BlockAddressMode am, Register base,
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RegList regs, Condition cond = AL);
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void ldrex(Register rd, Register rn, Condition cond = AL);
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void strex(Register rd, Register rt, Register rn, Condition cond = AL);
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// Miscellaneous instructions.
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void clrex();
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void nop(Condition cond = AL);
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// Note that gdb sets breakpoints using the undefined instruction 0xe7f001f0.
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void bkpt(uint16_t imm16);
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void svc(uint32_t imm24);
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// Floating point instructions (VFPv3-D16 and VFPv3-D32 profiles).
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void vmovsr(SRegister sn, Register rt, Condition cond = AL);
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void vmovrs(Register rt, SRegister sn, Condition cond = AL);
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void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL);
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void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL);
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void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL);
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void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL);
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void vmovs(SRegister sd, SRegister sm, Condition cond = AL);
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void vmovd(DRegister dd, DRegister dm, Condition cond = AL);
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// Returns false if the immediate cannot be encoded.
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bool vmovs(SRegister sd, float s_imm, Condition cond = AL);
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bool vmovd(DRegister dd, double d_imm, Condition cond = AL);
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void vldrs(SRegister sd, Address ad, Condition cond = AL);
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void vstrs(SRegister sd, Address ad, Condition cond = AL);
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void vldrd(DRegister dd, Address ad, Condition cond = AL);
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void vstrd(DRegister dd, Address ad, Condition cond = AL);
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void vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
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void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
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void vsubs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
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void vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
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void vmuls(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
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void vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
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void vmlas(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
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void vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
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void vmlss(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
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void vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
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void vdivs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
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void vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
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void vabss(SRegister sd, SRegister sm, Condition cond = AL);
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void vabsd(DRegister dd, DRegister dm, Condition cond = AL);
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void vnegs(SRegister sd, SRegister sm, Condition cond = AL);
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void vnegd(DRegister dd, DRegister dm, Condition cond = AL);
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void vsqrts(SRegister sd, SRegister sm, Condition cond = AL);
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void vsqrtd(DRegister dd, DRegister dm, Condition cond = AL);
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void vcvtsd(SRegister sd, DRegister dm, Condition cond = AL);
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void vcvtds(DRegister dd, SRegister sm, Condition cond = AL);
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void vcvtis(SRegister sd, SRegister sm, Condition cond = AL);
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void vcvtid(SRegister sd, DRegister dm, Condition cond = AL);
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void vcvtsi(SRegister sd, SRegister sm, Condition cond = AL);
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void vcvtdi(DRegister dd, SRegister sm, Condition cond = AL);
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void vcvtus(SRegister sd, SRegister sm, Condition cond = AL);
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void vcvtud(SRegister sd, DRegister dm, Condition cond = AL);
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void vcvtsu(SRegister sd, SRegister sm, Condition cond = AL);
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void vcvtdu(DRegister dd, SRegister sm, Condition cond = AL);
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void vcmps(SRegister sd, SRegister sm, Condition cond = AL);
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void vcmpd(DRegister dd, DRegister dm, Condition cond = AL);
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void vcmpsz(SRegister sd, Condition cond = AL);
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void vcmpdz(DRegister dd, Condition cond = AL);
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void vmstat(Condition cond = AL); // VMRS APSR_nzcv, FPSCR
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// Branch instructions.
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void b(Label* label, Condition cond = AL);
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void bl(Label* label, Condition cond = AL);
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void blx(Register rm, Condition cond = AL);
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// Macros.
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// Branch to an entry address that can be patched at runtime.
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void Branch(const ExternalLabel* label);
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void BranchLink(const ExternalLabel* label);
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// Branch to entry after setting LR and storing LR at ad.
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void BranchLinkStore(const ExternalLabel* label, Address ad);
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// Branch to [base + offset] after setting LR.
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void BranchLinkOffset(Register base, int offset);
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// Add signed constant value to rd. May clobber IP.
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void AddConstant(Register rd, int32_t value, Condition cond = AL);
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void AddConstant(Register rd, Register rn, int32_t value,
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Condition cond = AL);
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void AddConstantSetFlags(Register rd, Register rn, int32_t value,
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Condition cond = AL);
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void AddConstantWithCarry(Register rd, Register rn, int32_t value,
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Condition cond = AL);
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// Load and Store. May clobber IP.
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void LoadImmediate(Register rd, int32_t value, Condition cond = AL);
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void LoadSImmediate(SRegister sd, float value, Condition cond = AL);
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void LoadDImmediate(DRegister dd, double value,
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Register scratch, Condition cond = AL);
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void MarkExceptionHandler(Label* label);
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void LoadObject(Register rd, const Object& object);
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void LoadFromOffset(LoadOperandType type,
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Register reg,
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Register base,
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int32_t offset,
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Condition cond = AL);
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void StoreToOffset(StoreOperandType type,
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Register reg,
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Register base,
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int32_t offset,
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Condition cond = AL);
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void LoadSFromOffset(SRegister reg,
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Register base,
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|
int32_t offset,
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|
Condition cond = AL);
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void StoreSToOffset(SRegister reg,
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Register base,
|
|
int32_t offset,
|
|
Condition cond = AL);
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void LoadDFromOffset(DRegister reg,
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|
Register base,
|
|
int32_t offset,
|
|
Condition cond = AL);
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void StoreDToOffset(DRegister reg,
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|
Register base,
|
|
int32_t offset,
|
|
Condition cond = AL);
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|
|
|
void Push(Register rd, Condition cond = AL);
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|
void Pop(Register rd, Condition cond = AL);
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|
|
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void PushList(RegList regs, Condition cond = AL);
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void PopList(RegList regs, Condition cond = AL);
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|
|
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void Mov(Register rd, Register rm, Condition cond = AL);
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|
|
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// Convenience shift instructions. Use mov instruction with shifter operand
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|
// for variants setting the status flags or using a register shift count.
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|
void Lsl(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL);
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void Lsr(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL);
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|
void Asr(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL);
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|
void Ror(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL);
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|
void Rrx(Register rd, Register rm, Condition cond = AL);
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|
|
|
// Emit data (e.g encoded instruction or immediate) in instruction stream.
|
|
void Emit(int32_t value);
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|
|
|
private:
|
|
AssemblerBuffer buffer_; // Contains position independent code.
|
|
const GrowableObjectArray& object_pool_; // Objects and jump targets.
|
|
int32_t prologue_offset_;
|
|
|
|
int32_t AddObject(const Object& obj);
|
|
int32_t AddExternalLabel(const ExternalLabel* label);
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|
|
|
class CodeComment : public ZoneAllocated {
|
|
public:
|
|
CodeComment(intptr_t pc_offset, const String& comment)
|
|
: pc_offset_(pc_offset), comment_(comment) { }
|
|
|
|
intptr_t pc_offset() const { return pc_offset_; }
|
|
const String& comment() const { return comment_; }
|
|
|
|
private:
|
|
intptr_t pc_offset_;
|
|
const String& comment_;
|
|
|
|
DISALLOW_COPY_AND_ASSIGN(CodeComment);
|
|
};
|
|
|
|
GrowableArray<CodeComment*> comments_;
|
|
|
|
void EmitType01(Condition cond,
|
|
int type,
|
|
Opcode opcode,
|
|
int set_cc,
|
|
Register rn,
|
|
Register rd,
|
|
ShifterOperand so);
|
|
|
|
void EmitType5(Condition cond, int offset, bool link);
|
|
|
|
void EmitMemOp(Condition cond,
|
|
bool load,
|
|
bool byte,
|
|
Register rd,
|
|
Address ad);
|
|
|
|
void EmitMemOpAddressMode3(Condition cond,
|
|
int32_t mode,
|
|
Register rd,
|
|
Address ad);
|
|
|
|
void EmitMultiMemOp(Condition cond,
|
|
BlockAddressMode am,
|
|
bool load,
|
|
Register base,
|
|
RegList regs);
|
|
|
|
void EmitShiftImmediate(Condition cond,
|
|
Shift opcode,
|
|
Register rd,
|
|
Register rm,
|
|
ShifterOperand so);
|
|
|
|
void EmitShiftRegister(Condition cond,
|
|
Shift opcode,
|
|
Register rd,
|
|
Register rm,
|
|
ShifterOperand so);
|
|
|
|
void EmitMulOp(Condition cond,
|
|
int32_t opcode,
|
|
Register rd,
|
|
Register rn,
|
|
Register rm,
|
|
Register rs);
|
|
|
|
void EmitVFPsss(Condition cond,
|
|
int32_t opcode,
|
|
SRegister sd,
|
|
SRegister sn,
|
|
SRegister sm);
|
|
|
|
void EmitVFPddd(Condition cond,
|
|
int32_t opcode,
|
|
DRegister dd,
|
|
DRegister dn,
|
|
DRegister dm);
|
|
|
|
void EmitVFPsd(Condition cond,
|
|
int32_t opcode,
|
|
SRegister sd,
|
|
DRegister dm);
|
|
|
|
void EmitVFPds(Condition cond,
|
|
int32_t opcode,
|
|
DRegister dd,
|
|
SRegister sm);
|
|
|
|
void EmitBranch(Condition cond, Label* label, bool link);
|
|
static int32_t EncodeBranchOffset(int offset, int32_t inst);
|
|
static int DecodeBranchOffset(int32_t inst);
|
|
int32_t EncodeTstOffset(int offset, int32_t inst);
|
|
int DecodeTstOffset(int32_t inst);
|
|
|
|
// Returns whether or not the given register is used for passing parameters.
|
|
static int RegisterCompare(const Register* reg1, const Register* reg2) {
|
|
return *reg1 - *reg2;
|
|
}
|
|
|
|
DISALLOW_ALLOCATION();
|
|
DISALLOW_COPY_AND_ASSIGN(Assembler);
|
|
};
|
|
|
|
} // namespace dart
|
|
|
|
#endif // VM_ASSEMBLER_ARM_H_
|