Commit Graph

141 Commits

Author SHA1 Message Date
johnmccutchan@google.com 635ba4bbd9 Port flow_graph*, disassembler to ISL_Print
BUG=
R=srdjan@google.com

Review URL: https://codereview.chromium.org//907093002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@43609 260f80e4-7a28-3924-810f-c04153c831b5
2015-02-09 20:49:32 +00:00
srdjan@google.com 12c5e2bbaf Cleanup: use const reference for ParsedFunction where possible.
R=rmacnak@google.com

Review URL: https://codereview.chromium.org//878243002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@43226 260f80e4-7a28-3924-810f-c04153c831b5
2015-01-28 00:41:09 +00:00
srdjan@google.com 110a74f954 Cleanups: parsed_function()->function() => function()
R=johnmccutchan@google.com

Review URL: https://codereview.chromium.org//881063003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@43213 260f80e4-7a28-3924-810f-c04153c831b5
2015-01-27 22:09:31 +00:00
koda@google.com 99127744c6 Add Zone-based handle allocation interface and reduce use of Isolate-based interfaces.
Remove deprecated Isolate-based BitVector constructor.

R=asiva@google.com

Review URL: https://codereview.chromium.org//868913002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@43136 260f80e4-7a28-3924-810f-c04153c831b5
2015-01-26 14:54:02 +00:00
koda@google.com 280dc6fbd4 Introduce simple Thread class to support gradual refactoring of interfaces.
This first iteration of Thread just forwards a subset of the BaseIsolate methods.

The plan is to first add Thread/Zone-based interfaces where appropriate, deprecate their Isolate-based versions, and finally remove them once all callsites have been migrated.

This CL only demonstrates a small part of this migration, for BitVector and some of the compiler classes. There are thousands of additional call-sites that will need to be updated.

R=asiva@google.com

Review URL: https://codereview.chromium.org//850183005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@43073 260f80e4-7a28-3924-810f-c04153c831b5
2015-01-22 14:14:16 +00:00
koda@google.com 33b55e64e4 Isolate/Thread split: Isolate -> Zone for LocationSummary.
The isolate was being passed around, even though only its current zone was used.

Pass that zone directly instead, giving two benefits:
1. helps prepare for the upcoming Isolate/Thread split, where "new(isolate)" must go, and
2. saves a pointer indirection at the allocation sites.

Review URL: https://codereview.chromium.org//855533002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42935 260f80e4-7a28-3924-810f-c04153c831b5
2015-01-15 21:29:57 +00:00
srdjan@google.com bad6a61899 Cleanups.
R=vegorov@google.com

Review URL: https://codereview.chromium.org//774763002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42069 260f80e4-7a28-3924-810f-c04153c831b5
2014-12-02 18:48:12 +00:00
fschneider@google.com 876193b31a Make CTX allocatable by the register allocator.
This change makes CTX available by not caching the current
context while in Dart code. Instead the current context
is held in a local variable (:saved_current_context_var) and
is passed as argument in CTX at calls.

This also simplifies a lot of code in the debugger: As a result,
Isolate::top_context is not needed anymore since the current context
can always be extracted from a Dart frame.

R=vegorov@google.com

Review URL: https://codereview.chromium.org//678763004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@41422 260f80e4-7a28-3924-810f-c04153c831b5
2014-10-30 15:42:38 +00:00
vegorov@google.com 3f5c8471bf Keep list of uses sorted when building it.
We were violating sorting at instructions that use the same value as both fixed register input and an unallocated one producing a list that contained use at P, followed by a use at P-1.

This would later cause a problem when we split live-range at P-1 and spill [..., P-1) prefix.

Use at P-1 would be attributed to unspilled part of the range leading to completely incorrect parallel move at P-1: [rx <- S+X, ry <- rx], where rx - is the aforementioned fixed register and ry is a register selected for an unallocated use of the value.

R=srdjan@google.com
BUG=

Review URL: https://codereview.chromium.org//601103004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40681 260f80e4-7a28-3924-810f-c04153c831b5
2014-09-25 17:10:06 +00:00
srdjan@google.com b8891bf412 Pass isolate to BitVector constructor.
R=hausner@google.com

Review URL: https://codereview.chromium.org//587873003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40528 260f80e4-7a28-3924-810f-c04153c831b5
2014-09-19 23:14:34 +00:00
fschneider@google.com da0fb6bbe2 More intrinsics in IR.
R=srdjan@google.com, vegorov@google.com, zra@google.com

Review URL: https://codereview.chromium.org//513213002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40088 260f80e4-7a28-3924-810f-c04153c831b5
2014-09-10 13:34:58 +00:00
vegorov@google.com 33b533e564 Fix register hinting for phis.
The way it was implemented did not always work for phis for live ranges extending past the loop, because the hint itself stayed uncoverted until after register allocation inside the loop was completed.

For the loop like this:

f() {
  var x = 1.0,  y = 2.0;
  for (var i = 0; i < 100; i++) x += y;
  return x;
}

That used to generate:

loop:
  cmp ecx,0xc8
  jnl ->exit
  mov xmm3, xmm2
  addsd xmm3, xmm1
  mov xmm2, xmm3
  add ecx,0x2
  jmp ->loop

With this change we generate:

loop:
  cmp ecx,0xc8
  jnl ->exit
  addsd xmm2,xmm1
  add ecx,0x2
  jmp ->loop

R=fschneider@google.com
BUG=

Review URL: https://codereview.chromium.org//556453006

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40024 260f80e4-7a28-3924-810f-c04153c831b5
2014-09-09 11:26:58 +00:00
vegorov@google.com 2d9907c88c Ensure that BoxInt32 input is correctly preserved on the slow-path.
Register allocator is unable to preserve writable registers automatically because they behave like temps: have no fixed represenation or usage inside the instruction template.

This means writable registers have to be manually added with the right representation to the live_register set when necessary.

Add verification that checks this and fix existing misuses.

R=fschneider@google.com
BUG=

Review URL: https://codereview.chromium.org//517343002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@39703 260f80e4-7a28-3924-810f-c04153c831b5
2014-08-29 15:19:51 +00:00
vegorov@google.com 9f9e250e92 Support Int32 representation for selected binary operations.
BUG=
R=fschneider@google.com

Review URL: https://codereview.chromium.org//504143003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@39595 260f80e4-7a28-3924-810f-c04153c831b5
2014-08-27 14:49:19 +00:00
vegorov@google.com 77c26187f2 Support allocation sinking for compound objects.
- Improve escape/alias analysis:
-- Storing an object into a field of another object does not mean that this object escapes (or has aliases) as long as that object does not have any loads from the same place;
-- Places like X.f and Y.f don't alias if X and Y are two different allocation instructions even if X and Y themselves potentially have aliases;
-- Improve precision of alias analysis for indexed properties;

- Support dematerialization and rematerialization of objects that are referenced by other dematerialized objects.
-- Use fix-point algorithm to collect candidates for allocation sinking;
-- Support aborting unsuccessful allocation sinking.

R=fschneider@google.com, johnmccutchan@google.com

Review URL: https://codereview.chromium.org//395943003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38404 260f80e4-7a28-3924-810f-c04153c831b5
2014-07-18 18:35:08 +00:00
johnmccutchan@google.com 92330fbc32 Support SameAsFirstInput policy in register allocator when inputs are paired machine registers
BUG=
R=vegorov@google.com

Review URL: https://codereview.chromium.org//393323004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38290 260f80e4-7a28-3924-810f-c04153c831b5
2014-07-16 16:45:10 +00:00
johnmccutchan@google.com 2ebd74a740 Add Uint32 representation.
- Add new representation: kUnboxedUint32.
- Add BinaryUint32Op, UnaryUint32Op, ShiftUint32Op instructions.
- Add new optimization pass which replaces Mint instructions with Uint32 instructions when possible.
- IA32 completed.
- ARM completed.

R=fschneider@google.com, vegorov@google.com, zra@google.com

Review URL: https://codereview.chromium.org//345563007

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38198 260f80e4-7a28-3924-810f-c04153c831b5
2014-07-14 17:01:02 +00:00
vegorov@google.com 00daaa6106 Don't assign safepoint at the definition to the definition's live-range.
This avoids treating spill slot associated with the definition live during GC as
it will only be filled in after definition's code is fully executed.

Additionally this makes output register dead for GC inside the definiton itself
which is something we used to guarantee manually by removing it from the
live_registers set before calling on the slow path.

BUG=
R=fschneider@google.com

Review URL: https://codereview.chromium.org//375693004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38059 260f80e4-7a28-3924-810f-c04153c831b5
2014-07-08 14:12:00 +00:00
iposva@google.com 3878793b10 - Reduce the number of Isolate::Current() calls.
R=johnmccutchan@google.com

Review URL: https://codereview.chromium.org//296003013

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@36564 260f80e4-7a28-3924-810f-c04153c831b5
2014-05-23 12:07:33 +00:00
johnmccutchan@google.com 8f4cbeaefa Use GPRs for mints.
Changes:

* Register allocator now allocates GPRs for kUnboxedMint.
* Register allocator supports for SameAsFirstInput for register pairs.
* Register allocator properly handles register pairs in environment uses and materialization uses.
* BoxInteger updated on IA32/ARM.
* UnboxInteger updated on IA32/ARM.
* BinaryMintOp updated on IA32/ARM.
* ShiftMintOp updated on IA32/ARM.
* UnaryMintOp updated on IA32/ARM.
* RelationalOp updated on IA32/ARM.
* EqualityCompare updated on IA32/ARM.
* LoadIndexed and StoreIndexed updated on IA32/ARM.
* New Deopt instructions added.
* Update live_registers when an instruction has a fixed register input and a call on the slow path.
* Improve printing of register pairs in flow graph.
* Do not assume live registers in slow paths contain tagged values.
* LiveRange pairs for kUnboxedMint definitions marked as kUntagged representation (reduces stack usage).
* Live register spilling on ARM uses same register order as stack map encoding.
* Spill slots containing tagged and untagged are segregated.
* Print stack maps when printing live ranges with safe points.
* Print allocated spill slot when printing live ranges.

Status:

* IA32 completed. All tests are passing.
* ARM completed. All tests passing.

R=fschneider@google.com, srdjan@google.com, zra@google.com

Review URL: https://codereview.chromium.org//252333002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@36468 260f80e4-7a28-3924-810f-c04153c831b5
2014-05-22 06:30:51 +00:00
srdjan@google.com 25bab2bb3b Another fix in register allocation where th eimplicit assumption is that numebr of CPU registers is equal or greater than number of FPU registers.
R=johnmccutchan@google.com

Review URL: https://codereview.chromium.org//289133003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@36267 260f80e4-7a28-3924-810f-c04153c831b5
2014-05-16 18:57:22 +00:00
srdjan@google.com 7ba400fc44 Fix register allocator to properly allocate containers.
R=hausner@google.com

Review URL: https://codereview.chromium.org//286973011

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@36264 260f80e4-7a28-3924-810f-c04153c831b5
2014-05-16 18:21:04 +00:00
ngeoffray@google.com e3f17ce842 Code is truly a no-op. Previous failure was due to a leftover printf statement.
R=fschneider@google.com

Review URL: https://codereview.chromium.org//268743004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@35789 260f80e4-7a28-3924-810f-c04153c831b5
2014-05-06 08:19:49 +00:00
ngeoffray@google.com c5672f5c39 Remove debugging code.
Review URL: https://codereview.chromium.org//267793004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@35685 260f80e4-7a28-3924-810f-c04153c831b5
2014-05-02 09:20:18 +00:00
ngeoffray@google.com eea043b4dc Revert r35682, one test is failing: standalone/io/process_sync_test. Code may actually be changing something.
Review URL: https://codereview.chromium.org//262823007

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@35683 260f80e4-7a28-3924-810f-c04153c831b5
2014-05-02 09:17:28 +00:00
ngeoffray@google.com 24fa40e0b8 Remove code that has no effect: live_outs are always empty at this stage.
R=fschneider@google.com, vegorov@google.com

Review URL: https://codereview.chromium.org//257273003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@35682 260f80e4-7a28-3924-810f-c04153c831b5
2014-05-02 08:56:11 +00:00
zra@google.com 2348d3ebd1 Teaches the register allocator about a second assembler temporary.
ARM64 explicitly has two assembler temporaries that fall in the
middle of the range of registers that Dart may otherwise use. To
comply with this convention, the register allocator must
recognize two TMP registers. I've called the added one TMP2,
but I'm open to suggestions for other names.

R=regis@google.com

Review URL: https://codereview.chromium.org//239283003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@35070 260f80e4-7a28-3924-810f-c04153c831b5
2014-04-15 18:01:51 +00:00
johnmccutchan@google.com 1eb7046d00 Restore WritableRegister input LiveRange shape
BUG=
R=zra@google.com

Review URL: https://codereview.chromium.org//229143002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@34838 260f80e4-7a28-3924-810f-c04153c831b5
2014-04-08 20:25:22 +00:00
johnmccutchan@google.com 3834c9a869 Support for multiple register values
- Adds a PairLocation type (Location is still a single word but now has two tags one for constants and one for pairs).
- New representations: kPairOfTagged & kPairOfUnboxedDouble.
- Register allocator uses second SSA index for Definitions that use two registers.
- Fix LiveRange shape for kWritableRegister inputs.
- Updated MergedMathInstr that returns a kPairOfTagged or kPairOfUnboxedDouble (depending on the merged math kind).
- A new instruction (ExtractNthOutput) for extracting a single register from an instruction that has a output register pair.

Open issues that need to be addressed in a follow up CL:

- Adjust PhiInstr and handling of PhiInstr in the register allocator to work with output pairs (once unboxed mints are in GPRs).

R=fschneider@google.com, srdjan@google.com

Review URL: https://codereview.chromium.org//215363004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@34833 260f80e4-7a28-3924-810f-c04153c831b5
2014-04-08 16:13:43 +00:00
johnmccutchan@google.com e255df56ed Refactor to support multiple outputs in location summary
R=srdjan@google.com

Review URL: https://codereview.chromium.org//207063002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@34250 260f80e4-7a28-3924-810f-c04153c831b5
2014-03-21 14:40:30 +00:00
johnmccutchan@google.com ed5894d0cf Unbox/Box Float64x2 and inline typed array loads and stores
R=fschneider@google.com

Review URL: https://codereview.chromium.org//172653002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32869 260f80e4-7a28-3924-810f-c04153c831b5
2014-02-20 20:41:54 +00:00
fschneider@google.com 893b25e5b4 Revert r31601 (Use constants from the frame at OSR entry...).
Because this CL also changed the way spill slots are allocated for
catch entry blocks it caused invalid code for optimized try-catch
under certain conditions.

R=srdjan@google.com

Review URL: https://codereview.chromium.org//141163009

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@31948 260f80e4-7a28-3924-810f-c04153c831b5
2014-01-20 10:43:41 +00:00
fschneider@google.com c414fbf2ca Use constants from the frame at OSR entry.
The code for reserving stack slots for OSR entry values is shared with the
code for reserving stack slots for try/catch. It does not handle them
optimally (reserving slots above the desired ones and copying them down,
instead of directly reserving the desired one). This CL simplifies allocation
of spill slots for try-catch as well.

This is an rebased version of Kevin's original CL
(https://codereview.chromium.org/102173003/).
I removed an invalid assertion and removed more code that became unnecessary
with this change.

R=srdjan@google.com

Review URL: https://codereview.chromium.org//125943002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@31601 260f80e4-7a28-3924-810f-c04153c831b5
2014-01-08 11:27:10 +00:00
fschneider@google.com 6abd6e326e Add mutable double boxes for fields.
This allows the optimizing compiler to generate unboxed loads/stores
to fields containing double values. The double value is stored
in a reusable double object.

Unboxed loads/stores are generated for optimized code. Unoptimized code
allocates a new double on loads. To avoid performance regressions
for fields that are only written few times (e.g. only in the constructor)
I put a heuristic in place that
compares the usage count of setters and getters. Unboxed operations
are only generated if the setter is invoked a significant amount of
times (threshold is 10% of getter invocations).

The CL is so big because it changes the way LocationSummmary
is allocated: We now have a bit to generate different summaries
for optimized and unoptimized code.

R=srdjan@google.com

Review URL: https://codereview.chromium.org//99573005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@31164 260f80e4-7a28-3924-810f-c04153c831b5
2013-12-16 15:11:31 +00:00
johnmccutchan@google.com 29c01044bc This is the final breaking change in dart:typed_data needed for Dart 1.0. We need this change because the ECMAScript SIMD specification only includes Int32x4 and Int32x4List and our types must match.
R=srdjan@google.com

Review URL: https://codereview.chromium.org//56023004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@29849 260f80e4-7a28-3924-810f-c04153c831b5
2013-11-04 21:56:59 +00:00
jacobr@google.com 605b33c1bc fix cpp11 compile errors
R=asiva@google.com

Review URL: https://codereview.chromium.org//23072026

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@26387 260f80e4-7a28-3924-810f-c04153c831b5
2013-08-20 20:24:11 +00:00
fschneider@google.com 2793f7ad63 Fix bug with optimized try-catch on ARM/MIPS.
The constant pool pointer must be restored before any parallel
moves at the catch-entry block.

In addition, this CL removes CatchEntryInstr and folds its
functionality into CatchBlockEntryInstr. Until now every catch-block
started with CatchBlockEntryInstr followed by a CatchEntryInstr.

This simplifies a lot of code in the compiler and avoids issues
with allocator-move code inserted between the two instructions.

BUG=https://code.google.com/p/dart/issues/detail?id=12291
TEST=tests/language/try_catch4_test.dart
R=regis@google.com, srdjan@google.com

Review URL: https://codereview.chromium.org//22590002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25918 260f80e4-7a28-3924-810f-c04153c831b5
2013-08-08 08:20:10 +00:00
fschneider@google.com 5e6dfa2cc3 Fix register allocation bug in building use intervals.
This bug was only exposed on ARM, but can be a problem
on other platforms as well.

When building the use intervals for a value that
is used more than once at one instruction, the use
interval was not adjusted correctly: Under certain
conditions the resulting interval can be too short.
It can occur when the first use is a writable register use,
and the second use is a normal register use.
This CL grows the use intervals to the correct size
in that case.

BUG=https://code.google.com/p/dart/issues/detail?id=11800
TEST=tests/language/regress_11800_test.dart
R=vegorov@google.com

Review URL: https://codereview.chromium.org//22412002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25810 260f80e4-7a28-3924-810f-c04153c831b5
2013-08-06 12:43:09 +00:00
fschneider@google.com 1745be4209 Fix bug in register allocation at catch entry blocks.
The registers used to pass the exception and the stacktrace values
need to be blocked at catch block entry until after the CatchEntry
instruction which stores them into local variables.

R=vegorov@google.com

Review URL: https://codereview.chromium.org//17232004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24105 260f80e4-7a28-3924-810f-c04153c831b5
2013-06-17 17:35:00 +00:00
kmillikin@google.com 3e78b2ad4a Reapply "Initial implementation of on-stack replacement (OSR)."
This reapplies SVN r24024 with a bugfix.

After OSR compilation, restore the pre-OSR code (which might be already
optimized) rather than the unoptimized code (which might have its entry
patched).  When the optimized code entry is patched it is only safe to call
it as a static call, not as an instance call.

R=fschneider@google.com

Review URL: https://codereview.chromium.org//17233003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24088 260f80e4-7a28-3924-810f-c04153c831b5
2013-06-17 11:05:15 +00:00
kmillikin@google.com d6f3eccdf2 Revert "Initial implementation of on-stack replacement (OSR)."
This reverts commit 24024.

TBR=fschneider@google.com

Review URL: https://codereview.chromium.org//16888013

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24025 260f80e4-7a28-3924-810f-c04153c831b5
2013-06-14 10:30:53 +00:00
kmillikin@google.com 0b39927d30 Initial implementation of on-stack replacement (OSR).
Add profiling support to select OSR candidates and launch the compiler
for OSR, followed by entry to the function at the OSR entry point.

Implemented only on IA32 and X64.  The initial implementation can be
improved in various ways --- specifically: tuning of profiling
parameters and incorporation of feedback about the actual values seen
at OSR entry.

R=fschneider@google.com

Review URL: https://codereview.chromium.org//16693006

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24024 260f80e4-7a28-3924-810f-c04153c831b5
2013-06-14 10:10:55 +00:00
fschneider@google.com 8ad125f607 Optimize functions containing try-catch.
This is a first step towards fully optimizing try-catch-finally.

At a catch entry, all local variables and parameters are
expected at a fixed stack location. There is a list of
initial definitions at the catch entry block, similar to
the initial definitions at graph entry.

Inside every try-block there is a special prologue code before each
call (instruction that may throw) inside the try-block. This prologue
is similar to a parallel move instruction: It moves all locals+parameters
to the locations expected by the catch-entry block. The stack frame
is extended with the corresponding number of fixed slots right below
the normal spill slots.

Every function containing try-catch has additional compiler-
generated local variables to pass the context, the exception and
the stack trace.

Variable liveness analysis is adapted to treat locals inside try{} blocks
specially: Every call has an implicit LoadLocal of every local variable.
This CL uses a safe approximiation of liveness which can be optimized further.

Current restrictions which are planned for future CLs:
 * No inlining inside try-blocks.
 * No inlining of functions containing try-catch.
 * No try-finally yet.

R=kmillikin@google.com

Review URL: https://codereview.chromium.org//14682020

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22615 260f80e4-7a28-3924-810f-c04153c831b5
2013-05-13 10:33:24 +00:00
vegorov@google.com 2565ca222f Implement a variation of scalar replacement for non-escaping allocations.
AllocationSinking pass discovers non-escaping allocations that have no input uses other than uses in the stores into its own fields.

Every environment use of such allocation is replaced by a state snapshot (MaterializeObject instruction) that describes the state of each initialized field in the object. State snapshots are computed through an additional round of load-forwarding.

Once snapshots are computed allocations are removed from the graph.

MaterializeObject instructions are not compiled into native code but produce deoptimization instructions instead that describe how object should be materialized at deoptimization.

Deoptimization instructions now follow the following format:

[mat obj #1]...[mat obj #N][ret addr][... mat arguments ...][... real frames ...]

- the prefix describes each object to materialize on deopt via kMaterializeObject instruction;
- actual values that are needed for materialization are emited as a part of bottom-most stack frame. This is done to simplify implementation: they need to be discoverable by a GC during materialization phase. At the end of deoptimization they will be removed from the stack;
- normal stack slots can refer to materialized objects via kMaterializedObjectRef instruction.

Additionally this change contains fixes in load-forwarding that are needed to guarantee that all artificial LoadField instructions inserted during AllocationSinking are correctly replaced with actual values.

Limitations of the current implementation:

- can't eliminate allocations that flow into phis but otherwise don't actually escape;
- can't sink allocations out of loops;
- allocation with type arguments are not handled.

R=regis@google.com, srdjan@google.com, zra@google.com

Review URL: https://codereview.chromium.org//14935005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22485 260f80e4-7a28-3924-810f-c04153c831b5
2013-05-07 23:40:42 +00:00
kmillikin@google.com 7e31a88a0a Initial support for polymorphic inlining.
Consider each polymorphic variant separately for inlining in frequency
order.  Share inlined bodies for shared targets.

Insert an SSA redefinition of the receiver in each inlined variant to
prevent hoisting.  Hoisting code specialized to the receiver (e.g.,
direct access to internal fields of typed data arrays) out of the
inlined body is not safe.

R=fschneider@google.com, srdjan@google.com

Review URL: https://codereview.chromium.org//14740005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22434 260f80e4-7a28-3924-810f-c04153c831b5
2013-05-06 17:22:18 +00:00
vegorov@google.com 8607801589 Ensure that safepoints are assigned to the live ranges of constants.
R=fschneider@google.com
BUG=dart:10272

Review URL: https://codereview.chromium.org//14542004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22124 260f80e4-7a28-3924-810f-c04153c831b5
2013-04-29 15:51:15 +00:00
vegorov@google.com 81ecaba321 Re-apply r20377.
Compute local variable liveness before translation to SSA.

Use it to remove dead values from deoptimization environments.

R=fschneider@google.com
BUG=

Review URL: https://codereview.chromium.org//14215006

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21439 260f80e4-7a28-3924-810f-c04153c831b5
2013-04-15 11:53:50 +00:00
vegorov@google.com 4d4a91ac04 Fix bug in ParallelMoveResolver::EmitSwap: implement swaps of FPU spill slots.
Remove representation from location. Presence of representation in location encoding was violating the invariant that unequal locations must be disjoint (where equality for locations is defined in terms of bitwise equality of their encoding). This could lead ParallelMoveResolver to treat XMM1 containing unboxed double as unequal location to XMM1 containing unboxed mint, which is obviously incorrect.

For similar reason eliminate kFloat32x4StackSlot and kUint32x4StackSlot distinction is eliminated and both are replaced with kQuadStackSlot. Register allocator now guarantees that no kQuadStackSlot occupies the same space as any other kDoubleStackSlot. This also shrinks optimized stack when only doubles are used (but might lead to a higher stack utilization when a mixture of doubles and quads is used).

Implement allocation of scratch Cpu and Xmm registers for ParallelMoveResolver. This also allows to remove push(eax)/pop(eax) pairs when resolving memory-memory cycles on ia32.

BUG=dart:9710

Review URL: https://codereview.chromium.org//13801014

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21148 260f80e4-7a28-3924-810f-c04153c831b5
2013-04-09 12:23:46 +00:00
johnmccutchan@google.com 7e1450cb9b Flow graph SIMD changes
Review URL: https://codereview.chromium.org//13471013

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20945 260f80e4-7a28-3924-810f-c04153c831b5
2013-04-04 23:23:30 +00:00
vegorov@google.com 535ed8eb25 Revert "Compute local variable liveness before translation to SSA."
Attaching environments to branches on strict comparisons breaks pattern matching in the optimizer and regresses performance.

This reverts commit r20377.

TBR=kmillikin@google.com

Review URL: https://codereview.chromium.org//12827027

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20400 260f80e4-7a28-3924-810f-c04153c831b5
2013-03-22 18:32:17 +00:00