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46 Commits

Author SHA1 Message Date
Ryan Macnak 883f25ff08 Use the Code's pointer offsets to find object references when disassembling IA32. 
Attempt to de-flake language/disassemble_test by removing a heap walk.

R=fschneider@google.com

Review URL: https://codereview.chromium.org/2160343003 .
 2016-07-19 17:25:36 -07:00
Ryan Macnak 85cdc0eac2 Don't assume we want the iOS ABI if running simarm on Mac and the EABI otherwise. 
Allow controlling the target ABI by defining TARGET_ABI_IOS or TARGET_ABI_EABI.  If neither is defined, default to the previous behavior.

Make Linux, Mac, Android and iOS agree on the value of PreferredCodeAlignment for all architectures.

BUG=http://dartbug.com/26464
R=zra@google.com

Review URL: https://codereview.chromium.org/1982613003 .
 2016-05-17 15:03:54 -07:00
John McCutchan e2e7af1229 Remove more feature in product mode 
- Remove Timeline.
- Remove more vmservice code.
- Remove AST printing.
- Remove IL printing.
- Remove profiler.
- Remove thread interrupter.
- Remove disassembler.
- Remove Library::CheckFunctionFingerprints.

- Update test status files for product mode.

Size of dart_bootstrap before: 5287631
Size of dart_bootstrap after: 5112783

Reduction in size: 174848 bytes.

Total reduction in size (382734 + 174848): 557582 bytes.

R=rmacnak@google.com

Review URL: https://codereview.chromium.org/1678203002 .
 2016-02-09 08:45:32 -08:00
Ryan Macnak d422888b46 Use the iOS ABI when running SIMARM on Mac or targeting iOS. 
Linux / iOS
R7   preserved / FP
R9   preserved / volatile
R11  FP / preserved

BUG=http://dartbug.com/24683
R=zra@google.com

Review URL: https://codereview.chromium.org/1421253004 .
 2015-10-27 14:36:38 -07:00
Ryan Macnak dd7250323d Re-assign registers on ARM so PP and CODE_REG are below R7 (FP on iOS). 
Also update descriptions of register availability in instrinsics.

1) Mechanical replacement in *arm.* files except the simulator and constants_arm.h (with sed).

R5 -> R9
R6 -> R8
R8 -> R10
R9 -> R5
R10 -> R6

2) Change register aliases.

CTX = R10 -> CTX = R6
PP = R9 -> PP = R5
ICREG = R5 -> ICREG = R9
CODE_REG = R10 -> CODE_REG = R6
THR = R8 -> THR = R10

3) Fixup users of ldrd/strd to have valid register pairs.

bigint_lsh
bigint_absadd
bigint_abssub
bigint_sqradd
TYPED_ARRAY_ALLOCATION
InlineArrayAllocation
AllocateArrayStub
AllocateContextStub

4) Fix PushList in MegamorphicMissStub to keep runtime call arguments in the right order.

BUG=http://dartbug.com/24683
R=fschneider@google.com

Review URL: https://codereview.chromium.org/1419223003 .
 2015-10-26 11:05:32 -07:00
Florian Schneider bac82e2592 VM: New calling convention for generated code. 
Instead of calling code object directly, call indirectly and
pass the code object in a register. The object pool is then loaded from
the code object. This is another preparation step for making generated code
relocatable.

All non-ia32 platforms:
No entry patching.

ARM:
PC marker (now code object) moves to the same place as on x64 (below saved PP, above saved FP).
R9 is now used as PP, R10 as CODE_REG.

BUG=
R=koda@google.com, rmacnak@google.com

Committed: https://github.com/dart-lang/sdk/commit/1d343e5a7b75168fb6c9f86b64c55173cdbdc9b2

Review URL: https://codereview.chromium.org//1192103004 .
 2015-09-19 13:21:09 +02:00
Florian Schneider 7af7a2db87 Revert "VM: New calling convention for generated code." 
This reverts commit 1d343e5a7b.

Because of Windows test failures.

BUG=
TBR=whesse@google.com

Review URL: https://codereview.chromium.org//1343373003 .
 2015-09-16 13:46:05 +02:00
Florian Schneider 1d343e5a7b VM: New calling convention for generated code. 
Instead of calling code object directly, call indirectly and
pass the code object in a register. The object pool is then loaded from
the code object. This is another preparation step for making generated code
relocatable.

All non-ia32 platforms:
No entry patching.

ARM:
PC marker (now code object) moves to the same place as on x64 (below saved PP, above saved FP).
R9 is now used as PP, R10 as CODE_REG.

BUG=
R=rmacnak@google.com

Review URL: https://codereview.chromium.org//1192103004 .
 2015-09-16 13:05:58 +02:00
regis@google.com 2e2bcf6149 Use a breakpoint instruction for a stop message on arm instead of 
a svc instruction (or hlt instruction on arm64).
The instructions svc and hlt are used in conjunction with a simulator only.
At least, gdb now stops on armv5te when hitting a stop message (no prompt).
Add support for printing stop message in disassembly on mips and arm64.
Clean up various bkpt codes on arm (now similar to arm64 and mips).

R=zra@google.com

Review URL: https://codereview.chromium.org//1097413004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@45363 260f80e4-7a28-3924-810f-c04153c831b5
 2015-04-22 20:45:52 +00:00
zra@google.com 9eaea2e779 Fixes ARM instruction version checking. 
Emulates umaal on ARMv5TE.

Review URL: https://codereview.chromium.org//1062593003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@44940 260f80e4-7a28-3924-810f-c04153c831b5
 2015-04-07 17:36:46 +00:00
srdjan@google.com 4c8545557a Add inlining ranges/intervals to code objects so that we can map a pc to the inlined stack. The mapping is not fast, used only for disassembly. 
Copied from other CL: https://codereview.chromium.org/790213004/

Review URL: https://codereview.chromium.org//817823002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42522 260f80e4-7a28-3924-810f-c04153c831b5
 2014-12-19 20:03:27 +00:00
zra@google.com f3a21e3ff3 Uses correct mnemonic for vmrs instructions. 
Keeps vmstat as a macro.

R=iposva@google.com

Review URL: https://codereview.chromium.org//647523002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@41042 260f80e4-7a28-3924-810f-c04153c831b5
 2014-10-10 15:30:41 +00:00
regis@google.com 632edf5d55 Implement bigint mulAdd and sqrAdd intrinsics on ARM. 
Add support for umaal instruction on ARM (assembler, disassembler, simulator).
Add assembler test for umaal instruction on ARM.

R=johnmccutchan@google.com, zra@google.com

Review URL: https://codereview.chromium.org//638983002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40993 260f80e4-7a28-3924-810f-c04153c831b5
 2014-10-08 16:59:59 +00:00
zra@google.com c6f380ed3d Avoids vmovsr on ARM. 
R=johnmccutchan@google.com, regis@google.com

Review URL: https://codereview.chromium.org//606893002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40696 260f80e4-7a28-3924-810f-c04153c831b5
 2014-09-25 22:09:26 +00:00
zra@google.com b39bcf7bf6 Allows unboxed doubles to be disabled. 
This helps to support ARMv5TE. Also adds asserts to
ensure that neon and vfp instructions are not generated
when those features are disabled on ARM.

R=srdjan@google.com

Review URL: https://codereview.chromium.org//292433008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@36262 260f80e4-7a28-3924-810f-c04153c831b5
 2014-05-16 17:17:52 +00:00
zra@google.com c323e2ac13 Implements unboxed Mints on ARM. 
R=johnmccutchan@google.com, regis@google.com

Review URL: https://codereview.chromium.org//206503005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@34256 260f80e4-7a28-3924-810f-c04153c831b5
 2014-03-21 16:26:21 +00:00
jacobr@google.com 605b33c1bc fix cpp11 compile errors 
R=asiva@google.com

Review URL: https://codereview.chromium.org//23072026

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@26387 260f80e4-7a28-3924-810f-c04153c831b5
 2013-08-20 20:24:11 +00:00
zra@google.com 8f3e8783f8 Implements the two argument shuffle SIMD instruction for ARM. 
R=regis@google.com

Review URL: https://codereview.chromium.org//21004011

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25638 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-30 20:49:22 +00:00
zra@google.com dd9adc1a86 Adds more SIMD instructions for ARM. 
Adds the vnegqs, vabsqs, and vandq instructions.

Also reverts the increase in the number of floating point registers since it is causing crashes on hardware.

R=regis@google.com

Review URL: https://codereview.chromium.org//19493004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25320 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-22 23:26:12 +00:00
zra@google.com 4b97f8c18c Adds reciprocal squre root SIMD instructions for ARM. 
R=regis@google.com

Review URL: https://codereview.chromium.org//19875002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25291 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-22 18:19:44 +00:00
zra@google.com a15bac1044 Adds ARM SIMD instructions. 
vminqs, maxqs, vrecpeqs (Reciprocal estimate), vrecpsqs (Reciprocal Newton-Raphson step).

R=regis@google.com

Review URL: https://codereview.chromium.org//19773017

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25245 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-19 21:32:03 +00:00
zra@google.com 18f6092d52 Implements ARM SIMD comparison instructions. 
R=regis@google.com

Review URL: https://codereview.chromium.org//19678020

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25189 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-18 22:56:45 +00:00
zra@google.com d886c10f6e Enables a SIMD test for ARM. 
Required adding the veorq, vmovq, and vdup instructions.

R=regis@google.com

Review URL: https://codereview.chromium.org//19776007

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25165 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-18 18:40:27 +00:00
zra@google.com 4731ad6b71 Adds the vtbl ARM SIMD instruction. 
It is needed for the Float32x4ShuffleInstr of the intermediate language.

R=regis@google.com

Review URL: https://codereview.chromium.org//19400003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25073 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-16 21:18:26 +00:00
zra@google.com 3cebda38e6 Merges ARM load/store type enums into one enum. 
R=regis@google.com

Review URL: https://codereview.chromium.org//19256021

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25064 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-16 18:32:40 +00:00
zra@google.com 344b295eee Implements ARM SIMD multiplication and subtraction instructions. 
R=regis@google.com

Review URL: https://codereview.chromium.org//19290006

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25052 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-16 16:13:56 +00:00
zra@google.com f219f81b14 Begins implementation of ARM neon instructions. 
Just adds the vadd instruction, but also changes the
arm assembler to expose the Q registers rather than the
D registers. Q0 = D1:D0 = S3:S2:S1:S0. This is similar
to how ia32 and x64 use only the xmm registers for
floating point.

R=regis@google.com

Review URL: https://codereview.chromium.org//18684008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24982 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-12 23:22:50 +00:00
regis@google.com 3711825476 Fix Random_nextState intrinsic on ARM. 
R=zra@google.com

Review URL: https://codereview.chromium.org//18054006

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24548 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-27 20:16:53 +00:00
zra@google.com e5229295a0 Removes ARM mrc instruction. 
It is a privileged instruction and was only being used in tests
running on the simulator.

R=regis@google.com

Review URL: https://codereview.chromium.org//16194010

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23367 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-29 21:31:27 +00:00
zra@google.com 26fa41d1b1 Implements intrinsics for ARM. 
R=regis@google.com

Review URL: https://codereview.chromium.org//15822008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23311 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-28 22:55:51 +00:00
zra@google.com fabc87d633 Fixes for integer division on ARM hardware so that assembler tests pass. 
Now, all VM tests that pass on SIMARM, pass on ARM.

Also, more assertions in the ARM disassembler and simulator to
make sure that condition codes aren't used with bkpt.

R=regis@google.com

Review URL: https://codereview.chromium.org//14784011

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22471 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-07 18:21:18 +00:00
regis@google.com ad6005e5c4 Support debugger API on ARM. 
Support smull ARM instruction in order to detect 32-bit multiplication overflow.
Enable debugger api tests on ARM.
Enable isolate tests on ARM.
Enable code descriptors tests on ARM.
Enable snapshot tests on ARM.
Enable heap tests on ARM.

Review URL: https://codereview.chromium.org//13983016

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21890 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-23 16:10:22 +00:00
zra@google.com f6da1febeb Drops into Simulator Debugger only in a session that is already interactive. 
This change backs out an earlier change to the disassemblers that
made them return false if an instruction couldn't be decoded.
This was used in the simulator debuggers for arm and mips to avoid
executing an instruction that couldn't be decoded.

Instead, now when an unknown instruction is encountered in the simulator,
if the simulator is running interactively, we drop into
the debugger, and otherwise die. We detect that a simulator is
running interactively by setting a flag if we enter the debugger
for a user set break point.
Review URL: https://codereview.chromium.org//12903006

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20394 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-22 18:11:05 +00:00
zra@google.com 82367b380d Copies Simulator Debugger from ARM to MIPS. 
Also includes changes to keep it from aborting unexpectedly.
Among other things, I changed the Disassembler::Disassemble to return false
when the underlying decoder can't decode an instruction. Then,
the MIPS SimulatorDebugger will refuse to step or cont on an instruction
that the Disassembler can't decode.
Review URL: https://codereview.chromium.org//12431016

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19958 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-13 18:43:16 +00:00
iposva@google.com f507e542de - Add a skeleton MIPS assembler, disassembler and simulator. 
- Remove unused fields and methods from ARM simulator.
- Remove unused 5th parameter from Simulator::Call.
Review URL: https://codereview.chromium.org//12541003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19606 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-07 11:04:27 +00:00
zra@google.com 31da7d6c55 Adds muls, sdiv, udiv instructions to ARM simulator, assembler, disassembler 
Review URL: https://codereview.chromium.org//12459005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19511 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-05 19:53:43 +00:00
zra@google.com c9c0881ac7 Adds mrc instruction to arm simulator, assembler, disassembler. 
This instruction will be used to query an arm processor to
determine whether it supports the sdiv and udiv instructions.

Also adds a flag --sim_has_int_div to the arm simulator,
which changes the result of the mrc instruction so we can
test both ways.
Review URL: https://codereview.chromium.org//12378080

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19439 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-05 01:03:22 +00:00
regis@google.com a879bba2ff Second codegen test passing on ARM (simulated). 
This required support on ARM for:
- compilation of static calls
- patching of static calls
- stub to call into runtime
- redirection support for calls from simulator to host runtime
- stack frame iteration
Review URL: https://codereview.chromium.org//12381034

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19405 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-04 18:08:38 +00:00
zra@google.com 767b8ec8fc Adds vstm, vldm to ARM simulator, assembler, disassembler 
Review URL: https://codereview.chromium.org//12390039

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19404 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-04 17:45:38 +00:00
regis@google.com 3b374ead4b Compile and simulate first dart function on arm generated from ast. 
Review URL: https://codereview.chromium.org//12335102

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19152 260f80e4-7a28-3924-810f-c04153c831b5
 2013-02-27 17:13:51 +00:00
regis@google.com 8d24d2b98a Implement ARM disassembler. 
Implement ARM call patcher.
Review URL: https://codereview.chromium.org//12301042

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18769 260f80e4-7a28-3924-810f-c04153c831b5
 2013-02-20 17:28:35 +00:00
regis@google.com 912194a756 Fix vm code base so that it can be built for --arch=simarm (no snapshot yet). 
Review URL: https://codereview.chromium.org//11956004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@17246 260f80e4-7a28-3924-810f-c04153c831b5
 2013-01-18 00:34:20 +00:00
sgjesse@google.com 65896148c9 Move utils.h and utils.cc from runtime/vm to runtime/platform 
Moved additional parts of globals.h from vm/ to platform/ to support
types and constants used by utils.*.

R=ager@google.com, iposva@google.com

BUG=
TEST=

Review URL: http://codereview.chromium.org//9209001

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@3337 260f80e4-7a28-3924-810f-c04153c831b5
 2012-01-16 13:23:40 +00:00
sgjesse@google.com bf67f24098 Move assert.h/assert.cc from runtime/vm to runtime/platform 
The purpose of this change is twofold:

1. Source in the bin directory can now use the same assertions as
   source in the vm directory. The ASSERT macro used by the code
   in runtime/bin was just defined to use assert from the standard
   C library.
2. Moving other implementation parts from runtime/vm to
   runtime/platform (e.g. classes Monitor and Mutex) for sharing
   between runtime/bin and runtime/vm will be easier as these
   implementations rely on these assertion macros.

Created two gypi files for the platform directory. One for the
headers and one for the source. The source one is only included
when building the VM library and will be present in libdart.a
when the dart executable is linked.

All the code for asserts is still in the dart namespace.

Also re-arranged the order of includes to be alphabetically in
the files touched.

R=ager@google.com, iposva@google.com

BUG=
TEST=

Review URL: http://codereview.chromium.org//9189003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@3335 260f80e4-7a28-3924-810f-c04153c831b5
 2012-01-16 12:28:10 +00:00
regis@google.com d55fe56fcc Disassembler for x64. 
Review URL: http://codereview.chromium.org//8758005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@1953 260f80e4-7a28-3924-810f-c04153c831b5
 2011-11-30 23:12:46 +00:00
dgrove@google.com 4c0f559d23 Initial checkin. 
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@15 260f80e4-7a28-3924-810f-c04153c831b5
 2011-10-05 05:20:07 +00:00