In addition to tracking input and output ranges in the IC-stubs with a Smi fastpath (SmiAdd and SmiSub, currently) this CL also introduces two IC stubs that have no fast-path by still track ranges and update the range feedback.
We are able to distinguish between the following ranges (encoding of the lattice is shown in the parens):
- u-smi (0000)
- smi (0001)
- uint31 (0010)
- int32 (0011)
- uint32 (0100)
- int64 (1xxx) and (x1x1)
BUG=
R=fschneider@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//735543003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42370 260f80e4-7a28-3924-810f-c04153c831b5
First steps towards general pretenuring support.
* Generalize Heap::Top/EndAddress.
* Add testing flag to exercise new code paths.
* Also update the slow-case runtime calls, to ensure a fresh block will be allocated in old.
Next steps are general invalidation of the generated code and adding a policy that doesn't blow up the store buffers), and freelist allocation.
Review URL: https://codereview.chromium.org//578443003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40530 260f80e4-7a28-3924-810f-c04153c831b5
Previous implementation changed input representation depending on the propagated type of the value which violated assumptions made by SelectRepresentations phase.
Instead of using tagged/mint input require unboxed Int32/Uint32 input and insert explicit truncating unboxing when building StoreIndexed operation in the optimizer. This also leads to strictly better code and opens possibilities for further optimizations.
Implement Int32/Uint32 representation support on all platforms. This includes boxing, unboxing and unboxed converter operations.
Merge BoxInt32/BoxUint32 and UnboxInt32/UnboxUint32 instruction sequences to minimize duplication.
Improve instruction sequences by utilizing CARRY flag set by smi untagging where possible (ARM, ia32, x86).
Enable all tests that were disabled by r40078, r40079.
BUG=http://dartbug.com/20875R=fschneider@google.com, johnmccutchan@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//552303005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40143 260f80e4-7a28-3924-810f-c04153c831b5
1. Deopts on division when neither vfp nor idiv are present.
In a subsequent CL, I can add a leaf runtime call for this.
2. Uses a different PC read offset in STR and STM instructions.
On ARMv5 and earlier, the PC read offset is 8 except in STR
and STM instructions, where it is implementation defined. On
lego mindstorm it is 12. This requires changing
kEntryPointToPcMarkerOffset to be a function.
3. Uses a dummy struct to compute the size of a compressed
pc descriptor to avoid alignment issues. sizeof(PcDescriptorRec)
is 16 on ia32 and arm. Subtracting sizeof(int16_t) gives 14,
which creates alignment problems on ARM, i.e. poor performance on
ARMv6 and later, and wrong results on ARMv5 and earlier.
R=regis@google.com
Review URL: https://codereview.chromium.org//467103005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@39250 260f80e4-7a28-3924-810f-c04153c831b5
This change generate inline code for context allocation and makes
the stores to initialize the parent pointer and the context variables
explicit in the optimized flow graph. This allows dead store elimination
to eliminate those stores.
Before, we only had inlined context allocation for ia32.
Furthermore:
* Added an assertion that the exit label of slow-path code
is bound when emitting deferred code. This used to cause random crashes
if forgotten.
* Fixed a bug in allocation stats on ARM.
BUG=dartbug.com/17238
R=srdjan@google.com
Review URL: https://codereview.chromium.org//346823003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@39202 260f80e4-7a28-3924-810f-c04153c831b5
Avoid reloading the class-id at the entry to last inlined variant at
inlined polymorphic call sites. For this I added a new check instruction
CheckClassIdInstr to deoptimize on integer-comparison.
In polymorphic CheckClass with small dense ranges of class-ids now generate
max. 2 branch instructions by doing a range check and computing a test mask
instead of a sequence of compare and branch instructions.
I fixed the crash bug which was due to illegal hoisting of CheckClassId and
two more assertion failures.
R=vegorov@google.com
Review URL: https://codereview.chromium.org//381803005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38154 260f80e4-7a28-3924-810f-c04153c831b5
Avoid reloading the class-id at the entry to last inlined variant at
inlined polymorphic call sites. For this I added a new check instruction
CheckClassIdInstr to deoptimize on integer-comparison.
In polymorphic CheckClass with small dense ranges of class-ids now generate
max. 2 branch instructions by doing a range check and computing a test mask
instead of a sequence of compare and branch instructions.
R=johnmccutchan@google.com
Review URL: https://codereview.chromium.org//181183004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38116 260f80e4-7a28-3924-810f-c04153c831b5
Change executable pages to be read/execute but not writable by default.
All pages are made temporarily writable just before a full GC, because both
the mark and sweep phases write to the pages. When allocating in a page and
when patching code, the pages are made temporarily writable.
The order of allocation of Code and Instructions objects is changed so that
a GC will not occur after Instructions is allocated. (A full GC would
render the Instructions unwritable.) A scoped object is used to make memory
protection simpler.
Original CL: https://codereview.chromium.org/106593002/
I added a cc test that is expected to crash.
R=srdjan@google.com
Review URL: https://codereview.chromium.org//136563002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32493 260f80e4-7a28-3924-810f-c04153c831b5
This change rewrites the code from the ARM assembler for parsing /proc/cpuinfo on Linux and Android, and collects it into a CpuInfo class that can be used for other architectures as well. This code is in cpuinfo_*.cc. /proc/cpuinfo equivalents are used for Mac and Windows. CpuInfo is used by the VM service to report on the hardware dart is running on. In the future CpuInfo can also be used here to provide more information.
R=iposva@google.com, johnmccutchan@google.com
Review URL: https://codereview.chromium.org//120723003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32468 260f80e4-7a28-3924-810f-c04153c831b5
Instead of emitting a large smi constant directly as an immediate, xor the
smi with a random 32-bit cookie at compile time, emit code to move that into
a register and then to xor the register with the cookie.
1. In unoptimized code constants are always loaded into a register in
ConstantInstr::EmitNativeCode. Change it to load safely.
2. In optimized code constants loaded into a register for use by an
instruction are loaded by ParallelMoveResolver::EmitMove. Change it to
load safely.
3. In optimized code some instructions allow constants as inputs. These are
reflected with an input location of Location::RegisterOrConstant (or
similar) or else Location::Constant. For the former allocate a register
if the constant is unsafe, and for the latter check for safety before
allowing the constant input.
BUG=https://code.google.com/p/dart/issues/detail?id=1742R=iposva@google.com, srdjan@google.com
Review URL: https://codereview.chromium.org//48743002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@29439 260f80e4-7a28-3924-810f-c04153c831b5
koda@google.com