Instead of using RawObject* as keys, use Object*. Using handles eliminates any assumption
about the underlying GC implementation (e.g. requiring that old objects don't move).
Remove special handling of null_object by making HashMap more generic and
allowing the trait to specify the value used to indicate an empty element.
The goal is to use one unified, efficient implementation of the constant
pool on all architectures that require one (x64, arm64, mips).
R=vegorov@google.com, zra@google.com
Review URL: https://codereview.chromium.org//848703002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42901 260f80e4-7a28-3924-810f-c04153c831b5
In addition to tracking input and output ranges in the IC-stubs with a Smi fastpath (SmiAdd and SmiSub, currently) this CL also introduces two IC stubs that have no fast-path by still track ranges and update the range feedback.
We are able to distinguish between the following ranges (encoding of the lattice is shown in the parens):
- u-smi (0000)
- smi (0001)
- uint31 (0010)
- int32 (0011)
- uint32 (0100)
- int64 (1xxx) and (x1x1)
BUG=
R=fschneider@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//735543003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42370 260f80e4-7a28-3924-810f-c04153c831b5
Since Register is an enum type, it is automatically
coerced to integer types when passed as a parameter to
functions expecting an integer argument. This change
expands the use of Immediate and Operand wrappers
for Assembler instructions and macros to avoid this
automatic coercion.
I've also added dummy constructors to Address and
FieldAddress classes to address the same problem,
but in a way that does not increase verbosity,
since Address and FieldAddress are much more
prevalent in the code.
A cleaner solution would involve making Register
no longer coercable to integer types, but this
would likely require many changes to the Assemblers.
R=regis@google.com
Review URL: https://codereview.chromium.org//593363003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40905 260f80e4-7a28-3924-810f-c04153c831b5
First steps towards general pretenuring support.
* Generalize Heap::Top/EndAddress.
* Add testing flag to exercise new code paths.
* Also update the slow-case runtime calls, to ensure a fresh block will be allocated in old.
Next steps are general invalidation of the generated code and adding a policy that doesn't blow up the store buffers), and freelist allocation.
Review URL: https://codereview.chromium.org//578443003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40530 260f80e4-7a28-3924-810f-c04153c831b5
Previous implementation changed input representation depending on the propagated type of the value which violated assumptions made by SelectRepresentations phase.
Instead of using tagged/mint input require unboxed Int32/Uint32 input and insert explicit truncating unboxing when building StoreIndexed operation in the optimizer. This also leads to strictly better code and opens possibilities for further optimizations.
Implement Int32/Uint32 representation support on all platforms. This includes boxing, unboxing and unboxed converter operations.
Merge BoxInt32/BoxUint32 and UnboxInt32/UnboxUint32 instruction sequences to minimize duplication.
Improve instruction sequences by utilizing CARRY flag set by smi untagging where possible (ARM, ia32, x86).
Enable all tests that were disabled by r40078, r40079.
BUG=http://dartbug.com/20875R=fschneider@google.com, johnmccutchan@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//552303005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40143 260f80e4-7a28-3924-810f-c04153c831b5
1. Deopts on division when neither vfp nor idiv are present.
In a subsequent CL, I can add a leaf runtime call for this.
2. Uses a different PC read offset in STR and STM instructions.
On ARMv5 and earlier, the PC read offset is 8 except in STR
and STM instructions, where it is implementation defined. On
lego mindstorm it is 12. This requires changing
kEntryPointToPcMarkerOffset to be a function.
3. Uses a dummy struct to compute the size of a compressed
pc descriptor to avoid alignment issues. sizeof(PcDescriptorRec)
is 16 on ia32 and arm. Subtracting sizeof(int16_t) gives 14,
which creates alignment problems on ARM, i.e. poor performance on
ARMv6 and later, and wrong results on ARMv5 and earlier.
R=regis@google.com
Review URL: https://codereview.chromium.org//467103005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@39250 260f80e4-7a28-3924-810f-c04153c831b5
This change generate inline code for context allocation and makes
the stores to initialize the parent pointer and the context variables
explicit in the optimized flow graph. This allows dead store elimination
to eliminate those stores.
Before, we only had inlined context allocation for ia32.
Furthermore:
* Added an assertion that the exit label of slow-path code
is bound when emitting deferred code. This used to cause random crashes
if forgotten.
* Fixed a bug in allocation stats on ARM.
BUG=dartbug.com/17238
R=srdjan@google.com
Review URL: https://codereview.chromium.org//346823003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@39202 260f80e4-7a28-3924-810f-c04153c831b5
On these architectures it's preferable to load Scavenger address into the register and then access top/end fields through this register instead of loading addresses of those fields as immediates --- which takes either two instructions or a memory load through a pool pointer.
Cleanup boxing slow-paths in the optimizing compiler. We had tons of duplicated code that was essentially doing the same thing.
BUG=
R=johnmccutchan@google.com, regis@google.com
Review URL: https://codereview.chromium.org//410333003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38539 260f80e4-7a28-3924-810f-c04153c831b5
Changes:
* Register allocator now allocates GPRs for kUnboxedMint.
* Register allocator supports for SameAsFirstInput for register pairs.
* Register allocator properly handles register pairs in environment uses and materialization uses.
* BoxInteger updated on IA32/ARM.
* UnboxInteger updated on IA32/ARM.
* BinaryMintOp updated on IA32/ARM.
* ShiftMintOp updated on IA32/ARM.
* UnaryMintOp updated on IA32/ARM.
* RelationalOp updated on IA32/ARM.
* EqualityCompare updated on IA32/ARM.
* LoadIndexed and StoreIndexed updated on IA32/ARM.
* New Deopt instructions added.
* Update live_registers when an instruction has a fixed register input and a call on the slow path.
* Improve printing of register pairs in flow graph.
* Do not assume live registers in slow paths contain tagged values.
* LiveRange pairs for kUnboxedMint definitions marked as kUntagged representation (reduces stack usage).
* Live register spilling on ARM uses same register order as stack map encoding.
* Spill slots containing tagged and untagged are segregated.
* Print stack maps when printing live ranges with safe points.
* Print allocated spill slot when printing live ranges.
Status:
* IA32 completed. All tests are passing.
* ARM completed. All tests passing.
R=fschneider@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//252333002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@36468 260f80e4-7a28-3924-810f-c04153c831b5
mls, mla, umull, smull, etc. are not implemented on
all ARMv6's. This change works around them. For
mls and mla, we just use two instructions. smull
was used to check for overflow in mul, so we have
to do that manually. For umlal in the Random
intrinsic, we just fall through for now, though in
principal it wouldn't be hard to emulate.
R=regis@google.com
Review URL: https://codereview.chromium.org//255273003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@35550 260f80e4-7a28-3924-810f-c04153c831b5
Change executable pages to be read/execute but not writable by default.
All pages are made temporarily writable just before a full GC, because both
the mark and sweep phases write to the pages. When allocating in a page and
when patching code, the pages are made temporarily writable.
The order of allocation of Code and Instructions objects is changed so that
a GC will not occur after Instructions is allocated. (A full GC would
render the Instructions unwritable.) A scoped object is used to make memory
protection simpler.
Original CL: https://codereview.chromium.org/106593002/
I added a cc test that is expected to crash.
R=srdjan@google.com
Review URL: https://codereview.chromium.org//136563002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32493 260f80e4-7a28-3924-810f-c04153c831b5
fschneider@google.com