This fixes c13b481aeb.
IA32 does not load a constant pool and does not use the CODE_REG to
create the pc marker, so it does not need to preserve CODE_REG in
instrinsics. Blocking another register from graph instrinsics caused some of
them to need to spill, which is asserted to never happen.
R=fschneider@google.com
Review URL: https://codereview.chromium.org/1418813005 .
This enables thread-safe logging (e.g., ISL_Print, which will soon be renamed to THR_Print), which is needed for concurrent
marking (DetachCode) and compilation.
Make finalization of GC marking tasks concurrent, now that it's thread-safe.
BUG=
R=iposva@google.com
Review URL: https://codereview.chromium.org//1314673008 .
Add THR register that caches the current thread in generated code.
Shuffle some registers around as needed to free one up.
Note: Assembler::LoadIsolate now always loads the *current* isolate whenever the code is executed, rather than the isolate in which the code was compiled (no existing code was affected by this slight change in semantics).
Rewrite some ia32 stubs to use one less register, and for some ia32 bigint intrinsics, explicitly save THR (like CTX in the past, see r44699).
Next steps:
- pass current thread rather than isolate in NativeArguments
- ditto for exception handler jump
- migrate fields vm_tag, top_exit_frame_info, etc. to thread
R=srdjan@google.com
Review URL: https://codereview.chromium.org//1156593002
This first iteration of Thread just forwards a subset of the BaseIsolate methods.
The plan is to first add Thread/Zone-based interfaces where appropriate, deprecate their Isolate-based versions, and finally remove them once all callsites have been migrated.
This CL only demonstrates a small part of this migration, for BitVector and some of the compiler classes. There are thousands of additional call-sites that will need to be updated.
R=asiva@google.com
Review URL: https://codereview.chromium.org//850183005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@43073 260f80e4-7a28-3924-810f-c04153c831b5
The isolate was being passed around, even though only its current zone was used.
Pass that zone directly instead, giving two benefits:
1. helps prepare for the upcoming Isolate/Thread split, where "new(isolate)" must go, and
2. saves a pointer indirection at the allocation sites.
Review URL: https://codereview.chromium.org//855533002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42935 260f80e4-7a28-3924-810f-c04153c831b5
This change makes CTX available by not caching the current
context while in Dart code. Instead the current context
is held in a local variable (:saved_current_context_var) and
is passed as argument in CTX at calls.
This also simplifies a lot of code in the debugger: As a result,
Isolate::top_context is not needed anymore since the current context
can always be extracted from a Dart frame.
R=vegorov@google.com
Review URL: https://codereview.chromium.org//678763004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@41422 260f80e4-7a28-3924-810f-c04153c831b5
We were violating sorting at instructions that use the same value as both fixed register input and an unallocated one producing a list that contained use at P, followed by a use at P-1.
This would later cause a problem when we split live-range at P-1 and spill [..., P-1) prefix.
Use at P-1 would be attributed to unspilled part of the range leading to completely incorrect parallel move at P-1: [rx <- S+X, ry <- rx], where rx - is the aforementioned fixed register and ry is a register selected for an unallocated use of the value.
R=srdjan@google.com
BUG=
Review URL: https://codereview.chromium.org//601103004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40681 260f80e4-7a28-3924-810f-c04153c831b5
The way it was implemented did not always work for phis for live ranges extending past the loop, because the hint itself stayed uncoverted until after register allocation inside the loop was completed.
For the loop like this:
f() {
var x = 1.0, y = 2.0;
for (var i = 0; i < 100; i++) x += y;
return x;
}
That used to generate:
loop:
cmp ecx,0xc8
jnl ->exit
mov xmm3, xmm2
addsd xmm3, xmm1
mov xmm2, xmm3
add ecx,0x2
jmp ->loop
With this change we generate:
loop:
cmp ecx,0xc8
jnl ->exit
addsd xmm2,xmm1
add ecx,0x2
jmp ->loop
R=fschneider@google.com
BUG=
Review URL: https://codereview.chromium.org//556453006
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40024 260f80e4-7a28-3924-810f-c04153c831b5
Register allocator is unable to preserve writable registers automatically because they behave like temps: have no fixed represenation or usage inside the instruction template.
This means writable registers have to be manually added with the right representation to the live_register set when necessary.
Add verification that checks this and fix existing misuses.
R=fschneider@google.com
BUG=
Review URL: https://codereview.chromium.org//517343002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@39703 260f80e4-7a28-3924-810f-c04153c831b5
- Improve escape/alias analysis:
-- Storing an object into a field of another object does not mean that this object escapes (or has aliases) as long as that object does not have any loads from the same place;
-- Places like X.f and Y.f don't alias if X and Y are two different allocation instructions even if X and Y themselves potentially have aliases;
-- Improve precision of alias analysis for indexed properties;
- Support dematerialization and rematerialization of objects that are referenced by other dematerialized objects.
-- Use fix-point algorithm to collect candidates for allocation sinking;
-- Support aborting unsuccessful allocation sinking.
R=fschneider@google.com, johnmccutchan@google.com
Review URL: https://codereview.chromium.org//395943003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38404 260f80e4-7a28-3924-810f-c04153c831b5
This avoids treating spill slot associated with the definition live during GC as
it will only be filled in after definition's code is fully executed.
Additionally this makes output register dead for GC inside the definiton itself
which is something we used to guarantee manually by removing it from the
live_registers set before calling on the slow path.
BUG=
R=fschneider@google.com
Review URL: https://codereview.chromium.org//375693004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38059 260f80e4-7a28-3924-810f-c04153c831b5
Changes:
* Register allocator now allocates GPRs for kUnboxedMint.
* Register allocator supports for SameAsFirstInput for register pairs.
* Register allocator properly handles register pairs in environment uses and materialization uses.
* BoxInteger updated on IA32/ARM.
* UnboxInteger updated on IA32/ARM.
* BinaryMintOp updated on IA32/ARM.
* ShiftMintOp updated on IA32/ARM.
* UnaryMintOp updated on IA32/ARM.
* RelationalOp updated on IA32/ARM.
* EqualityCompare updated on IA32/ARM.
* LoadIndexed and StoreIndexed updated on IA32/ARM.
* New Deopt instructions added.
* Update live_registers when an instruction has a fixed register input and a call on the slow path.
* Improve printing of register pairs in flow graph.
* Do not assume live registers in slow paths contain tagged values.
* LiveRange pairs for kUnboxedMint definitions marked as kUntagged representation (reduces stack usage).
* Live register spilling on ARM uses same register order as stack map encoding.
* Spill slots containing tagged and untagged are segregated.
* Print stack maps when printing live ranges with safe points.
* Print allocated spill slot when printing live ranges.
Status:
* IA32 completed. All tests are passing.
* ARM completed. All tests passing.
R=fschneider@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//252333002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@36468 260f80e4-7a28-3924-810f-c04153c831b5
- Adds a PairLocation type (Location is still a single word but now has two tags one for constants and one for pairs).
- New representations: kPairOfTagged & kPairOfUnboxedDouble.
- Register allocator uses second SSA index for Definitions that use two registers.
- Fix LiveRange shape for kWritableRegister inputs.
- Updated MergedMathInstr that returns a kPairOfTagged or kPairOfUnboxedDouble (depending on the merged math kind).
- A new instruction (ExtractNthOutput) for extracting a single register from an instruction that has a output register pair.
Open issues that need to be addressed in a follow up CL:
- Adjust PhiInstr and handling of PhiInstr in the register allocator to work with output pairs (once unboxed mints are in GPRs).
R=fschneider@google.com, srdjan@google.com
Review URL: https://codereview.chromium.org//215363004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@34833 260f80e4-7a28-3924-810f-c04153c831b5
The code for reserving stack slots for OSR entry values is shared with the
code for reserving stack slots for try/catch. It does not handle them
optimally (reserving slots above the desired ones and copying them down,
instead of directly reserving the desired one). This CL simplifies allocation
of spill slots for try-catch as well.
This is an rebased version of Kevin's original CL
(https://codereview.chromium.org/102173003/).
I removed an invalid assertion and removed more code that became unnecessary
with this change.
R=srdjan@google.com
Review URL: https://codereview.chromium.org//125943002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@31601 260f80e4-7a28-3924-810f-c04153c831b5
This allows the optimizing compiler to generate unboxed loads/stores
to fields containing double values. The double value is stored
in a reusable double object.
Unboxed loads/stores are generated for optimized code. Unoptimized code
allocates a new double on loads. To avoid performance regressions
for fields that are only written few times (e.g. only in the constructor)
I put a heuristic in place that
compares the usage count of setters and getters. Unboxed operations
are only generated if the setter is invoked a significant amount of
times (threshold is 10% of getter invocations).
The CL is so big because it changes the way LocationSummmary
is allocated: We now have a bit to generate different summaries
for optimized and unoptimized code.
R=srdjan@google.com
Review URL: https://codereview.chromium.org//99573005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@31164 260f80e4-7a28-3924-810f-c04153c831b5
This bug was only exposed on ARM, but can be a problem
on other platforms as well.
When building the use intervals for a value that
is used more than once at one instruction, the use
interval was not adjusted correctly: Under certain
conditions the resulting interval can be too short.
It can occur when the first use is a writable register use,
and the second use is a normal register use.
This CL grows the use intervals to the correct size
in that case.
BUG=https://code.google.com/p/dart/issues/detail?id=11800
TEST=tests/language/regress_11800_test.dart
R=vegorov@google.com
Review URL: https://codereview.chromium.org//22412002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25810 260f80e4-7a28-3924-810f-c04153c831b5
Florian Schneider