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[vm,arm64] Fix disassembly of add/sub with extended register and rd = SP

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Aliases cmn and cmp should be used only for adds/subs (with S bit set).

TEST=vm/cc/AddExtReg

Change-Id: Id453282f8397a1a696771d901e66bf77697bf7dd
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/476864
Reviewed-by: Ryan Macnak <rmacnak@google.com>
Commit-Queue: Alexander Markov <alexmarkov@google.com>
This commit is contained in:
Alexander Markov
2026-02-02 09:41:16 -08:00
committed by Commit Queue
parent ba57159a6a
commit 46cbb8152f
2 changed files with 6 additions and 2 deletions
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runtime/vm/compiler/assembler/assembler_arm64_test.cc
+4
View File
@@ -322,6 +322,8 @@ ASSEMBLER_TEST_GENERATE(AddExtReg, assembler) {
__ movz(R1, Immediate(0xffff), 0);
__ movk(R1, Immediate(0xffff), 1); // R1 <- -1 (32-bit)
__ add(R0, R0, Operand(R1, SXTW, 0)); // R0 <- R0 + (sign extended R1)
__ mov(R2, ZR);
__ add(CSP, CSP, Operand(R2, UXTX, 0));
__ ret();
}
@@ -333,6 +335,8 @@ ASSEMBLER_TEST_RUN(AddExtReg, test) {
"movz r1, #0xffff\n"
"movk r1, #0xffff lsl 16\n"
"add r0, r0, r1 sxtw\n"
"mov r2, zr\n"
"add csp, csp, r2 uxtx 0\n"
"ret\n");
}
runtime/vm/compiler/assembler/disassembler_arm64.cc
+2 -2
View File
@@ -1114,7 +1114,7 @@ void ARM64Decoder::DecodeLoadStore(Instr* instr) {
void ARM64Decoder::DecodeAddSubShiftExt(Instr* instr) {
switch (instr->Bit(30)) {
case 0: {
if (instr->RdField() == R31) {
if ((instr->RdField() == R31) && (instr->SField() == 1)) {
Format(instr, "cmn'sf 'rn, 'shift_op");
} else {
Format(instr, "add'sf's 'rd, 'rn, 'shift_op");
@@ -1122,7 +1122,7 @@ void ARM64Decoder::DecodeAddSubShiftExt(Instr* instr) {
break;
}
case 1: {
if (instr->RdField() == R31) {
if ((instr->RdField() == R31) && (instr->SField() == 1)) {
Format(instr, "cmp'sf 'rn, 'shift_op");
} else {
if (instr->RnField() == R31) {