Gateway Rewrite

This folder hosts the native ESP-IDF C++ rewrite of the Lua DALI gateway.

Layout

• apps/: standard ESP-IDF applications for each firmware role.
  • apps/gateway/main/Kconfig.projbuild: project-visible gateway-role settings such as per-channel native/serial PHY selection, gateway ids, and pin mapping.
• components/: reusable components shared by all gateway applications.
  • gateway_core/: boot profile and top-level role bootstrap.
  • dali/: vendored ESP-IDF DALI HAL/backend reused from LuatOS.
  • dali_domain/: native DALI domain facade over dali_cpp.
  • gateway_ble/: NimBLE GATT bridge for BLE transport parity on FFF1/FFF2/FFF3.
  • gateway_controller/: Lua-compatible gateway command dispatcher, internal scene/group state, and notification fan-out.
  • gateway_network/: initial HTTP /info and /dali/cmd plus UDP port 2020 control-plane ingress for the native gateway.
  • gateway_runtime/: persistent runtime state, command queueing, and device info services.

Current status

The native rewrite now wires a shared gateway_core bootstrap component, a multi-channel dali_domain wrapper over dali_cpp, a local vendored dali hardware backend from the LuatOS ESP-IDF port, an initial gateway_runtime service that provides persistent settings, device info, Lua-compatible command framing helpers, and Lua-style query command deduplication, plus a gateway_controller service that starts the gateway command task, dispatches core Lua gateway opcodes, and owns internal scene/group state. The gateway app now also includes an initial gateway_ble NimBLE bridge that advertises a Lua-compatible GATT service and forwards FFF3 framed notifications plus incoming FFF1/FFF2/FFF3 writes into the native controller and DALI domain, and an initial gateway_network service that starts the native HTTP /info and POST /dali/cmd surfaces plus the UDP control-plane router on port 2020. The gateway app exposes per-channel PHY selection through main/Kconfig.projbuild; each channel can be disabled, bound to the native DALI GPIO HAL, or bound to a UART1/UART2 serial PHY.