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Converted C++ comments to C comments.

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This commit is contained in:
skarg
2008-01-08 21:30:50 +00:00
parent a8dffb5a12
commit e17cb0559e
10 changed files with 2289 additions and 2286 deletions
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bacnet-stack/comment.sh
+9 -6
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@@ -1,22 +1,25 @@
#!/bin/sh
#!/bin/bash
# This script converts any C++ comments to C comments
# using the ccmtcnvt tool from the liwc package
CONVERTER=/usr/bin/ccmtcnvt
# silent fail if the tool is not installed
[ -x /usr/bin/ccmtcnvt ] || exit 0
[ -x ${CONVERTER} ] || exit 0
directory=${1-`pwd`}
for filename in $( find ${directory} -name '*.c' )
do
echo Converting ${filename}
/usr/bin/ccmtcnvt ${filename} > /tmp/ccmtcnvt.karg
mv /tmp/ccmtcnvt.karg ${filename}
TEMPFILE="/tmp/ccmtcnvt.$RANDOM.txt"
${CONVERTER} ${filename} > ${TEMPFILE}
mv ${TEMPFILE} ${filename}
done
for filename in $( find ${directory} -name '*.h' )
do
echo Converting ${filename}
/usr/bin/ccmtcnvt ${filename} > /tmp/ccmtcnvt.karg
mv /tmp/ccmtcnvt.karg ${filename}
TEMPFILE="/tmp/ccmtcnvt.$RANDOM.txt"
${CONVERTER} ${filename} > ${TEMPFILE}
mv ${TEMPFILE} ${filename}
done
bacnet-stack/ports/at91sam7s/at91sam7s256.h
+1817 -1817
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File diff suppressed because it is too large Load Diff
bacnet-stack/ports/at91sam7s/board.h
+54 -54
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@@ -1,17 +1,17 @@
//----------------------------------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
//----------------------------------------------------------------------------------------------------
// The software is delivered "AS IS" without warranty or condition of any
// kind, either express, implied or statutory. This includes without
// limitation any warranty or condition with respect to merchantability or
// fitness for any particular purpose, or against the infringements of
// intellectual property rights of others.
//----------------------------------------------------------------------------------------------------
// File Name: Board.h
// Object: AT91SAM7S Evaluation Board Features Definition File.
//
// Creation: JPP 16/June/2004
//----------------------------------------------------------------------------------------------------
/*---------------------------------------------------------------------------------------------------- */
/* ATMEL Microcontroller Software Support - ROUSSET - */
/*---------------------------------------------------------------------------------------------------- */
/* The software is delivered "AS IS" without warranty or condition of any */
/* kind, either express, implied or statutory. This includes without */
/* limitation any warranty or condition with respect to merchantability or */
/* fitness for any particular purpose, or against the infringements of */
/* intellectual property rights of others. */
/*---------------------------------------------------------------------------------------------------- */
/* File Name: Board.h */
/* Object: AT91SAM7S Evaluation Board Features Definition File. */
/* */
/* Creation: JPP 16/June/2004 */
/*---------------------------------------------------------------------------------------------------- */
#ifndef Board_h
#define Board_h
@@ -19,10 +19,10 @@
#include "isr.h"
#define __inline inline
//-----------------------------------------------
// SAM7Board Memories Definition
//-----------------------------------------------
// The AT91SAM7S2564 embeds a 64-Kbyte SRAM bank, and 256 K-Byte Flash
/*----------------------------------------------- */
/* SAM7Board Memories Definition */
/*----------------------------------------------- */
/* The AT91SAM7S2564 embeds a 64-Kbyte SRAM bank, and 256 K-Byte Flash */
#define INT_SRAM 0x00200000
#define INT_SRAM_REMAP 0x00000000
@@ -33,48 +33,48 @@
#define FLASH_PAGE_NB 512
#define FLASH_PAGE_SIZE 128
//------------------------
// Leds Definition
//------------------------
#define LED1 (1<<0) // PA0
#define LED2 (1<<1) // PA1
#define LED3 (1<<2) // PA2
#define LED4 (1<<3) // PA3
/*------------------------ */
/* Leds Definition */
/*------------------------ */
#define LED1 (1<<0) /* PA0 */
#define LED2 (1<<1) /* PA1 */
#define LED3 (1<<2) /* PA2 */
#define LED4 (1<<3) /* PA3 */
#define NB_LEB 4
#define LED_MASK (LED1|LED2|LED3|LED4)
//----------------------------------
// Push Buttons Definition
//-----------------------------------
#define SW1_MASK (1<<19) // PA19
#define SW2_MASK (1<<20) // PA20
#define SW3_MASK (1<<15) // PA15
#define SW4_MASK (1<<14) // PA14
/*---------------------------------- */
/* Push Buttons Definition */
/*----------------------------------- */
#define SW1_MASK (1<<19) /* PA19 */
#define SW2_MASK (1<<20) /* PA20 */
#define SW3_MASK (1<<15) /* PA15 */
#define SW4_MASK (1<<14) /* PA14 */
#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
#define SW1 (1<<19) // PA19
#define SW2 (1<<20) // PA20
#define SW3 (1<<15) // PA15
#define SW4 (1<<14) // PA14
#define SW1 (1<<19) /* PA19 */
#define SW2 (1<<20) /* PA20 */
#define SW3 (1<<15) /* PA15 */
#define SW4 (1<<14) /* PA14 */
//-------------------------
// USART Definition
//-------------------------
// SUB-D 9 points J3 DBGU
#define DBGU_RXD AT91C_PA9_DRXD // JP11 must be close
#define DBGU_TXD AT91C_PA10_DTXD // JP12 must be close
#define AT91C_DBGU_BAUD 115200 // Baud rate
#define US_RXD_PIN AT91C_PA5_RXD0 // JP9 must be close
#define US_TXD_PIN AT91C_PA6_TXD0 // JP7 must be close
#define US_RTS_PIN AT91C_PA7_RTS0 // JP8 must be close
#define US_CTS_PIN AT91C_PA8_CTS0 // JP6 must be close
/*------------------------- */
/* USART Definition */
/*------------------------- */
/* SUB-D 9 points J3 DBGU */
#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */
#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */
#define AT91C_DBGU_BAUD 115200 /* Baud rate */
#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */
#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */
#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */
#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */
//--------------
// Master Clock
//--------------
#define EXT_OC 18432000 // Exetrnal ocilator MAINCK
#define MCK 47923200 // MCK (PLLRC div by 2)
#define MCKKHz (MCK/1000) //
/*-------------- */
/* Master Clock */
/*-------------- */
#define EXT_OC 18432000 /* Exetrnal ocilator MAINCK */
#define MCK 47923200 /* MCK (PLLRC div by 2) */
#define MCKKHz (MCK/1000) /* */
#endif // Board_h
#endif /* Board_h */
bacnet-stack/ports/at91sam7s/init.c
+62 -62
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@@ -1,25 +1,25 @@
// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// The software is delivered "AS IS" without warranty or condition of any
// kind, either express, implied or statutory. This includes without
// limitation any warranty or condition with respect to merchantability or
// fitness for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ----------------------------------------------------------------------------
// File Name : Cstartup_SAM7.c
// Object : Low level initializations written in C for IAR tools
// 1.0 08/Sep/04 JPP : Creation
// 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
// ----------------------------------------------------------------------------
/* ---------------------------------------------------------------------------- */
/* ATMEL Microcontroller Software Support - ROUSSET - */
/* ---------------------------------------------------------------------------- */
/* The software is delivered "AS IS" without warranty or condition of any */
/* kind, either express, implied or statutory. This includes without */
/* limitation any warranty or condition with respect to merchantability or */
/* fitness for any particular purpose, or against the infringements of */
/* intellectual property rights of others. */
/* ---------------------------------------------------------------------------- */
/* File Name : Cstartup_SAM7.c */
/* Object : Low level initializations written in C for IAR tools */
/* 1.0 08/Sep/04 JPP : Creation */
/* 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed */
/* ---------------------------------------------------------------------------- */
// Include the board file description
/* Include the board file description */
#include "AT91SAM7S256.h"
#include "Board.h"
// The following functions must be write in ARM mode this function called directly
// by exception vector
/* The following functions must be write in ARM mode this function called directly */
/* by exception vector */
extern void AT91F_Spurious_handler(
void);
extern void AT91F_Default_IRQ_handler(
@@ -27,74 +27,74 @@ extern void AT91F_Default_IRQ_handler(
extern void AT91F_Default_FIQ_handler(
void);
//*----------------------------------------------------------------------------
//* \fn AT91F_LowLevelInit
//* \brief This function performs very low level HW initialization
//* this function can be use a Stack, depending the compilation
//* optimization mode
//*----------------------------------------------------------------------------
/**---------------------------------------------------------------------------- */
/** \fn AT91F_LowLevelInit */
/** \brief This function performs very low level HW initialization */
/** this function can be use a Stack, depending the compilation */
/** optimization mode */
/**---------------------------------------------------------------------------- */
void LowLevelInit(
void)
{
int i;
AT91PS_PMC pPMC = AT91C_BASE_PMC;
//* Set Flash Wait sate
// Single Cycle Access at Up to 30 MHz, or 40
// if MCK = 48054841 I have 50 Cycle for 1 usecond ( flied MC_FMR->FMCN
// result: AT91C_MC_FMR = 0x00320100 (MC Flash Mode Register)
/** Set Flash Wait sate */
/* Single Cycle Access at Up to 30 MHz, or 40 */
/* if MCK = 48054841 I have 50 Cycle for 1 usecond ( flied MC_FMR->FMCN */
/* result: AT91C_MC_FMR = 0x00320100 (MC Flash Mode Register) */
AT91C_BASE_MC->MC_FMR =
(((AT91C_MC_FMCN) & (50 << 16)) | AT91C_MC_FWS_1FWS);
//* Watchdog Disable
// result: AT91C_WDTC_WDMR = 0x00008000 (Watchdog Mode Register)
/** Watchdog Disable */
/* result: AT91C_WDTC_WDMR = 0x00008000 (Watchdog Mode Register) */
AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
//* Set MCK at 48 054 841
// 1 Enabling the Main Oscillator:
// SCK = 1/32768 = 30.51 uSecond
// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
// result: AT91C_CKGR_MOR = 0x00000601 (Main Oscillator Register)
/** Set MCK at 48 054 841 */
/* 1 Enabling the Main Oscillator: */
/* SCK = 1/32768 = 30.51 uSecond */
/* Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms */
/* result: AT91C_CKGR_MOR = 0x00000601 (Main Oscillator Register) */
pPMC->PMC_MOR = ((AT91C_CKGR_OSCOUNT & (0x06 << 8)) | AT91C_CKGR_MOSCEN);
// Wait the startup time
/* Wait the startup time */
while (!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
// PMC Clock Generator PLL Register setup
//
// The following settings are used: DIV = 14
// MUL = 72
// PLLCOUNT = 10
//
// Main Clock (MAINCK from crystal oscillator) = 18432000 hz (see AT91SAM7-EK schematic)
// MAINCK / DIV = 18432000/14 = 1316571 hz
// PLLCK = 1316571 * (MUL + 1) = 1316571 * (72 + 1) = 1316571 * 73 = 96109683 hz
//
// PLLCOUNT = number of slow clock cycles before the LOCK bit is set
// in PMC_SR after CKGR_PLLR is written.
//
// PLLCOUNT = 10
//
// OUT = 0 (not used)
// result: AT91C_CKGR_PLLR = 0x00000000480A0E (PLL Register)
/* PMC Clock Generator PLL Register setup */
/* */
/* The following settings are used: DIV = 14 */
/* MUL = 72 */
/* PLLCOUNT = 10 */
/* */
/* Main Clock (MAINCK from crystal oscillator) = 18432000 hz (see AT91SAM7-EK schematic) */
/* MAINCK / DIV = 18432000/14 = 1316571 hz */
/* PLLCK = 1316571 * (MUL + 1) = 1316571 * (72 + 1) = 1316571 * 73 = 96109683 hz */
/* */
/* PLLCOUNT = number of slow clock cycles before the LOCK bit is set */
/* in PMC_SR after CKGR_PLLR is written. */
/* */
/* PLLCOUNT = 10 */
/* */
/* OUT = 0 (not used) */
/* result: AT91C_CKGR_PLLR = 0x00000000480A0E (PLL Register) */
pPMC->PMC_PLLR =
((AT91C_CKGR_DIV & 14) | (AT91C_CKGR_PLLCOUNT & (10 << 8)) |
(AT91C_CKGR_MUL & (72 << 16)));
// Wait the startup time (until PMC Status register LOCK bit is set)
/* Wait the startup time (until PMC Status register LOCK bit is set) */
while (!(pPMC->PMC_SR & AT91C_PMC_LOCK));
// PMC Master Clock (MCK) Register setup
//
// CSS = 3 (PLLCK clock selected)
//
// PRES = 1 (MCK = PLLCK / 2) = 96109683/2 = 48054841 hz
//
// Note: Master Clock MCK = 48054841 hz (this is the CPU clock speed)
// result: AT91C_PMC_MCKR = 0x00000007 (Master Clock Register)
/* PMC Master Clock (MCK) Register setup */
/* */
/* CSS = 3 (PLLCK clock selected) */
/* */
/* PRES = 1 (MCK = PLLCK / 2) = 96109683/2 = 48054841 hz */
/* */
/* Note: Master Clock MCK = 48054841 hz (this is the CPU clock speed) */
/* result: AT91C_PMC_MCKR = 0x00000007 (Master Clock Register) */
pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2;
// Set up the default interrupts handler vectors
/* Set up the default interrupts handler vectors */
AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler;
for (i = 1; i < 31; i++) {
AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler;
bacnet-stack/ports/at91sam7s/isr.c
+18 -18
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@@ -1,21 +1,21 @@
// **********************************************************************************************
//
// File Name : isr.c
// Title : interrupt enable/disable functions
//
//
// This module provides the interface routines for setting up and
// controlling the various interrupt modes present on the ARM processor.
// Copyright 2004, R O SoftWare
// No guarantees, warrantees, or promises, implied or otherwise.
// May be used for hobby or commercial purposes provided copyright
// notice remains intact.
//
// Note from Jim Lynch:
// This module was developed by Bill Knight, RO Software and used with his permission.
// Taken from the Yahoo LPC2000 User's Group - Files Section 'UT050418A.ZIP'
// Specifically, the module armVIC.c with the include file references removed
// **********************************************************************************************
/* ********************************************************************************************** */
/* */
/* File Name : isr.c */
/* Title : interrupt enable/disable functions */
/* */
/* */
/* This module provides the interface routines for setting up and */
/* controlling the various interrupt modes present on the ARM processor. */
/* Copyright 2004, R O SoftWare */
/* No guarantees, warrantees, or promises, implied or otherwise. */
/* May be used for hobby or commercial purposes provided copyright */
/* notice remains intact. */
/* */
/* Note from Jim Lynch: */
/* This module was developed by Bill Knight, RO Software and used with his permission. */
/* Taken from the Yahoo LPC2000 User's Group - Files Section 'UT050418A.ZIP' */
/* Specifically, the module armVIC.c with the include file references removed */
/* ********************************************************************************************** */
#define IRQ_MASK 0x00000080
#define FIQ_MASK 0x00000040
bacnet-stack/ports/at91sam7s/main.c
+29 -29
View File
@@ -45,9 +45,9 @@
#include "iam.h"
#include "txbuf.h"
// *******************************************************
// FIXME: use header files? External References
// *******************************************************
/* ******************************************************* */
/* FIXME: use header files? External References */
/* ******************************************************* */
extern void LowLevelInit(
void);
extern unsigned enableIRQ(
@@ -95,37 +95,37 @@ static inline void init(
volatile AT91PS_PMC pPMC = AT91C_BASE_PMC;
pPMC->PMC_PCER = pPMC->PMC_PCSR | (1 << AT91C_ID_PIOA);
// Set up the LEDs (PA0 - PA3)
/* Set up the LEDs (PA0 - PA3) */
volatile AT91PS_PIO pPIO = AT91C_BASE_PIOA;
// PIO Enable Register
// allow PIO to control pins P0 - P3 and pin 19
/* PIO Enable Register */
/* allow PIO to control pins P0 - P3 and pin 19 */
pPIO->PIO_PER = LED_MASK | SW1_MASK;
// PIO Output Enable Register
// sets pins P0 - P3 to outputs
/* PIO Output Enable Register */
/* sets pins P0 - P3 to outputs */
pPIO->PIO_OER = LED_MASK;
// PIO Set Output Data Register
// turns off the four LEDs
/* PIO Set Output Data Register */
/* turns off the four LEDs */
pPIO->PIO_SODR = LED_MASK;
// Select PA19 (pushbutton) to be FIQ function (Peripheral B)
/* Select PA19 (pushbutton) to be FIQ function (Peripheral B) */
pPIO->PIO_BSR = SW1_MASK;
// Set up the AIC registers for FIQ (pushbutton SW1)
/* Set up the AIC registers for FIQ (pushbutton SW1) */
volatile AT91PS_AIC pAIC = AT91C_BASE_AIC;
// Disable FIQ interrupt in
// AIC Interrupt Disable Command Register
/* Disable FIQ interrupt in */
/* AIC Interrupt Disable Command Register */
pAIC->AIC_IDCR = (1 << AT91C_ID_FIQ);
// Set the interrupt source type in
// AIC Source Mode Register[0]
/* Set the interrupt source type in */
/* AIC Source Mode Register[0] */
pAIC->AIC_SMR[AT91C_ID_FIQ] = (AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED);
// Clear the FIQ interrupt in
// AIC Interrupt Clear Command Register
/* Clear the FIQ interrupt in */
/* AIC Interrupt Clear Command Register */
pAIC->AIC_ICCR = (1 << AT91C_ID_FIQ);
// Remove disable FIQ interrupt in
// AIC Interrupt Disable Command Register
/* Remove disable FIQ interrupt in */
/* AIC Interrupt Disable Command Register */
pAIC->AIC_IDCR = (0 << AT91C_ID_FIQ);
// Enable the FIQ interrupt in
// AIC Interrupt Enable Command Register
/* Enable the FIQ interrupt in */
/* AIC Interrupt Enable Command Register */
pAIC->AIC_IECR = (1 << AT91C_ID_FIQ);
}
@@ -161,27 +161,27 @@ static uint8_t Receive_PDU[MAX_MPDU]; /* PDU data */
int main(
void)
{
unsigned long IdleCount = 0; // idle loop blink counter
unsigned long IdleCount = 0; /* idle loop blink counter */
bool LED1_Off_Enabled = true;
bool LED2_Off_Enabled = true;
bool LED3_Off_Enabled = true;
uint16_t pdu_len = 0;
BACNET_ADDRESS src; /* source address */
// Set up the LEDs (PA0 - PA3)
/* Set up the LEDs (PA0 - PA3) */
volatile AT91PS_PIO pPIO = AT91C_BASE_PIOA;
// Initialize the Atmel AT91SAM7S256
// (watchdog, PLL clock, default interrupts, etc.)
/* Initialize the Atmel AT91SAM7S256 */
/* (watchdog, PLL clock, default interrupts, etc.) */
LowLevelInit();
TimerInit();
init();
bacnet_init();
// enable interrupts
/* enable interrupts */
enableIRQ();
enableFIQ();
/* broadcast an I-Am on startup */
iam_send(&Handler_Transmit_Buffer[0]);
// endless blink loop
/* endless blink loop */
while (1) {
millisecond_timer();
if (!DCC_Timer) {
@@ -233,7 +233,7 @@ int main(
/* wait */
LED_Timer_4 = 1000;
}
// count # of times through the idle loop
/* count # of times through the idle loop */
IdleCount++;
/* BACnet handling */
pdu_len = datalink_receive(&src,
bacnet-stack/ports/at91sam7s/timer.c
+293 -293
View File
@@ -1,40 +1,40 @@
// *****************************************************************************
//
// Purpose: Set up the 16-bit Timer/Counter
//
// We will use Timer Channel 0 to develop a 1 msec interrupt.
//
// The AT91SAM7S-EK board has a 18,432,000 hz crystal oscillator.
//
// MAINCK = 18432000 hz
// PLLCK = (MAINCK / DIV) * (MUL + 1) = 18432000/14 * (72 + 1)
// PLLCLK = 1316571 * 73 = 96109683 hz
//
// MCK = PLLCLK / 2 = 96109683 / 2 = 48054841 hz
//
// TIMER_CLOCK5 = MCK / 1024 = 48054841 / 1024 = 46928 hz
//
// TIMER_CLOCK5 Period = 1 / 46928 = 21.309239686 microseconds
//
// A little algebra: .001 sec = count * 21.3092396896*10**-6
// count = .001 / 21.3092396896*10**-6
// count = 46.928
//
//
// Therefore: set Timer Channel 0 register RC to 46*milliseconds
// turn on capture mode WAVE = 0
// enable the clock CLKEN = 1
// select TIMER_CLOCK5 TCCLKS = 100
// clock is NOT inverted CLKI = 0
// enable RC compare CPCTRG = 1
// enable RC compare interrupt CPCS = 1
// disable all the other timer 0 interrupts
//
// Author: James P Lynch May 12, 2007
// Modified by Steve Karg
// Changed timer to 1ms.
// Encapsulated the intialization
// *****************************************************************************
/* ***************************************************************************** */
/* */
/* Purpose: Set up the 16-bit Timer/Counter */
/* */
/* We will use Timer Channel 0 to develop a 1 msec interrupt. */
/* */
/* The AT91SAM7S-EK board has a 18,432,000 hz crystal oscillator. */
/* */
/* MAINCK = 18432000 hz */
/* PLLCK = (MAINCK / DIV) * (MUL + 1) = 18432000/14 * (72 + 1) */
/* PLLCLK = 1316571 * 73 = 96109683 hz */
/* */
/* MCK = PLLCLK / 2 = 96109683 / 2 = 48054841 hz */
/* */
/* TIMER_CLOCK5 = MCK / 1024 = 48054841 / 1024 = 46928 hz */
/* */
/* TIMER_CLOCK5 Period = 1 / 46928 = 21.309239686 microseconds */
/* */
/* A little algebra: .001 sec = count * 21.3092396896*10**-6 */
/* count = .001 / 21.3092396896*10**-6 */
/* count = 46.928 */
/* */
/* */
/* Therefore: set Timer Channel 0 register RC to 46*milliseconds */
/* turn on capture mode WAVE = 0 */
/* enable the clock CLKEN = 1 */
/* select TIMER_CLOCK5 TCCLKS = 100 */
/* clock is NOT inverted CLKI = 0 */
/* enable RC compare CPCTRG = 1 */
/* enable RC compare interrupt CPCS = 1 */
/* disable all the other timer 0 interrupts */
/* */
/* Author: James P Lynch May 12, 2007 */
/* Modified by Steve Karg */
/* Changed timer to 1ms. */
/* Encapsulated the intialization */
/* ***************************************************************************** */
/**********************************************************
@@ -53,262 +53,262 @@ static volatile int SilenceTime;
static void Timer0_Setup(
int milliseconds)
{
// TC Block Control Register TC_BCR (read/write)
//
// |------------------------------------------------------------------|------|
// | SYNC |
// |------------------------------------------------------------------|------|
// 31 1 0
//
// SYNC = 0 (no effect) <===== take default
// SYNC = 1 (generate software trigger for all 3 timer channels simultaneously)
//
// create a pointer to TC Global Register structure
/* TC Block Control Register TC_BCR (read/write) */
/* */
/* |------------------------------------------------------------------|------| */
/* | SYNC | */
/* |------------------------------------------------------------------|------| */
/* 31 1 0 */
/* */
/* SYNC = 0 (no effect) <===== take default */
/* SYNC = 1 (generate software trigger for all 3 timer channels simultaneously) */
/* */
/* create a pointer to TC Global Register structure */
AT91PS_TCB pTCB = AT91C_BASE_TCB;
// SYNC trigger not used
/* SYNC trigger not used */
pTCB->TCB_BCR = 0;
// TC Block Mode Register TC_BMR (read/write)
//
// |-------------------------------------|-----------|-----------|-----------|
// | TC2XC2S TCXC1S TC0XC0S |
// |-------------------------------------|-----------|-----------|-----------|
// 31 5 4 3 2 1 0
//
// TC0XC0S Select = 00 TCLK0 (PA4)
// = 01 none <===== we select this one
// = 10 TIOA1 (PA15)
// = 11 TIOA2 (PA26)
//
// TCXC1S Select = 00 TCLK1 (PA28)
// = 01 none <===== we select this one
// = 10 TIOA0 (PA15)
// = 11 TIOA2 (PA26)
//
// TC2XC2S Select = 00 TCLK2 (PA29)
// = 01 none <===== we select this one
// = 10 TIOA0 (PA00)
// = 11 TIOA1 (PA26)
//
// external clocks not used
/* TC Block Mode Register TC_BMR (read/write) */
/* */
/* |-------------------------------------|-----------|-----------|-----------| */
/* | TC2XC2S TCXC1S TC0XC0S | */
/* |-------------------------------------|-----------|-----------|-----------| */
/* 31 5 4 3 2 1 0 */
/* */
/* TC0XC0S Select = 00 TCLK0 (PA4) */
/* = 01 none <===== we select this one */
/* = 10 TIOA1 (PA15) */
/* = 11 TIOA2 (PA26) */
/* */
/* TCXC1S Select = 00 TCLK1 (PA28) */
/* = 01 none <===== we select this one */
/* = 10 TIOA0 (PA15) */
/* = 11 TIOA2 (PA26) */
/* */
/* TC2XC2S Select = 00 TCLK2 (PA29) */
/* = 01 none <===== we select this one */
/* = 10 TIOA0 (PA00) */
/* = 11 TIOA1 (PA26) */
/* */
/* external clocks not used */
pTCB->TCB_BMR = 0x15;
// TC Channel Control Register TC_CCR (read/write)
//
// |----------------------------------|--------------|------------|-----------|
// | SWTRG CLKDIS CLKENS |
// |----------------------------------|--------------|------------|-----------|
// 31 2 1 0
//
// CLKEN = 0 no effect
// CLKEN = 1 enables the clock <===== we select this one
//
// CLKDIS = 0 no effect <===== take default
// CLKDIS = 1 disables the clock
//
// SWTRG = 0 no effect
// SWTRG = 1 software trigger aserted counter reset and clock starts <===== we select this one
//
// create a pointer to channel 0 Register structure
/* TC Channel Control Register TC_CCR (read/write) */
/* */
/* |----------------------------------|--------------|------------|-----------| */
/* | SWTRG CLKDIS CLKENS | */
/* |----------------------------------|--------------|------------|-----------| */
/* 31 2 1 0 */
/* */
/* CLKEN = 0 no effect */
/* CLKEN = 1 enables the clock <===== we select this one */
/* */
/* CLKDIS = 0 no effect <===== take default */
/* CLKDIS = 1 disables the clock */
/* */
/* SWTRG = 0 no effect */
/* SWTRG = 1 software trigger aserted counter reset and clock starts <===== we select this one */
/* */
/* create a pointer to channel 0 Register structure */
AT91PS_TC pTC = AT91C_BASE_TC0;
// enable the clock and start it
/* enable the clock and start it */
pTC->TC_CCR = 0x5;
// TC Channel Mode Register TC_CMR (read/write)
//
// |-----------------------------------|------------|---------------|
// | LDRB LDRA |
// |-----------------------------------|------------|---------------|
// 31 19 18 17 16
//
// |----------|---------|--------------|------------|---------------|
// |WAVE = 0 CPCTRG ABETRG ETRGEDG |
// |----------|---------|--------------|------------|---------------|
// 15 14 13 11 10 9 8
//
// |----------|---------|--------------|------------|---------------|
// | LDBDIS LDBSTOP BURST CLKI TCCLKS |
// |----------|---------|--------------|------------|---------------|
// 7 6 5 4 3 2 0
//
// CLOCK SELECTION
// TCCLKS = 000 TIMER_CLOCK1 (MCK/2 = 24027420 hz)
// 001 TIMER_CLOCK2 (MCK/8 = 6006855 hz)
// 010 TIMER_CLOCK3 (MCK/32 = 1501713 hz)
// 011 TIMER_CLOCK4 (MCK/128 = 375428 hz)
// 100 TIMER_CLOCK5 (MCK/1024 = 46928 hz) <===== we select this one
// 101 XC0
// 101 XC1
// 101 XC2
//
// CLOCK INVERT
// CLKI = 0 counter incremented on rising clock edge <===== we select this one
// CLKI = 1 counter incremented on falling clock edge
//
// BURST SIGNAL SELECTION
// BURST = 00 clock is not gated by any external system <===== take default
// 01 XC0 is anded with the clock
// 10 XC1 is anded with the clock
// 11 XC2 is anded with the clock
//
// COUNTER CLOCK STOPPED WITH RB LOADING
// LDBSTOP = 0 counter clock is not stopped when RB loading occurs <===== take default
// = 1 counter clock is stopped when RB loading occur
//
// COUNTER CLOCK DISABLE WITH RB LOADING
// LDBDIS = 0 counter clock is not disabled when RB loading occurs <===== take default
// = 1 counter clock is disabled when RB loading occurs
//
// EXTERNAL TRIGGER EDGE SELECTION
// ETRGEDG = 00 (none) <===== take default
// 01 (rising edge)
// 10 (falling edge)
// 11 (each edge)
//
// TIOA OR TIOB EXTERNAL TRIGGER SELECTION
// ABETRG = 0 (TIOA is used) <===== take default
// 1 (TIOB is used)
//
// RC COMPARE TRIGGER ENABLE
// CPCTRG = 0 (RC Compare has no effect on the counter and its clock)
// 1 (RC Compare resets the counter and starts the clock) <===== we select this one
//
// WAVE
// WAVE = 0 Capture Mode is enabled <===== we select this one
// 1 Waveform Mode is enabled
//
// RA LOADING SELECTION
// LDRA = 00 none) <===== take default
// 01 (rising edge of TIOA)
// 10 (falling edge of TIOA)
// 11 (each edge of TIOA)
//
// RB LOADING SELECTION
// LDRB = 00 (none) <===== take default
// 01 (rising edge of TIOA)
// 10 (falling edge of TIOA)
// 11 (each edge of TIOA)
//
// TCCLKS = 1 (TIMER_CLOCK5)
// CPCTRG = 1 (RC Compare resets the counter and restarts the clock)
// WAVE = 0 (Capture mode enabled)
/* TC Channel Mode Register TC_CMR (read/write) */
/* */
/* |-----------------------------------|------------|---------------| */
/* | LDRB LDRA | */
/* |-----------------------------------|------------|---------------| */
/* 31 19 18 17 16 */
/* */
/* |----------|---------|--------------|------------|---------------| */
/* |WAVE = 0 CPCTRG ABETRG ETRGEDG | */
/* |----------|---------|--------------|------------|---------------| */
/* 15 14 13 11 10 9 8 */
/* */
/* |----------|---------|--------------|------------|---------------| */
/* | LDBDIS LDBSTOP BURST CLKI TCCLKS | */
/* |----------|---------|--------------|------------|---------------| */
/* 7 6 5 4 3 2 0 */
/* */
/* CLOCK SELECTION */
/* TCCLKS = 000 TIMER_CLOCK1 (MCK/2 = 24027420 hz) */
/* 001 TIMER_CLOCK2 (MCK/8 = 6006855 hz) */
/* 010 TIMER_CLOCK3 (MCK/32 = 1501713 hz) */
/* 011 TIMER_CLOCK4 (MCK/128 = 375428 hz) */
/* 100 TIMER_CLOCK5 (MCK/1024 = 46928 hz) <===== we select this one */
/* 101 XC0 */
/* 101 XC1 */
/* 101 XC2 */
/* */
/* CLOCK INVERT */
/* CLKI = 0 counter incremented on rising clock edge <===== we select this one */
/* CLKI = 1 counter incremented on falling clock edge */
/* */
/* BURST SIGNAL SELECTION */
/* BURST = 00 clock is not gated by any external system <===== take default */
/* 01 XC0 is anded with the clock */
/* 10 XC1 is anded with the clock */
/* 11 XC2 is anded with the clock */
/* */
/* COUNTER CLOCK STOPPED WITH RB LOADING */
/* LDBSTOP = 0 counter clock is not stopped when RB loading occurs <===== take default */
/* = 1 counter clock is stopped when RB loading occur */
/* */
/* COUNTER CLOCK DISABLE WITH RB LOADING */
/* LDBDIS = 0 counter clock is not disabled when RB loading occurs <===== take default */
/* = 1 counter clock is disabled when RB loading occurs */
/* */
/* EXTERNAL TRIGGER EDGE SELECTION */
/* ETRGEDG = 00 (none) <===== take default */
/* 01 (rising edge) */
/* 10 (falling edge) */
/* 11 (each edge) */
/* */
/* TIOA OR TIOB EXTERNAL TRIGGER SELECTION */
/* ABETRG = 0 (TIOA is used) <===== take default */
/* 1 (TIOB is used) */
/* */
/* RC COMPARE TRIGGER ENABLE */
/* CPCTRG = 0 (RC Compare has no effect on the counter and its clock) */
/* 1 (RC Compare resets the counter and starts the clock) <===== we select this one */
/* */
/* WAVE */
/* WAVE = 0 Capture Mode is enabled <===== we select this one */
/* 1 Waveform Mode is enabled */
/* */
/* RA LOADING SELECTION */
/* LDRA = 00 none) <===== take default */
/* 01 (rising edge of TIOA) */
/* 10 (falling edge of TIOA) */
/* 11 (each edge of TIOA) */
/* */
/* RB LOADING SELECTION */
/* LDRB = 00 (none) <===== take default */
/* 01 (rising edge of TIOA) */
/* 10 (falling edge of TIOA) */
/* 11 (each edge of TIOA) */
/* */
/* TCCLKS = 1 (TIMER_CLOCK5) */
/* CPCTRG = 1 (RC Compare resets the counter and restarts the clock) */
/* WAVE = 0 (Capture mode enabled) */
pTC->TC_CMR = 0x4004;
// TC Register C TC_RC (read/write) Compare Register 16-bits
//
// |----------------------------------|----------------------------------------|
// | not used RC |
// |----------------------------------|----------------------------------------|
// 31 16 15 0
//
// Timer Calculation: What count gives 1 msec time-out?
//
// TIMER_CLOCK5 = MCK / 1024 = 48054841 / 1024 = 46928 hz
//
// TIMER_CLOCK5 Period = 1 / 46928 = 21.309239686 microseconds
//
// A little algebra: .001 sec = count * 21.3092396896*10**-6
// count = .001 / 21.3092396896*10**-6
// count = 46.928
//
// STK: Even Simpler, let the compiler do the work:
//
// TIMER_CLOCK5 = (MCK / 1024) / 1000
// = 48054841 / 1024 / 1000 = 46.928
/* TC Register C TC_RC (read/write) Compare Register 16-bits */
/* */
/* |----------------------------------|----------------------------------------| */
/* | not used RC | */
/* |----------------------------------|----------------------------------------| */
/* 31 16 15 0 */
/* */
/* Timer Calculation: What count gives 1 msec time-out? */
/* */
/* TIMER_CLOCK5 = MCK / 1024 = 48054841 / 1024 = 46928 hz */
/* */
/* TIMER_CLOCK5 Period = 1 / 46928 = 21.309239686 microseconds */
/* */
/* A little algebra: .001 sec = count * 21.3092396896*10**-6 */
/* count = .001 / 21.3092396896*10**-6 */
/* count = 46.928 */
/* */
/* STK: Even Simpler, let the compiler do the work: */
/* */
/* TIMER_CLOCK5 = (MCK / 1024) / 1000 */
/* = 48054841 / 1024 / 1000 = 46.928 */
pTC->TC_RC = ((MCK / 1024 / 1000) + 1) * milliseconds;
// TC Interrupt Enable Register TC_IER (write-only)
//
//
// |------------|-------|-------|-------|-------|--------|--------|--------|--------|
// | ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS |
// |------------|-------|-------|-------|-------|--------|--------|--------|--------|
// 31 8 7 6 5 4 3 2 1 0
//
// COVFS = 0 no effect <===== take default
// 1 enable counter overflow interrupt
//
// LOVRS = 0 no effect <===== take default
// 1 enable load overrun interrupt
//
// CPAS = 0 no effect <===== take default
// 1 enable RA compare interrupt
//
// CPBS = 0 no effect <===== take default
// 1 enable RB compare interrupt
//
// CPCS = 0 no effect
// 1 enable RC compare interrupt <===== we select this one
//
// LDRAS = 0 no effect <===== take default
// 1 enable RA load interrupt
//
// LDRBS = 0 no effect <===== take default
// 1 enable RB load interrupt
//
// ETRGS = 0 no effect <===== take default
// 1 enable External Trigger interrupt
//
// enable RC compare interrupt
/* TC Interrupt Enable Register TC_IER (write-only) */
/* */
/* */
/* |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
/* | ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS | */
/* |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
/* 31 8 7 6 5 4 3 2 1 0 */
/* */
/* COVFS = 0 no effect <===== take default */
/* 1 enable counter overflow interrupt */
/* */
/* LOVRS = 0 no effect <===== take default */
/* 1 enable load overrun interrupt */
/* */
/* CPAS = 0 no effect <===== take default */
/* 1 enable RA compare interrupt */
/* */
/* CPBS = 0 no effect <===== take default */
/* 1 enable RB compare interrupt */
/* */
/* CPCS = 0 no effect */
/* 1 enable RC compare interrupt <===== we select this one */
/* */
/* LDRAS = 0 no effect <===== take default */
/* 1 enable RA load interrupt */
/* */
/* LDRBS = 0 no effect <===== take default */
/* 1 enable RB load interrupt */
/* */
/* ETRGS = 0 no effect <===== take default */
/* 1 enable External Trigger interrupt */
/* */
/* enable RC compare interrupt */
pTC->TC_IER = 0x10;
// TC Interrupt Disable Register TC_IDR (write-only)
//
//
// |------------|-------|-------|-------|-------|--------|--------|--------|--------|
// | ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS |
// |------------|-------|-------|-------|-------|--------|--------|--------|--------|
// 31 8 7 6 5 4 3 2 1 0
//
// COVFS = 0 no effect
// 1 disable counter overflow interrupt <===== we select this one
//
// LOVRS = 0 no effect
// 1 disable load overrun interrupt <===== we select this one
//
// CPAS = 0 no effect
// 1 disable RA compare interrupt <===== we select this one
//
// CPBS = 0 no effect
// 1 disable RB compare interrupt <===== we select this one
//
// CPCS = 0 no effect <===== take default
// 1 disable RC compare interrupt
//
// LDRAS = 0 no effect
// 1 disable RA load interrupt <===== we select this one
//
// LDRBS = 0 no effect
// 1 disable RB load interrupt <===== we select this one
//
// ETRGS = 0 no effect
// 1 disable External Trigger interrupt <===== we select this one
//
// disable all except RC compare interrupt
/* TC Interrupt Disable Register TC_IDR (write-only) */
/* */
/* */
/* |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
/* | ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS | */
/* |------------|-------|-------|-------|-------|--------|--------|--------|--------| */
/* 31 8 7 6 5 4 3 2 1 0 */
/* */
/* COVFS = 0 no effect */
/* 1 disable counter overflow interrupt <===== we select this one */
/* */
/* LOVRS = 0 no effect */
/* 1 disable load overrun interrupt <===== we select this one */
/* */
/* CPAS = 0 no effect */
/* 1 disable RA compare interrupt <===== we select this one */
/* */
/* CPBS = 0 no effect */
/* 1 disable RB compare interrupt <===== we select this one */
/* */
/* CPCS = 0 no effect <===== take default */
/* 1 disable RC compare interrupt */
/* */
/* LDRAS = 0 no effect */
/* 1 disable RA load interrupt <===== we select this one */
/* */
/* LDRBS = 0 no effect */
/* 1 disable RB load interrupt <===== we select this one */
/* */
/* ETRGS = 0 no effect */
/* 1 disable External Trigger interrupt <===== we select this one */
/* */
/* disable all except RC compare interrupt */
pTC->TC_IDR = 0xEF;
}
// *****************************************************************************
//
// Timer 0 Interrupt Service Routine
//
// Entered when Timer0 RC compare interrupt asserts
//
// Author: James P Lynch May 12, 2007
// Modified by Steve Karg
// simplified and changed to a millisecond count-up timer
// *****************************************************************************
/* ***************************************************************************** */
/* */
/* Timer 0 Interrupt Service Routine */
/* */
/* Entered when Timer0 RC compare interrupt asserts */
/* */
/* Author: James P Lynch May 12, 2007 */
/* Modified by Steve Karg */
/* simplified and changed to a millisecond count-up timer */
/* ***************************************************************************** */
static void Timer0IrqHandler(
void)
{
volatile AT91PS_TC pTC = AT91C_BASE_TC0; // pointer to timer channel 0 register structure
unsigned int dummy; // temporary
volatile AT91PS_TC pTC = AT91C_BASE_TC0; /* pointer to timer channel 0 register structure */
unsigned int dummy; /* temporary */
// read TC0 Status Register to clear interrupt
/* read TC0 Status Register to clear interrupt */
dummy = pTC->TC_SR;
// increment the tick count
/* increment the tick count */
Timer_Milliseconds++;
if (SilenceTime < 60000)
SilenceTime++;
@@ -326,42 +326,42 @@ void Timer_Silence_Reset(
SilenceTime = 0;
}
// *****************************************************************************
//
// Timer 0 Initialization
//
// From James P Lynch main.c example code
// Modified by Steve Karg
// Moved timer startup code from main
// modified the peripheral clock init
// *****************************************************************************
/* ***************************************************************************** */
/* */
/* Timer 0 Initialization */
/* */
/* From James P Lynch main.c example code */
/* Modified by Steve Karg */
/* Moved timer startup code from main */
/* modified the peripheral clock init */
/* ***************************************************************************** */
void TimerInit(
void)
{
// enable the Timer0 peripheral clock
/* enable the Timer0 peripheral clock */
volatile AT91PS_PMC pPMC = AT91C_BASE_PMC;
pPMC->PMC_PCER = pPMC->PMC_PCSR | (1 << AT91C_ID_TC0);
// Set up the AIC registers for Timer 0
/* Set up the AIC registers for Timer 0 */
volatile AT91PS_AIC pAIC = AT91C_BASE_AIC;
// Disable timer 0 interrupt
// in AIC Interrupt Disable Command Register
/* Disable timer 0 interrupt */
/* in AIC Interrupt Disable Command Register */
pAIC->AIC_IDCR = (1 << AT91C_ID_TC0);
// Set the TC0 IRQ handler address in
// AIC Source Vector Register[12]
/* Set the TC0 IRQ handler address in */
/* AIC Source Vector Register[12] */
pAIC->AIC_SVR[AT91C_ID_TC0] = (unsigned int) Timer0IrqHandler;
// Set the interrupt source type and priority
// in AIC Source Mode Register[12]
/* Set the interrupt source type and priority */
/* in AIC Source Mode Register[12] */
pAIC->AIC_SMR[AT91C_ID_TC0] =
(AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 0x4);
// Clear the TC0 interrupt
// in AIC Interrupt Clear Command Register
/* Clear the TC0 interrupt */
/* in AIC Interrupt Clear Command Register */
pAIC->AIC_ICCR = (1 << AT91C_ID_TC0);
// Remove disable timer 0 interrupt
// in AIC Interrupt Disable Command Reg
/* Remove disable timer 0 interrupt */
/* in AIC Interrupt Disable Command Reg */
pAIC->AIC_IDCR = (0 << AT91C_ID_TC0);
// Enable the TC0 interrupt
// in AIC Interrupt Enable Command Register
/* Enable the TC0 interrupt */
/* in AIC Interrupt Enable Command Register */
pAIC->AIC_IECR = (1 << AT91C_ID_TC0);
// Setup timer0 to generate a 1 msec periodic interrupt
/* Setup timer0 to generate a 1 msec periodic interrupt */
Timer0_Setup(1);
}
bacnet-stack/ports/atmega168/rs485.c
+1 -1
View File
@@ -31,7 +31,7 @@
#include <stdbool.h>
#include <stdlib.h>
#include <stdio.h>
//#include "mstp.h"
/*#include "mstp.h" */
/* This file has been customized for use with ATMEGA168 */
#include "hardware.h"
bacnet-stack/ports/dos/timer.c
+4 -4
View File
@@ -33,8 +33,8 @@ static volatile int SilenceTime;
/* counts ticks */
volatile unsigned long Timer_Milliseconds;
#define RTC_CMD_ADDR 0x70 // RTC internal register offset goes here
#define RTC_DAT_ADDR 0x71 // RTC internal register R/W access here
#define RTC_CMD_ADDR 0x70 /* RTC internal register offset goes here */
#define RTC_DAT_ADDR 0x71 /* RTC internal register R/W access here */
static uint8_t RTC_RS_Convert(
uint16_t hertz)
@@ -139,8 +139,8 @@ static void interrupt Timer_Interrupt_Handler(
}
/* clear interrupt */
outportb(RTC_CMD_ADDR, 0x0C); // select RTC register C
temp_reg = inportb(RTC_DAT_ADDR); // read RTC register C
outportb(RTC_CMD_ADDR, 0x0C); /* select RTC register C */
temp_reg = inportb(RTC_DAT_ADDR); /* read RTC register C */
/* signal end of interrupt to slave PIC */
outportb(0xA0, 0x20);
/* signal end of interrupt to master PIC */
bacnet-stack/ports/win32/rx_fsm.c
+2 -2
View File
@@ -82,7 +82,7 @@ void *milliseconds_task(
dlmstp_millisecond_timer();
}
//return NULL;
/*return NULL; */
}
/* functions used by the MS/TP state machine to put or get data */
@@ -203,5 +203,5 @@ int main(
}
}
//return 0;
/*return 0; */
}