Enhanced the ADC to be able to read all channels, and fixed bug in configuration of ADC.
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@@ -47,40 +47,102 @@
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#error "ADC: F_CPU too large for accuracy."
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#endif
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/* we could have array of ADC results */
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static volatile uint8_t Sample_Result;
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/* Array of ADC results */
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#define ADC_CHANNELS_MAX 8
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static volatile uint16_t Sample_Result[ADC_CHANNELS_MAX];
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static volatile uint8_t Enabled_Channels;
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/* forward prototype */
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ISR(ADC_vect);
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ISR(ADC_vect)
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{
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/* since we configured as ADLAR=1, get value from ADCH */
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Sample_Result = ADCH;
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uint8_t index;
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uint16_t value = 0;
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/* determine which conversion finished */
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index = BITMASK_CHECK(ADMUX,((1<<MUX2)|(1<<MUX1)|(1<<MUX0)));
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/* read the results */
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value = ADCL;
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value |= (ADCH << 8);
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Sample_Result[index] = value;
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/* clear the mux */
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BITMASK_CLEAR(ADMUX, ((1<<MUX2)|(1<<MUX1)|(1<<MUX0)));
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/* find the next channel */
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while (Enabled_Channels) {
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index = (index+1)%ADC_CHANNELS_MAX;
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if (BIT_CHECK(Enabled_Channels, index)) {
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break;
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}
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}
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/* configure the next channel */
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BITMASK_SET(ADMUX, ((index)<<MUX0));
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/* Start the next conversion */
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BIT_SET(ADCSRA, ADSC);
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}
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uint8_t adc_result(
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uint8_t channel)
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{ /* 0..7 = ADC0..ADC7, respectively */
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return Sample_Result;
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void adc_enable(
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uint8_t index) /* 0..7 = ADC0..ADC7, respectively */
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{
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if (Enabled_Channels) {
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/* ADC interupt is already started */
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BIT_SET(Enabled_Channels, index);
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} else {
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if (index < ADC_CHANNELS_MAX) {
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/* not running yet */
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BIT_SET(Enabled_Channels, index);
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/* clear the mux */
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BITMASK_CLEAR(ADMUX, ((1<<MUX2)|(1<<MUX1)|(1<<MUX0)));
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/* configure the channel */
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BITMASK_SET(ADMUX, ((index)<<MUX0));
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/* Start the next conversion */
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BIT_SET(ADCSRA, ADSC);
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}
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}
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}
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uint8_t adc_result_8bit(
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uint8_t index) /* 0..7 = ADC0..ADC7, respectively */
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{
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uint8_t result = 0;
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if (index < ADC_CHANNELS_MAX) {
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adc_enable(index);
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result = (uint8_t)(Sample_Result[index]>>2);
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}
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return result;
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}
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uint16_t adc_result_10bit(
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uint8_t index) /* 0..7 = ADC0..ADC7, respectively */
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{
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uint16_t result = 0;
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if (index < ADC_CHANNELS_MAX) {
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adc_enable(index);
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result = Sample_Result[index];
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}
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return result;
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}
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void adc_init(
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void)
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{
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/* set prescaler */
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ADCSRA |= ADPS_8BIT;
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/* Initial channel selection */
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/* ADLAR = Left Adjust Result
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REFSx = hardware setup: cap on AREF
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*/
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ADMUX = 7 /* channel */ | (1 << ADLAR) | (0 << REFS1) | (1 << REFS0);
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*/
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ADMUX = (0 << ADLAR) | (0 << REFS1) | (1 << REFS0);
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/* ADEN = Enable
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ADSC = Start conversion
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ADIF = Interrupt Flag
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ADIE = Interrupt Enable
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ADATE = Auto Trigger Enable
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*/
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ADCSRA |= (1 << ADEN) | (1 << ADIE) | (1 << ADIF) | (1 << ADATE);
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ADCSRA = (1 << ADEN) | (1 << ADIE) |
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(0 << ADIF) | (0 << ADATE) | ADPS_10BIT;
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/* trigger selection bits
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0 0 0 Free Running mode
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0 0 1 Analog Comparator
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@@ -91,9 +153,7 @@ void adc_init(
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1 1 0 Timer/Counter1 Overflow
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1 1 1 Timer/Counter1 Capture Event
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*/
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ADCSRB |= (0 << ADTS2) | (0 << ADTS1) | (0 << ADTS0);
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/* start the conversions */
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ADCSRA |= (1 << ADSC);
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ADCSRB = (0 << ADTS2) | (0 << ADTS1) | (0 << ADTS0);
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/* Clear the Power Reduction bit */
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BIT_CLEAR(PRR, PRADC);
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}
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@@ -30,8 +30,12 @@
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extern "C" {
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#endif /* __cplusplus */
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uint8_t adc_result(
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uint8_t channel);
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void adc_enable(
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uint8_t index); /* 0..7 = ADC0..ADC7, respectively */
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uint8_t adc_result_8bit(
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uint8_t index); /* 0..7 = ADC0..ADC7, respectively */
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uint16_t adc_result_10bit(
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uint8_t index); /* 0..7 = ADC0..ADC7, respectively */
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void adc_init(
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void);
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