Tess Strickland
8f5f6971a9
The differences between the different implementations are very minor, so abstract out the few that remain into Assembler: * Change Load<X>FromPoolOffset to Load<X>FromPoolIndex and do pool offset calculations internally, since all caller sites have the pool index. (Especially important because the pool register is tagged on X64 and ARM and untagged on ARM64, so this abstracts that away.) * Add default for pool register argument on ARM, since ARM64 already had one and X64 doesn't take a pool register argument. Other changes: * Use specific TestTypeABI registers within the helper method that adds caller-side checks instead of passing registers as arguments and document which registers are used for input or output (and when, if they are used conditionally). Cq-Include-Trybots: luci.dart.try:vm-kernel-linux-debug-x64-try,vm-kernel-nnbd-linux-debug-x64-try,vm-kernel-linux-debug-ia32-try,vm-kernel-nnbd-linux-debug-ia32-try,vm-kernel-precomp-linux-debug-simarm_x64-try,vm-kernel-precomp-linux-debug-x64-try,vm-kernel-precomp-nnbd-linux-debug-simarm_x64-try,vm-kernel-precomp-nnbd-linux-debug-x64-try,vm-kernel-linux-release-simarm-try,vm-kernel-linux-release-simarm64-try,vm-kernel-nnbd-linux-release-simarm-try,vm-kernel-nnbd-linux-release-simarm64-try,vm-kernel-precomp-linux-release-simarm-try,vm-kernel-precomp-linux-release-simarm64-try,vm-kernel-precomp-nnbd-linux-release-simarm64-try Change-Id: Ifc7a0eaa6aacf7f629aa9647b028500648af653d Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/167803 Commit-Queue: Tess Strickland <sstrickl@google.com> Reviewed-by: Martin Kustermann <kustermann@google.com>
587 lines
19 KiB
C++
587 lines
19 KiB
C++
// Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64.
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#if defined(TARGET_ARCH_ARM64)
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#include "vm/instructions.h"
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#include "vm/instructions_arm64.h"
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#include "vm/constants.h"
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#include "vm/cpu.h"
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#include "vm/object.h"
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#include "vm/reverse_pc_lookup_cache.h"
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namespace dart {
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CallPattern::CallPattern(uword pc, const Code& code)
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: object_pool_(ObjectPool::Handle(code.GetObjectPool())),
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target_code_pool_index_(-1) {
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ASSERT(code.ContainsInstructionAt(pc));
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// Last instruction: blr ip0.
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ASSERT(*(reinterpret_cast<uint32_t*>(pc) - 1) == 0xd63f0200);
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Register reg;
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InstructionPattern::DecodeLoadWordFromPool(pc - 2 * Instr::kInstrSize, ®,
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&target_code_pool_index_);
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ASSERT(reg == CODE_REG);
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}
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ICCallPattern::ICCallPattern(uword pc, const Code& code)
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: object_pool_(ObjectPool::Handle(code.GetObjectPool())),
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target_pool_index_(-1),
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data_pool_index_(-1) {
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ASSERT(code.ContainsInstructionAt(pc));
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// Last instruction: blr lr.
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ASSERT(*(reinterpret_cast<uint32_t*>(pc) - 1) == 0xd63f03c0);
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Register data_reg, code_reg;
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intptr_t pool_index;
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InstructionPattern::DecodeLoadDoubleWordFromPool(
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pc - 2 * Instr::kInstrSize, &data_reg, &code_reg, &pool_index);
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ASSERT(data_reg == R5);
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ASSERT(code_reg == CODE_REG);
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data_pool_index_ = pool_index;
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target_pool_index_ = pool_index + 1;
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}
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NativeCallPattern::NativeCallPattern(uword pc, const Code& code)
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: object_pool_(ObjectPool::Handle(code.GetObjectPool())),
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end_(pc),
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native_function_pool_index_(-1),
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target_code_pool_index_(-1) {
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ASSERT(code.ContainsInstructionAt(pc));
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// Last instruction: blr ip0.
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ASSERT(*(reinterpret_cast<uint32_t*>(end_) - 1) == 0xd63f0200);
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Register reg;
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uword native_function_load_end = InstructionPattern::DecodeLoadWordFromPool(
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end_ - 2 * Instr::kInstrSize, ®, &target_code_pool_index_);
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ASSERT(reg == CODE_REG);
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InstructionPattern::DecodeLoadWordFromPool(native_function_load_end, ®,
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&native_function_pool_index_);
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ASSERT(reg == R5);
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}
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CodePtr NativeCallPattern::target() const {
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return static_cast<CodePtr>(object_pool_.ObjectAt(target_code_pool_index_));
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}
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void NativeCallPattern::set_target(const Code& target) const {
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object_pool_.SetObjectAt(target_code_pool_index_, target);
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// No need to flush the instruction cache, since the code is not modified.
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}
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NativeFunction NativeCallPattern::native_function() const {
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return reinterpret_cast<NativeFunction>(
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object_pool_.RawValueAt(native_function_pool_index_));
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}
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void NativeCallPattern::set_native_function(NativeFunction func) const {
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object_pool_.SetRawValueAt(native_function_pool_index_,
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reinterpret_cast<uword>(func));
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the loaded object in the output parameters 'reg' and 'obj'
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// respectively.
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uword InstructionPattern::DecodeLoadObject(uword end,
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const ObjectPool& object_pool,
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Register* reg,
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Object* obj) {
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// 1. LoadWordFromPool
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// or
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// 2. LoadDecodableImmediate
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uword start = 0;
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Instr* instr = Instr::At(end - Instr::kInstrSize);
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if (instr->IsLoadStoreRegOp()) {
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// Case 1.
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intptr_t index = 0;
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start = DecodeLoadWordFromPool(end, reg, &index);
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*obj = object_pool.ObjectAt(index);
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} else {
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// Case 2.
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intptr_t value = 0;
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start = DecodeLoadWordImmediate(end, reg, &value);
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*obj = static_cast<ObjectPtr>(value);
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}
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return start;
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the loaded immediate value in the output parameters 'reg' and 'value'
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// respectively.
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uword InstructionPattern::DecodeLoadWordImmediate(uword end,
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Register* reg,
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intptr_t* value) {
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// 1. LoadWordFromPool
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// or
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// 2. LoadWordFromPool
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// orri
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// or
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// 3. LoadPatchableImmediate
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uword start = end - Instr::kInstrSize;
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Instr* instr = Instr::At(start);
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bool odd = false;
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// Case 2.
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if (instr->IsLogicalImmOp()) {
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ASSERT(instr->Bit(29) == 1);
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odd = true;
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// end points at orri so that we can pass it to DecodeLoadWordFromPool.
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end = start;
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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// Case 2 falls through to case 1.
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}
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// Case 1.
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if (instr->IsLoadStoreRegOp()) {
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start = DecodeLoadWordFromPool(end, reg, value);
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if (odd) {
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*value |= 1;
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}
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return start;
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}
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// Case 3.
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// movk dst, imm3, 3; movk dst, imm2, 2; movk dst, imm1, 1; movz dst, imm0, 0
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->Bits(29, 2) == 3);
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ASSERT(instr->HWField() == 3); // movk dst, imm3, 3
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*reg = instr->RdField();
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*value = static_cast<int64_t>(instr->Imm16Field()) << 48;
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->Bits(29, 2) == 3);
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ASSERT(instr->HWField() == 2); // movk dst, imm2, 2
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ASSERT(instr->RdField() == *reg);
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*value |= static_cast<int64_t>(instr->Imm16Field()) << 32;
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->Bits(29, 2) == 3);
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ASSERT(instr->HWField() == 1); // movk dst, imm1, 1
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ASSERT(instr->RdField() == *reg);
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*value |= static_cast<int64_t>(instr->Imm16Field()) << 16;
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->Bits(29, 2) == 2);
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ASSERT(instr->HWField() == 0); // movz dst, imm0, 0
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ASSERT(instr->RdField() == *reg);
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*value |= static_cast<int64_t>(instr->Imm16Field());
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return start;
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}
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// See comment in instructions_arm64.h
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uword InstructionPattern::DecodeLoadWordFromPool(uword end,
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Register* reg,
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intptr_t* index) {
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// 1. ldr dst, [pp, offset]
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// or
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// 2. add dst, pp, #offset_hi12
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// ldr dst [dst, #offset_lo12]
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// or
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// 3. movz dst, low_offset, 0
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// movk dst, hi_offset, 1 (optional)
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// ldr dst, [pp, dst]
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uword start = end - Instr::kInstrSize;
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Instr* instr = Instr::At(start);
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intptr_t offset = 0;
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// Last instruction is always an ldr into a 64-bit X register.
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ASSERT(instr->IsLoadStoreRegOp() && (instr->Bit(22) == 1) &&
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(instr->Bits(30, 2) == 3));
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// Grab the destination register from the ldr instruction.
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*reg = instr->RtField();
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if (instr->Bit(24) == 1) {
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// base + scaled unsigned 12-bit immediate offset.
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// Case 1.
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offset |= (instr->Imm12Field() << 3);
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if (instr->RnField() == *reg) {
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsAddSubImmOp());
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ASSERT(instr->RnField() == PP);
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ASSERT(instr->RdField() == *reg);
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offset |= (instr->Imm12Field() << 12);
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}
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} else {
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ASSERT(instr->Bits(10, 2) == 2);
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// We have to look at the preceding one or two instructions to find the
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// offset.
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->RdField() == *reg);
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if (instr->Bits(29, 2) == 2) { // movz dst, low_offset, 0
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ASSERT(instr->HWField() == 0);
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offset = instr->Imm16Field();
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// no high offset.
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} else {
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ASSERT(instr->Bits(29, 2) == 3); // movk dst, high_offset, 1
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ASSERT(instr->HWField() == 1);
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offset = instr->Imm16Field() << 16;
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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ASSERT(instr->IsMoveWideOp());
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ASSERT(instr->RdField() == *reg);
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ASSERT(instr->Bits(29, 2) == 2); // movz dst, low_offset, 0
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ASSERT(instr->HWField() == 0);
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offset |= instr->Imm16Field();
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}
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}
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// PP is untagged on ARM64.
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ASSERT(Utils::IsAligned(offset, 8));
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*index = ObjectPool::IndexFromOffset(offset - kHeapObjectTag);
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return start;
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}
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// See comment in instructions_arm64.h
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uword InstructionPattern::DecodeLoadDoubleWordFromPool(uword end,
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Register* reg1,
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Register* reg2,
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intptr_t* index) {
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// Cases:
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//
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// 1. ldp reg1, reg2, [pp, offset]
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//
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// 2. add tmp, pp, #upper12
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// ldp reg1, reg2, [tmp, #lower12]
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//
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// 3. add tmp, pp, #upper12
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// add tmp, tmp, #lower12
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// ldp reg1, reg2, [tmp, 0]
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//
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// Note that the pp register is untagged!
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//
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uword start = end - Instr::kInstrSize;
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Instr* ldr_instr = Instr::At(start);
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// Last instruction is always an ldp into two 64-bit X registers.
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ASSERT(ldr_instr->IsLoadStoreRegPairOp() && (ldr_instr->Bit(22) == 1));
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// Grab the destination register from the ldp instruction.
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*reg1 = ldr_instr->RtField();
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*reg2 = ldr_instr->Rt2Field();
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Register base_reg = ldr_instr->RnField();
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const int base_offset = 8 * ldr_instr->Imm7Field();
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intptr_t pool_offset = 0;
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if (base_reg == PP) {
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// Case 1.
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pool_offset = base_offset;
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} else {
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// Case 2 & 3.
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ASSERT(base_reg == TMP);
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pool_offset = base_offset;
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start -= Instr::kInstrSize;
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Instr* add_instr = Instr::At(start);
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ASSERT(add_instr->IsAddSubImmOp());
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ASSERT(add_instr->RdField() == TMP);
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const auto shift = add_instr->Imm12ShiftField();
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ASSERT(shift == 0 || shift == 1);
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pool_offset += (add_instr->Imm12Field() << (shift == 1 ? 12 : 0));
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if (add_instr->RnField() == TMP) {
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start -= Instr::kInstrSize;
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Instr* prev_add_instr = Instr::At(start);
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ASSERT(prev_add_instr->IsAddSubImmOp());
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ASSERT(prev_add_instr->RnField() == PP);
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const auto shift = prev_add_instr->Imm12ShiftField();
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ASSERT(shift == 0 || shift == 1);
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pool_offset += (prev_add_instr->Imm12Field() << (shift == 1 ? 12 : 0));
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} else {
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ASSERT(add_instr->RnField() == PP);
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}
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}
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*index = ObjectPool::IndexFromOffset(pool_offset - kHeapObjectTag);
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return start;
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}
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bool DecodeLoadObjectFromPoolOrThread(uword pc, const Code& code, Object* obj) {
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ASSERT(code.ContainsInstructionAt(pc));
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Instr* instr = Instr::At(pc);
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if (instr->IsLoadStoreRegOp() && (instr->Bit(22) == 1) &&
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(instr->Bits(30, 2) == 3) && instr->Bit(24) == 1) {
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intptr_t offset = (instr->Imm12Field() << 3);
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if (instr->RnField() == PP) {
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// PP is untagged on ARM64.
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ASSERT(Utils::IsAligned(offset, 8));
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// A code object may have an object pool attached in bare instructions
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// mode if the v8 snapshot profile writer is active, but this pool cannot
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// be used for object loading.
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if (FLAG_use_bare_instructions) return false;
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intptr_t index = ObjectPool::IndexFromOffset(offset - kHeapObjectTag);
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const ObjectPool& pool = ObjectPool::Handle(code.object_pool());
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if (!pool.IsNull()) {
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if (pool.TypeAt(index) == ObjectPool::EntryType::kTaggedObject) {
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*obj = pool.ObjectAt(index);
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return true;
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}
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}
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} else if (instr->RnField() == THR) {
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return Thread::ObjectAtOffset(offset, obj);
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}
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}
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// TODO(rmacnak): Loads with offsets beyond 12 bits.
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return false;
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}
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// Encodes a load sequence ending at 'end'. Encodes a fixed length two
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// instruction load from the pool pointer in PP using the destination
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// register reg as a temporary for the base address.
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// Assumes that the location has already been validated for patching.
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void InstructionPattern::EncodeLoadWordFromPoolFixed(uword end,
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int32_t offset) {
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uword start = end - Instr::kInstrSize;
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Instr* instr = Instr::At(start);
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const int32_t upper12 = offset & 0x00fff000;
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const int32_t lower12 = offset & 0x00000fff;
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ASSERT((offset & 0xff000000) == 0); // Can't encode > 24 bits.
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ASSERT(((lower12 >> 3) << 3) == lower12); // 8-byte aligned.
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instr->SetImm12Bits(instr->InstructionBits(), lower12 >> 3);
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start -= Instr::kInstrSize;
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instr = Instr::At(start);
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instr->SetImm12Bits(instr->InstructionBits(), upper12 >> 12);
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instr->SetInstructionBits(instr->InstructionBits() | B22);
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}
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CodePtr CallPattern::TargetCode() const {
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return static_cast<CodePtr>(object_pool_.ObjectAt(target_code_pool_index_));
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}
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void CallPattern::SetTargetCode(const Code& target) const {
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object_pool_.SetObjectAt(target_code_pool_index_, target);
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// No need to flush the instruction cache, since the code is not modified.
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}
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ObjectPtr ICCallPattern::Data() const {
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return object_pool_.ObjectAt(data_pool_index_);
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}
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void ICCallPattern::SetData(const Object& data) const {
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ASSERT(data.IsArray() || data.IsICData() || data.IsMegamorphicCache());
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object_pool_.SetObjectAt(data_pool_index_, data);
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}
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CodePtr ICCallPattern::TargetCode() const {
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return static_cast<CodePtr>(object_pool_.ObjectAt(target_pool_index_));
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}
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void ICCallPattern::SetTargetCode(const Code& target) const {
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object_pool_.SetObjectAt(target_pool_index_, target);
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// No need to flush the instruction cache, since the code is not modified.
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}
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SwitchableCallPatternBase::SwitchableCallPatternBase(const Code& code)
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: object_pool_(ObjectPool::Handle(code.GetObjectPool())),
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data_pool_index_(-1),
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target_pool_index_(-1) {}
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ObjectPtr SwitchableCallPatternBase::data() const {
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return object_pool_.ObjectAt(data_pool_index_);
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}
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void SwitchableCallPatternBase::SetData(const Object& data) const {
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ASSERT(!Object::Handle(object_pool_.ObjectAt(data_pool_index_)).IsCode());
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object_pool_.SetObjectAt(data_pool_index_, data);
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}
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SwitchableCallPattern::SwitchableCallPattern(uword pc, const Code& code)
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: SwitchableCallPatternBase(code) {
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ASSERT(code.ContainsInstructionAt(pc));
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// Last instruction: blr lr.
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ASSERT(*(reinterpret_cast<uint32_t*>(pc) - 1) == 0xd63f03c0);
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Register ic_data_reg, code_reg;
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intptr_t pool_index;
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InstructionPattern::DecodeLoadDoubleWordFromPool(
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pc - 2 * Instr::kInstrSize, &ic_data_reg, &code_reg, &pool_index);
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ASSERT(ic_data_reg == R5);
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ASSERT(code_reg == CODE_REG);
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data_pool_index_ = pool_index;
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target_pool_index_ = pool_index + 1;
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}
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CodePtr SwitchableCallPattern::target() const {
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return static_cast<CodePtr>(object_pool_.ObjectAt(target_pool_index_));
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}
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void SwitchableCallPattern::SetTarget(const Code& target) const {
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ASSERT(Object::Handle(object_pool_.ObjectAt(target_pool_index_)).IsCode());
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object_pool_.SetObjectAt(target_pool_index_, target);
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}
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BareSwitchableCallPattern::BareSwitchableCallPattern(uword pc, const Code& code)
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: SwitchableCallPatternBase(code) {
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ASSERT(code.ContainsInstructionAt(pc));
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// Last instruction: blr lr.
|
|
ASSERT(*(reinterpret_cast<uint32_t*>(pc) - 1) == 0xd63f03c0);
|
|
|
|
Register ic_data_reg, code_reg;
|
|
intptr_t pool_index;
|
|
InstructionPattern::DecodeLoadDoubleWordFromPool(
|
|
pc - Instr::kInstrSize, &ic_data_reg, &code_reg, &pool_index);
|
|
ASSERT(ic_data_reg == R5);
|
|
ASSERT(code_reg == LR);
|
|
|
|
data_pool_index_ = pool_index;
|
|
target_pool_index_ = pool_index + 1;
|
|
}
|
|
|
|
CodePtr BareSwitchableCallPattern::target() const {
|
|
const uword pc = object_pool_.RawValueAt(target_pool_index_);
|
|
CodePtr result = ReversePc::Lookup(IsolateGroup::Current(), pc);
|
|
if (result != Code::null()) {
|
|
return result;
|
|
}
|
|
result = ReversePc::Lookup(Dart::vm_isolate()->group(), pc);
|
|
if (result != Code::null()) {
|
|
return result;
|
|
}
|
|
UNREACHABLE();
|
|
}
|
|
|
|
void BareSwitchableCallPattern::SetTarget(const Code& target) const {
|
|
ASSERT(object_pool_.TypeAt(target_pool_index_) ==
|
|
ObjectPool::EntryType::kImmediate);
|
|
object_pool_.SetRawValueAt(target_pool_index_,
|
|
target.MonomorphicEntryPoint());
|
|
}
|
|
|
|
ReturnPattern::ReturnPattern(uword pc) : pc_(pc) {}
|
|
|
|
bool ReturnPattern::IsValid() const {
|
|
Instr* bx_lr = Instr::At(pc_);
|
|
const Register crn = ConcreteRegister(LR);
|
|
const int32_t instruction = RET | (static_cast<int32_t>(crn) << kRnShift);
|
|
return bx_lr->InstructionBits() == instruction;
|
|
}
|
|
|
|
bool PcRelativeCallPattern::IsValid() const {
|
|
// bl <offset>
|
|
const uint32_t word = *reinterpret_cast<uint32_t*>(pc_);
|
|
const uint32_t branch_link = 0x25;
|
|
return (word >> 26) == branch_link;
|
|
}
|
|
|
|
bool PcRelativeTailCallPattern::IsValid() const {
|
|
// b <offset>
|
|
const uint32_t word = *reinterpret_cast<uint32_t*>(pc_);
|
|
const uint32_t branch_link = 0x5;
|
|
return (word >> 26) == branch_link;
|
|
}
|
|
|
|
void PcRelativeTrampolineJumpPattern::Initialize() {
|
|
#if !defined(DART_PRECOMPILED_RUNTIME)
|
|
uint32_t* pattern = reinterpret_cast<uint32_t*>(pattern_start_);
|
|
pattern[0] = kAdrEncoding;
|
|
pattern[1] = kMovzEncoding;
|
|
pattern[2] = kAddTmpTmp2;
|
|
pattern[3] = kJumpEncoding;
|
|
set_distance(0);
|
|
#else
|
|
UNREACHABLE();
|
|
#endif
|
|
}
|
|
|
|
int32_t PcRelativeTrampolineJumpPattern::distance() {
|
|
#if !defined(DART_PRECOMPILED_RUNTIME)
|
|
uint32_t* pattern = reinterpret_cast<uint32_t*>(pattern_start_);
|
|
const uint32_t adr = pattern[0];
|
|
const uint32_t movz = pattern[1];
|
|
const uint32_t lower16 =
|
|
(((adr >> 5) & ((1 << 19) - 1)) << 2) | ((adr >> 29) & 0x3);
|
|
const uint32_t higher16 = (movz >> kImm16Shift) & 0xffff;
|
|
return (higher16 << 16) | lower16;
|
|
#else
|
|
UNREACHABLE();
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
void PcRelativeTrampolineJumpPattern::set_distance(int32_t distance) {
|
|
#if !defined(DART_PRECOMPILED_RUNTIME)
|
|
uint32_t* pattern = reinterpret_cast<uint32_t*>(pattern_start_);
|
|
uint32_t low16 = distance & 0xffff;
|
|
uint32_t high16 = (distance >> 16) & 0xffff;
|
|
pattern[0] = kAdrEncoding | ((low16 & 0x3) << 29) | ((low16 >> 2) << 5);
|
|
pattern[1] = kMovzEncoding | (high16 << kImm16Shift);
|
|
ASSERT(IsValid());
|
|
#else
|
|
UNREACHABLE();
|
|
#endif
|
|
}
|
|
|
|
bool PcRelativeTrampolineJumpPattern::IsValid() const {
|
|
#if !defined(DART_PRECOMPILED_RUNTIME)
|
|
const uint32_t adr_mask = (3 << 29) | (((1 << 19) - 1) << 5);
|
|
const uint32_t movz_mask = 0xffff << 5;
|
|
uint32_t* pattern = reinterpret_cast<uint32_t*>(pattern_start_);
|
|
return ((pattern[0] & ~adr_mask) == kAdrEncoding) &&
|
|
((pattern[1] & ~movz_mask) == kMovzEncoding) &&
|
|
(pattern[2] == kAddTmpTmp2) && (pattern[3] == kJumpEncoding);
|
|
#else
|
|
UNREACHABLE();
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
intptr_t TypeTestingStubCallPattern::GetSubtypeTestCachePoolIndex() {
|
|
// Calls to the type testing stubs look like:
|
|
// ldr R9, ...
|
|
// ldr Rn, [PP+idx]
|
|
// blr R9
|
|
// or
|
|
// ldr Rn, [PP+idx]
|
|
// blr pc+<offset>
|
|
// where Rn = TypeTestABI::kSubtypeTestCacheReg.
|
|
|
|
// Ensure the caller of the type testing stub (whose return address is [pc_])
|
|
// branched via `blr R9` or a pc-relative call.
|
|
uword pc = pc_ - Instr::kInstrSize;
|
|
const uword blr_r9 = 0xd63f0120;
|
|
if (*reinterpret_cast<uint32_t*>(pc) != blr_r9) {
|
|
PcRelativeCallPattern pattern(pc);
|
|
RELEASE_ASSERT(pattern.IsValid());
|
|
}
|
|
|
|
const uword load_instr_end = pc;
|
|
|
|
Register reg;
|
|
intptr_t pool_index = -1;
|
|
InstructionPattern::DecodeLoadWordFromPool(load_instr_end, ®, &pool_index);
|
|
ASSERT_EQUAL(reg, TypeTestABI::kSubtypeTestCacheReg);
|
|
return pool_index;
|
|
}
|
|
|
|
} // namespace dart
|
|
|
|
#endif // defined TARGET_ARCH_ARM64
|