Ryan Macnak
04ba20aa98
Implements a backend targeting RV32GC and RV64GC, based on Linux standardizing around GC. The assembler is written to make it easy to disable usage of C, but because the sizes of some instruction sequences are compile-time constants, an additional build configuration would need to be defined to make use of it. The assembler and disassembler cover every RV32/64GC instruction. The simulator covers all instructions except accessing CSRs and the floating point state accessible through such, include accrued exceptions and dynamic rounding mode. Quirks: - RISC-V is a compare-and-branch architecture, but some existing "architecture-independent" parts of the Dart compiler assume a condition code architecture. To avoid rewriting these parts, we use a peephole in the assembler to map to compare-and-branch. See Assembler::BranchIf. Luckily nothing depended on taking multiple branches on the same condition code set. - There are no hardware overflow checks, so we must use Hacker's Delight style software checks. Often these are very cheap: if the sign of one operand is known, a single branch is needed. - The ranges of RISC-V branches and jumps are such that we use 3 levels of generation for forward branches, instead of the 2 levels of near and far branches used on ARM[64]. Nearly all code is handled by the first two levels with 20-bits of range, with enormous regex matchers triggering the third level that uses aupic+jalr to get 32-bits of range. - For PC-relative calls in AOT, we always generate auipc+jalr pairs with 32-bits of range, so we never generate trampolines. - Only a subset of registers are available in some compressed instructions, so we assign the most popular uses to these registers. In particular, THR, TMP[2], CODE and PP. This has the effect of assigning CODE and PP to volatile registers in the C calling convention, whereas they are assigned preserved registers on the other architectures. As on ARM64, PP is untagged; this is so short indices can be accessed with a compressed instruction. - There are no push or pop instructions, so combining pushes and pops is preferred so we can update SP once. - The C calling convention has a strongly aligned stack, but unlike on ARM64 we don't need to use an alternate stack pointer. The author ensured language was added to the RISC-V psABI making the OS responsible for realigning the stack pointer for signal handlers, allowing Dart to leave the stack pointer misaligned from the C calling convention's point of view until a foreign call. - We don't bother with the link register tracking done on ARM[64]. Instead we make use of an alternate link register to avoid inline spilling in the write barrier. Unimplemented: - non-trivial FFI cases - Compressed pointers - No intention to implement. - Unboxed SIMD - We might make use of the V extension registers when the V extension is ratified. - BigInt intrinsics TEST=existing tests for IL level, new tests for assembler/disassembler/simulator Bug: https://github.com/dart-lang/sdk/issues/38587 Bug: https://github.com/dart-lang/sdk/issues/48164 Change-Id: I991d1df4be5bf55efec5371b767b332d37dfa3e0 Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/217289 Reviewed-by: Alexander Markov <alexmarkov@google.com> Reviewed-by: Daco Harkes <dacoharkes@google.com> Reviewed-by: Slava Egorov <vegorov@google.com> Commit-Queue: Ryan Macnak <rmacnak@google.com>
76 lines
2.9 KiB
C++
76 lines
2.9 KiB
C++
// Copyright (c) 2021, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#ifndef RUNTIME_VM_STACK_FRAME_RISCV_H_
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#define RUNTIME_VM_STACK_FRAME_RISCV_H_
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#if !defined(RUNTIME_VM_STACK_FRAME_H_)
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#error Do not include stack_frame_riscv.h directly; use stack_frame.h instead.
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#endif
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namespace dart {
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/* RISC-V Dart Frame Layout
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| | <- TOS
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Callee frame | ... |
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| saved PP |
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| code object |
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| saved FP | (FP of current frame)
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| saved PC | (PC of current frame)
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+--------------------+
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Current frame | ... T| <- SP of current frame
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| first local T|
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| caller's PP T|
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| code object T| (current frame's code object)
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| caller's FP | <- FP of current frame
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| caller's RA | (PC of caller frame)
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+--------------------+
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Caller frame | last parameter | <- SP of caller frame
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| ... |
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T against a slot indicates it needs to be traversed during GC.
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*/
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static const int kDartFrameFixedSize = 4; // PP, FP, RA, PC marker.
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static const int kSavedPcSlotFromSp = -1;
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static const int kFirstObjectSlotFromFp = -1; // Used by GC to traverse stack.
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static const int kLastFixedObjectSlotFromFp = -2;
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static const int kFirstLocalSlotFromFp = -3;
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static const int kSavedCallerPpSlotFromFp = -2;
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static const int kPcMarkerSlotFromFp = -1;
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static const int kSavedCallerFpSlotFromFp = 0;
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static const int kSavedCallerPcSlotFromFp = 1;
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static const int kParamEndSlotFromFp = 1; // One slot past last parameter.
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static const int kCallerSpSlotFromFp = 2;
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static const int kLastParamSlotFromEntrySp = 0;
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// Entry and exit frame layout.
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#if defined(TARGET_ARCH_RISCV64)
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static const int kExitLinkSlotFromEntryFp = -28;
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#elif defined(TARGET_ARCH_RISCV32)
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static const int kExitLinkSlotFromEntryFp = -40;
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#endif
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COMPILE_ASSERT(kAbiPreservedCpuRegCount == 11);
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COMPILE_ASSERT(kAbiPreservedFpuRegCount == 12);
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// For FFI native -> Dart callbacks, this is the number of stack slots between
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// arguments passed on stack and arguments saved in callback prologue.
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//
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// 2 = return adddress (1) + saved frame pointer (1).
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//
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// If NativeCallbackTrampolines::Enabled(), then
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// kNativeCallbackTrampolineStackDelta must be added as well.
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constexpr intptr_t kCallbackSlotsBeforeSavedArguments = 2;
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// For FFI calls passing in TypedData, we save it on the stack before entering
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// a Dart frame. This denotes how to get to the backed up typed data.
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static const int kFfiCallerTypedDataSlotFromFp = kCallerSpSlotFromFp;
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} // namespace dart
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#endif // RUNTIME_VM_STACK_FRAME_RISCV_H_
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