zra@google.com
697364354b
Enables UnhandledException test for MIPS. Review URL: https://codereview.chromium.org//14289006 git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21898 260f80e4-7a28-3924-810f-c04153c831b5
513 lines
10 KiB
C++
513 lines
10 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#ifndef VM_CONSTANTS_MIPS_H_
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#define VM_CONSTANTS_MIPS_H_
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namespace dart {
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enum Register {
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R0 = 0,
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R1 = 1,
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kFirstFreeCpuRegister = 2,
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R2 = 2,
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R3 = 3,
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R4 = 4,
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R5 = 5,
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R6 = 6,
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R7 = 7,
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R8 = 8,
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R9 = 9,
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R10 = 10,
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R11 = 11,
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R12 = 12,
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R13 = 13,
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R14 = 14,
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R15 = 15,
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R16 = 16,
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R17 = 17,
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R18 = 18,
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R19 = 19,
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R20 = 20,
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R21 = 21,
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kLastFreeCpuRegister = 21,
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R22 = 22,
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R23 = 23,
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R24 = 24,
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R25 = 25,
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R26 = 26,
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R27 = 27,
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R28 = 28,
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R29 = 29,
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R30 = 30,
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R31 = 31,
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kNumberOfCpuRegisters = 32,
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kNoRegister = -1,
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// Register aliases.
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ZR = R0,
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AT = R1,
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V0 = R2,
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V1 = R3,
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A0 = R4,
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A1 = R5,
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A2 = R6,
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A3 = R7,
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T0 = R8,
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T1 = R9,
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T2 = R10,
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T3 = R11,
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T4 = R12,
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T5 = R13,
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T6 = R14,
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T7 = R15,
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S0 = R16,
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S1 = R17,
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S2 = R18,
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S3 = R19,
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S4 = R20,
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S5 = R21,
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S6 = R22,
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S7 = R23,
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T8 = R24,
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T9 = R25,
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K0 = R26,
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K1 = R27,
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GP = R28,
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SP = R29,
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FP = R30,
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RA = R31,
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};
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// Values for floating point registers.
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// Double-precision values use register pairs.
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enum FRegister {
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F0 = 0,
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F1 = 1,
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F2 = 2,
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F3 = 3,
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F4 = 4,
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F5 = 5,
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F6 = 6,
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F7 = 7,
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F8 = 8,
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F9 = 9,
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F10 = 10,
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F11 = 11,
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F12 = 12,
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F13 = 13,
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F14 = 14,
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F15 = 15,
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F16 = 16,
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F17 = 17,
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F18 = 18,
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F19 = 19,
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F20 = 20,
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F21 = 21,
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F22 = 22,
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F23 = 23,
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F24 = 24,
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F25 = 25,
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F26 = 26,
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F27 = 27,
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F28 = 28,
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F29 = 29,
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F30 = 30,
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F31 = 31,
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kNumberOfFRegisters = 32,
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kNoFRegister = -1,
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};
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// Architecture independent aliases.
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typedef FRegister FpuRegister;
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const FpuRegister FpuTMP = F0;
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const int kNumberOfFpuRegisters = kNumberOfFRegisters;
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const FpuRegister kNoFpuRegister = kNoFRegister;
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// Register aliases.
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const Register TMP1 = AT; // Used as scratch register by assembler.
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const Register TMP2 = T9; // Used as scratch register by assembler.
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const Register TMP = TMP1; // Arch independent flow graph compiler needs a
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// Register called TMP.
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const Register CTX = S6; // Caches current context in generated code.
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const Register PP = S7; // Caches object pool pointer in generated code.
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const Register SPREG = SP; // Stack pointer register.
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const Register FPREG = FP; // Frame pointer register.
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// The code that generates a comparison can be far away from the code that
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// generates the branch that uses the result of that comparison. In this case,
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// CMPRES is used for the result of the comparison.
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const Register CMPRES = T8;
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// Exception object is passed in this register to the catch handlers when an
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// exception is thrown.
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const Register kExceptionObjectReg = V0;
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// Stack trace object is passed in this register to the catch handlers when
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// an exception is thrown.
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const Register kStackTraceObjectReg = V1;
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typedef uint32_t RegList;
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const RegList kAllCpuRegistersList = 0xFFFFFFFF;
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const RegList kAbiArgumentCpuRegs =
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(1 << A0) | (1 << A1) | (1 << A2) | (1 << A3);
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const RegList kAbiPreservedCpuRegs =
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(1 << S0) | (1 << S1) | (1 << S2) | (1 << S3) |
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(1 << S4) | (1 << S5) | (1 << S6) | (1 << S7);
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const int kAbiPreservedCpuRegCount = 8;
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// FPU registers 20 - 31 are preserved across calls.
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const FRegister kAbiFirstPreservedFpuReg = F20;
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const FRegister kAbiLastPreservedFpuReg =
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static_cast<FRegister>(kNumberOfFRegisters - 1);
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// CPU registers available to Dart allocator.
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const RegList kDartAvailableCpuRegs =
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(1 << R2) | (1 << R3) | (1 << R4) | (1 << R5) |
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(1 << R6) | (1 << R7) | (1 << R8) | (1 << R9) |
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(1 << R10) | (1 << R11) | (1 << R12) | (1 << R13) |
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(1 << R14) | (1 << R15) | (1 << R16) | (1 << R17) |
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(1 << R18) | (1 << R19) | (1 << R20) | (1 << R21);
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const RegList kDartVolatileCpuRegs =
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kDartAvailableCpuRegs & ~kAbiPreservedCpuRegs;
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const int kDartVolatileCpuRegCount = 14;
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const Register kDartFirstVolatileCpuReg = R2;
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const Register kDartLastVolatileCpuReg = R15;
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// FPU registers 0 - 19 are not preserved across calls.
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const FRegister kDartFirstVolatileFpuReg = F0;
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const FRegister kDartLastVolatileFpuReg = F19;
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const int kDartVolatileFpuRegCount = 20;
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// Dart stack frame layout.
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static const int kLastParamSlotIndex = 3;
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static const int kFirstLocalSlotIndex = -2;
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// Values for the condition field.
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// There is no condition field on MIPS, but Conditions are used and passed
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// around by the intermediate language, so we need them here, too.
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enum Condition {
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EQ, // equal
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NE, // not equal
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GT, // greater than
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GE, // greater equal
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LT, // less than
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LE, // less equal
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VS, // overflow
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};
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// Constants used for the decoding or encoding of the individual fields of
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// instructions. Based on the "Table 4.25 CPU Instruction Format Fields".
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enum InstructionFields {
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kOpcodeShift = 26,
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kOpcodeBits = 6,
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kRsShift = 21,
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kRsBits = 5,
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kFmtShift = 21,
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kFmtBits = 5,
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kRtShift = 16,
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kRtBits = 5,
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kFtShift = 16,
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kFtBits = 5,
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kRdShift = 11,
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kRdBits = 5,
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kFsShift = 11,
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kFsBits = 5,
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kSaShift = 6,
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kSaBits = 5,
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kFdShift = 6,
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kFdBits = 5,
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kFunctionShift = 0,
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kFunctionBits = 6,
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kCop1FnShift = 0,
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kCop1FnBits = 6,
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kCop1SubShift = 21,
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kCop1SubBits = 5,
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kImmShift = 0,
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kImmBits = 16,
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kInstrShift = 0,
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kInstrBits = 26,
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kBreakCodeShift = 6,
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kBreakCodeBits = 20,
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kBranchOffsetMask = 0x0000ffff,
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};
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enum Opcode {
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SPECIAL = 0,
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REGIMM = 1,
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J = 2,
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JAL = 3,
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BEQ = 4,
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BNE = 5,
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BLEZ = 6,
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BGTZ = 7,
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ADDI = 8,
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ADDIU = 9,
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SLTI = 10,
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SLTIU = 11,
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ANDI = 12,
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ORI = 13,
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XORI = 14,
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LUI = 15,
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CPO0 = 16,
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COP1 = 17,
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COP2 = 18,
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COP1X = 19,
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BEQL = 20,
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BNEL = 21,
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BLEZL = 22,
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BGTZL = 23,
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SPECIAL2 = 28,
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JALX = 29,
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SPECIAL3 = 31,
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LB = 32,
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LH = 33,
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LWL = 34,
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LW = 35,
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LBU = 36,
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LHU = 37,
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LWR = 38,
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SB = 40,
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SH = 41,
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SWL = 42,
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SW = 43,
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SWR = 46,
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CACHE = 47,
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LL = 48,
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LWC1 = 49,
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LWC2 = 50,
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PREF = 51,
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LDC1 = 53,
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LDC2 = 54,
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SC = 56,
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SWC1 = 57,
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SWC2 = 58,
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SDC1 = 61,
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SDC2 = 62,
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};
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enum SpecialFunction {
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// SPECIAL opcodes.
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SLL = 0,
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MOVCI = 1,
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SRL = 2,
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SRA = 3,
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SLLV = 4,
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SRLV = 6,
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SRAV = 7,
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JR = 8,
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JALR = 9,
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MOVZ = 10,
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MOVN = 11,
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SYSCALL = 12,
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BREAK = 13,
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SYNC = 15,
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MFHI =16,
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MTHI = 17,
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MFLO = 18,
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MTLO = 19,
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MULT = 24,
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MULTU = 25,
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DIV = 26,
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DIVU = 27,
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ADD = 32,
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ADDU = 33,
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SUB = 34,
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SUBU = 35,
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AND = 36,
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OR = 37,
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XOR = 38,
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NOR = 39,
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SLT = 42,
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SLTU = 43,
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TGE = 48,
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TGEU = 49,
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TLT = 50,
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TLTU = 51,
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TEQ = 52,
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TNE = 54,
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// SPECIAL2 opcodes.
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CLZ = 32,
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CLO = 33,
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};
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enum RtRegImm {
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BLTZ = 0,
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BGEZ = 1,
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BLTZL = 2,
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BGEZL = 3,
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TGEI = 8,
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TGEIU = 9,
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TLTI = 10,
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TLTIU = 11,
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TEQI = 12,
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TNEI = 14,
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BLTZAL = 16,
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BGEZAL = 17,
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BLTZALL = 18,
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BGEZALL = 19,
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SYNCI = 31,
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};
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enum Cop1Function {
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COP1_ADD = 0,
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COP1_MOV = 6,
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};
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enum Cop1Sub {
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COP1_MF = 0,
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COP1_MT = 4,
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};
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enum Format {
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FMT_S = 16,
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FMT_D = 17,
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FMT_W = 20,
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FMT_L = 21,
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FMT_PS = 22,
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};
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class Instr {
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public:
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enum {
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kInstrSize = 4,
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};
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static const int32_t kBreakPointInstruction =
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(SPECIAL << kOpcodeShift) | (BREAK << kFunctionShift);
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static const int32_t kNopInstruction = 0;
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static const int32_t kStopMessageCode = 1;
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static const int32_t kRedirectCode = 2;
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static const int32_t kMsgMessageCode = 3;
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// Get the raw instruction bits.
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inline int32_t InstructionBits() const {
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return *reinterpret_cast<const int32_t*>(this);
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}
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// Set the raw instruction bits to value.
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inline void SetInstructionBits(int32_t value) {
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*reinterpret_cast<int32_t*>(this) = value;
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}
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// Read one particular bit out of the instruction bits.
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inline int32_t Bit(int nr) const {
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return (InstructionBits() >> nr) & 1;
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}
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// Read a bit field out of the instruction bits.
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inline int32_t Bits(int shift, int count) const {
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return (InstructionBits() >> shift) & ((1 << count) - 1);
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}
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// Accessors to the different named fields used in the MIPS encoding.
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inline Opcode OpcodeField() const {
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return static_cast<Opcode>(Bits(kOpcodeShift, kOpcodeBits));
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}
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inline Register RsField() const {
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return static_cast<Register>(Bits(kRsShift, kRsBits));
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}
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inline Register RtField() const {
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return static_cast<Register>(Bits(kRtShift, kRtBits));
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}
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inline Register RdField() const {
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return static_cast<Register>(Bits(kRdShift, kRdBits));
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}
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inline FRegister FsField() const {
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return static_cast<FRegister>(Bits(kFsShift, kFsBits));
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}
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inline FRegister FtField() const {
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return static_cast<FRegister>(Bits(kFtShift, kFtBits));
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}
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inline FRegister FdField() const {
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return static_cast<FRegister>(Bits(kFdShift, kFdBits));
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}
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inline int SaField() const {
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return Bits(kSaShift, kSaBits);
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}
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inline int32_t UImmField() const {
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return Bits(kImmShift, kImmBits);
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}
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inline int32_t SImmField() const {
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// Sign-extend the imm field.
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return (Bits(kImmShift, kImmBits) << (32 - kImmBits)) >> (32 - kImmBits);
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}
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inline int32_t BreakCodeField() const {
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return Bits(kBreakCodeShift, kBreakCodeBits);
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}
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inline SpecialFunction FunctionField() const {
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return static_cast<SpecialFunction>(Bits(kFunctionShift, kFunctionBits));
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}
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inline RtRegImm RegImmFnField() const {
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return static_cast<RtRegImm>(Bits(kRtShift, kRtBits));
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}
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inline bool IsBreakPoint() {
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return (OpcodeField() == SPECIAL) && (FunctionField() == BREAK);
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}
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inline Cop1Function Cop1FunctionField() const {
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return static_cast<Cop1Function>(Bits(kCop1FnShift, kCop1FnBits));
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}
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inline Cop1Sub Cop1SubField() const {
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return static_cast<Cop1Sub>(Bits(kCop1SubShift, kCop1SubBits));
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}
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inline bool HasFormat() const {
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return (OpcodeField() == COP1) && (Bit(25) == 1);
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}
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inline Format FormatField() const {
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return static_cast<Format>(Bits(kFmtShift, kFmtBits));
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}
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// Instructions are read out of a code stream. The only way to get a
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// reference to an instruction is to convert a pc. There is no way
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// to allocate or create instances of class Instr.
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// Use the At(pc) function to create references to Instr.
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static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
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private:
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DISALLOW_ALLOCATION();
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DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
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};
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} // namespace dart
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#endif // VM_CONSTANTS_MIPS_H_
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