regis@google.com
d79c7c1969
Implement error and exception handler stubs on ARM. Hook up simulator for object tests. Enable codegen and object tests on ARM. Review URL: https://codereview.chromium.org//14309004 git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21680 260f80e4-7a28-3924-810f-c04153c831b5
577 lines
17 KiB
C++
577 lines
17 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#ifndef VM_CONSTANTS_ARM_H_
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#define VM_CONSTANTS_ARM_H_
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#include "platform/assert.h"
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namespace dart {
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// We support both VFPv3-D16 and VFPv3-D32 profiles, but currently only one at
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// a time.
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#define VFPv3_D16
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#if defined(VFPv3_D16) == defined(VFPv3_D32)
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#error "Exactly one of VFPv3_D16 or VFPv3_D32 can be defined at a time."
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#endif
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enum Register {
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kFirstFreeCpuRegister = 0,
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R0 = 0,
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R1 = 1,
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R2 = 2,
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R3 = 3,
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R4 = 4,
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R5 = 5,
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R6 = 6,
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R7 = 7,
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R8 = 8,
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kLastFreeCpuRegister = 8,
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R9 = 9,
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R10 = 10,
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R11 = 11,
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R12 = 12,
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R13 = 13,
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R14 = 14,
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R15 = 15,
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FP = 11,
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IP = 12,
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SP = 13,
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LR = 14,
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PC = 15,
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kNumberOfCpuRegisters = 16,
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kNoRegister = -1,
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};
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// Values for single-precision floating point registers.
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enum SRegister {
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S0 = 0,
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S1 = 1,
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S2 = 2,
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S3 = 3,
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S4 = 4,
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S5 = 5,
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S6 = 6,
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S7 = 7,
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S8 = 8,
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S9 = 9,
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S10 = 10,
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S11 = 11,
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S12 = 12,
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S13 = 13,
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S14 = 14,
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S15 = 15,
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S16 = 16,
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S17 = 17,
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S18 = 18,
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S19 = 19,
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S20 = 20,
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S21 = 21,
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S22 = 22,
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S23 = 23,
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S24 = 24,
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S25 = 25,
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S26 = 26,
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S27 = 27,
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S28 = 28,
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S29 = 29,
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S30 = 30,
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S31 = 31,
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kNumberOfSRegisters = 32,
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kNoSRegister = -1,
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};
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// Values for double-precision floating point registers.
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enum DRegister {
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D0 = 0,
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D1 = 1,
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D2 = 2,
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D3 = 3,
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D4 = 4,
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D5 = 5,
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D6 = 6,
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D7 = 7,
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D8 = 8,
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D9 = 9,
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D10 = 10,
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D11 = 11,
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D12 = 12,
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D13 = 13,
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D14 = 14,
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D15 = 15,
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#ifdef VFPv3_D16
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kNumberOfDRegisters = 16,
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#else
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D16 = 16,
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D17 = 17,
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D18 = 18,
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D19 = 19,
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D20 = 20,
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D21 = 21,
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D22 = 22,
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D23 = 23,
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D24 = 24,
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D25 = 25,
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D26 = 26,
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D27 = 27,
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D28 = 28,
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D29 = 29,
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D30 = 30,
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D31 = 31,
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kNumberOfDRegisters = 32,
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#endif
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kNumberOfOverlappingDRegisters = 16,
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kNoDRegister = -1,
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};
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// Architecture independent aliases.
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typedef DRegister FpuRegister;
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const FpuRegister FpuTMP = D0;
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const int kNumberOfFpuRegisters = kNumberOfDRegisters;
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const FpuRegister kNoFpuRegister = kNoDRegister;
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// Register aliases.
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const Register TMP = IP; // Used as scratch register by assembler.
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const Register CTX = R9; // Caches current context in generated code.
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const Register PP = R10; // Caches object pool pointer in generated code.
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const Register SPREG = SP; // Stack pointer register.
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const Register FPREG = FP; // Frame pointer register.
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// Exception object is passed in this register to the catch handlers when an
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// exception is thrown.
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const Register kExceptionObjectReg = R0;
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// Stack trace object is passed in this register to the catch handlers when
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// an exception is thrown.
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const Register kStackTraceObjectReg = R1;
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// List of registers used in load/store multiple.
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typedef uint16_t RegList;
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const RegList kAllCpuRegistersList = 0xFFFF;
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// C++ ABI call registers.
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const RegList kAbiArgumentCpuRegs =
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(1 << R0) | (1 << R1) | (1 << R2) | (1 << R3);
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const RegList kAbiPreservedCpuRegs =
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(1 << R4) | (1 << R5) | (1 << R6) | (1 << R7) |
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(1 << R8) | (1 << R9) | (1 << R10);
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const int kAbiPreservedCpuRegCount = 7;
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const DRegister kAbiFirstPreservedFpuReg = D8;
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const DRegister kAbiLastPreservedFpuReg =
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static_cast<DRegister>(kNumberOfDRegisters - 1);
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// CPU registers available to Dart allocator.
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const RegList kDartAvailableCpuRegs =
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(1 << R0) | (1 << R1) | (1 << R2) | (1 << R3) |
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(1 << R4) | (1 << R5) | (1 << R6) | (1 << R7) | (1 << R8);
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// Registers available to Dart that are not preserved by runtime calls.
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const RegList kDartVolatileCpuRegs =
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kDartAvailableCpuRegs & ~kAbiPreservedCpuRegs;
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const int kDartVolatileCpuRegCount = 4;
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const DRegister kDartFirstVolatileFpuReg = D0;
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const DRegister kDartLastVolatileFpuReg = D7;
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const int kDartVolatileFpuRegCount = 8;
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// Dart stack frame layout.
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static const int kLastParamSlotIndex = 3;
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static const int kFirstLocalSlotIndex = -2;
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// Values for the condition field as defined in section A3.2.
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enum Condition {
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kNoCondition = -1,
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EQ = 0, // equal
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NE = 1, // not equal
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CS = 2, // carry set/unsigned higher or same
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CC = 3, // carry clear/unsigned lower
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MI = 4, // minus/negative
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PL = 5, // plus/positive or zero
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VS = 6, // overflow
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VC = 7, // no overflow
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HI = 8, // unsigned higher
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LS = 9, // unsigned lower or same
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GE = 10, // signed greater than or equal
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LT = 11, // signed less than
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GT = 12, // signed greater than
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LE = 13, // signed less than or equal
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AL = 14, // always (unconditional)
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kSpecialCondition = 15, // special condition (refer to section A3.2.1)
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kMaxCondition = 16,
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};
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// Opcodes for Data-processing instructions (instructions with a type 0 and 1)
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// as defined in section A3.4
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enum Opcode {
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kNoOperand = -1,
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AND = 0, // Logical AND
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EOR = 1, // Logical Exclusive OR
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SUB = 2, // Subtract
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RSB = 3, // Reverse Subtract
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ADD = 4, // Add
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ADC = 5, // Add with Carry
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SBC = 6, // Subtract with Carry
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RSC = 7, // Reverse Subtract with Carry
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TST = 8, // Test
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TEQ = 9, // Test Equivalence
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CMP = 10, // Compare
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CMN = 11, // Compare Negated
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ORR = 12, // Logical (inclusive) OR
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MOV = 13, // Move
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BIC = 14, // Bit Clear
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MVN = 15, // Move Not
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kMaxOperand = 16
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};
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// Shifter types for Data-processing operands as defined in section A5.1.2.
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enum Shift {
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kNoShift = -1,
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LSL = 0, // Logical shift left
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LSR = 1, // Logical shift right
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ASR = 2, // Arithmetic shift right
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ROR = 3, // Rotate right
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kMaxShift = 4
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};
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// Special Supervisor Call 24-bit codes used in the presence of the ARM
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// simulator for redirection, breakpoints, stop messages, and spill markers.
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// See /usr/include/asm/unistd.h
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const uint32_t kRedirectionSvcCode = 0x90001f; // unused syscall, was sys_stty
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const uint32_t kBreakpointSvcCode = 0x900020; // unused syscall, was sys_gtty
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const uint32_t kStopMessageSvcCode = 0x9f0001; // __ARM_NR_breakpoint
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const uint32_t kSpillMarkerSvcBase = 0x9f0100; // unused ARM private syscall
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const uint32_t kWordSpillMarkerSvcCode = kSpillMarkerSvcBase + 1;
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const uint32_t kDWordSpillMarkerSvcCode = kSpillMarkerSvcBase + 2;
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// Constants used for the decoding or encoding of the individual fields of
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// instructions. Based on the "Figure 3-1 ARM instruction set summary".
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enum InstructionFields {
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kConditionShift = 28,
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kConditionBits = 4,
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kTypeShift = 25,
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kTypeBits = 3,
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kLinkShift = 24,
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kLinkBits = 1,
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kUShift = 23,
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kUBits = 1,
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kOpcodeShift = 21,
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kOpcodeBits = 4,
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kSShift = 20,
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kSBits = 1,
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kRnShift = 16,
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kRnBits = 4,
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kRdShift = 12,
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kRdBits = 4,
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kRsShift = 8,
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kRsBits = 4,
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kRmShift = 0,
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kRmBits = 4,
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// Immediate instruction fields encoding.
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kRotateShift = 8,
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kRotateBits = 4,
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kImmed8Shift = 0,
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kImmed8Bits = 8,
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// Shift instruction register fields encodings.
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kShiftImmShift = 7,
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kShiftRegisterShift = 8,
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kShiftImmBits = 5,
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kShiftShift = 5,
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kShiftBits = 2,
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// Load/store instruction offset field encoding.
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kOffset12Shift = 0,
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kOffset12Bits = 12,
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kOffset12Mask = 0x00000fff,
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// Mul instruction register fields encodings.
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kMulRdShift = 16,
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kMulRdBits = 4,
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kMulRnShift = 12,
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kMulRnBits = 4,
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// MRC instruction offset field encoding.
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kCRmShift = 0,
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kCRmBits = 4,
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kOpc2Shift = 5,
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kOpc2Bits = 3,
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kCoprocShift = 8,
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kCoprocBits = 4,
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kCRnShift = 16,
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kCRnBits = 4,
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kOpc1Shift = 21,
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kOpc1Bits = 3,
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kBranchOffsetMask = 0x00ffffff
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};
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// The class Instr enables access to individual fields defined in the ARM
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// architecture instruction set encoding as described in figure A3-1.
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//
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// Example: Test whether the instruction at ptr sets the condition code bits.
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//
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// bool InstructionSetsConditionCodes(byte* ptr) {
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// Instr* instr = Instr::At(ptr);
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// int type = instr->TypeField();
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// return ((type == 0) || (type == 1)) && instr->HasS();
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// }
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//
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class Instr {
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public:
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enum {
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kInstrSize = 4,
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kInstrSizeLog2 = 2,
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kPCReadOffset = 8
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};
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static const int32_t kBreakPointInstruction = // svc #kBreakpointSvcCode
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((AL << kConditionShift) | (0xf << 24) | kBreakpointSvcCode);
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static const int kBreakPointInstructionSize = kInstrSize;
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bool IsBreakPoint() {
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return IsBkpt();
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}
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// Get the raw instruction bits.
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inline int32_t InstructionBits() const {
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return *reinterpret_cast<const int32_t*>(this);
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}
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// Set the raw instruction bits to value.
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inline void SetInstructionBits(int32_t value) {
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*reinterpret_cast<int32_t*>(this) = value;
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}
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// Read one particular bit out of the instruction bits.
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inline int Bit(int nr) const {
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return (InstructionBits() >> nr) & 1;
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}
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// Read a bit field out of the instruction bits.
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inline int Bits(int shift, int count) const {
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return (InstructionBits() >> shift) & ((1 << count) - 1);
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}
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// Accessors for the different named fields used in the ARM encoding.
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// The naming of these accessor corresponds to figure A3-1.
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// Generally applicable fields
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inline Condition ConditionField() const {
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return static_cast<Condition>(Bits(kConditionShift, kConditionBits));
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}
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inline int TypeField() const { return Bits(kTypeShift, kTypeBits); }
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inline Register RnField() const { return static_cast<Register>(
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Bits(kRnShift, kRnBits)); }
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inline Register RdField() const { return static_cast<Register>(
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Bits(kRdShift, kRdBits)); }
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// Fields used in Data processing instructions
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inline Opcode OpcodeField() const {
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return static_cast<Opcode>(Bits(kOpcodeShift, kOpcodeBits));
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}
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inline int SField() const { return Bits(kSShift, kSBits); }
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// with register
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inline Register RmField() const {
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return static_cast<Register>(Bits(kRmShift, kRmBits));
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}
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inline Shift ShiftField() const { return static_cast<Shift>(
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Bits(kShiftShift, kShiftBits)); }
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inline int RegShiftField() const { return Bit(4); }
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inline Register RsField() const {
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return static_cast<Register>(Bits(kRsShift, kRsBits));
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}
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inline int ShiftAmountField() const { return Bits(kShiftImmShift,
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kShiftImmBits); }
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// with immediate
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inline int RotateField() const { return Bits(kRotateShift, kRotateBits); }
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inline int Immed8Field() const { return Bits(kImmed8Shift, kImmed8Bits); }
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// Fields used in Load/Store instructions
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inline int PUField() const { return Bits(23, 2); }
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inline int BField() const { return Bit(22); }
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inline int WField() const { return Bit(21); }
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inline int LField() const { return Bit(20); }
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// with register uses same fields as Data processing instructions above
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// with immediate
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inline int Offset12Field() const { return Bits(kOffset12Shift,
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kOffset12Bits); }
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// multiple
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inline int RlistField() const { return Bits(0, 16); }
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// extra loads and stores
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inline int SignField() const { return Bit(6); }
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inline int HField() const { return Bit(5); }
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inline int ImmedHField() const { return Bits(8, 4); }
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inline int ImmedLField() const { return Bits(0, 4); }
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// Fields used in Branch instructions
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inline int LinkField() const { return Bits(kLinkShift, kLinkBits); }
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inline int SImmed24Field() const { return ((InstructionBits() << 8) >> 8); }
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// Fields used in Supervisor Call instructions
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inline uint32_t SvcField() const { return Bits(0, 24); }
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// Field used in Breakpoint instruction
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inline uint16_t BkptField() const {
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return ((Bits(8, 12) << 4) | Bits(0, 4));
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}
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// Field used in 16-bit immediate move instructions
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inline uint16_t MovwField() const {
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return ((Bits(16, 4) << 12) | Bits(0, 12));
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}
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// Field used in VFP float immediate move instruction
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inline float ImmFloatField() const {
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uint32_t imm32 = (Bit(19) << 31) | (((1 << 5) - Bit(18)) << 25) |
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(Bits(16, 2) << 23) | (Bits(0, 4) << 19);
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return bit_cast<float, uint32_t>(imm32);
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}
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// Field used in VFP double immediate move instruction
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inline double ImmDoubleField() const {
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uint64_t imm64 = (Bit(19)*(1LL << 63)) | (((1LL << 8) - Bit(18)) << 54) |
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(Bits(16, 2)*(1LL << 52)) | (Bits(0, 4)*(1LL << 48));
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return bit_cast<double, uint64_t>(imm64);
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}
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// Test for data processing instructions of type 0 or 1.
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// See "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition",
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// section A5.1 "ARM instruction set encoding".
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inline bool IsDataProcessing() const {
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ASSERT(ConditionField() != kSpecialCondition);
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ASSERT(Bits(26, 2) == 0); // Type 0 or 1.
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return ((Bits(20, 5) & 0x19) != 0x10) &&
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((Bit(25) == 1) || // Data processing immediate.
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(Bit(4) == 0) || // Data processing register.
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(Bit(7) == 0)); // Data processing register-shifted register.
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}
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// Tests for special encodings of type 0 instructions (extra loads and stores,
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// as well as multiplications, synchronization primitives, and miscellaneous).
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// Can only be called for a type 0 or 1 instruction.
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inline bool IsMiscellaneous() const {
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ASSERT(Bits(26, 2) == 0); // Type 0 or 1.
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return ((Bit(25) == 0) && ((Bits(20, 5) & 0x19) == 0x10) && (Bit(7) == 0));
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}
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inline bool IsMultiplyOrSyncPrimitive() const {
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ASSERT(Bits(26, 2) == 0); // Type 0 or 1.
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return ((Bit(25) == 0) && (Bits(4, 4) == 9));
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}
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// Test for Supervisor Call instruction.
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inline bool IsSvc() const {
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return ((InstructionBits() & 0x0f000000) == 0x0f000000);
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}
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// Test for Breakpoint instruction.
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inline bool IsBkpt() const {
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return ((InstructionBits() & 0x0ff000f0) == 0x01200070);
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}
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// VFP register fields.
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inline SRegister SnField() const {
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return static_cast<SRegister>((Bits(kRnShift, kRnBits) << 1) + Bit(7));
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}
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inline SRegister SdField() const {
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return static_cast<SRegister>((Bits(kRdShift, kRdBits) << 1) + Bit(22));
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}
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inline SRegister SmField() const {
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return static_cast<SRegister>((Bits(kRmShift, kRmBits) << 1) + Bit(5));
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}
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inline DRegister DnField() const {
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return static_cast<DRegister>(Bits(kRnShift, kRnBits) + (Bit(7) << 4));
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}
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inline DRegister DdField() const {
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return static_cast<DRegister>(Bits(kRdShift, kRdBits) + (Bit(22) << 4));
|
|
}
|
|
inline DRegister DmField() const {
|
|
return static_cast<DRegister>(Bits(kRmShift, kRmBits) + (Bit(5) << 4));
|
|
}
|
|
|
|
inline bool IsDivision() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 3);
|
|
return ((Bit(4) == 1) && (Bits(5, 3) == 0) &&
|
|
(Bit(20) == 1) && (Bits(22, 3) == 4));
|
|
}
|
|
|
|
// Test for VFP data processing or single transfer instructions of type 7.
|
|
inline bool IsVFPDataProcessingOrSingleTransfer() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 7);
|
|
return ((Bit(24) == 0) && (Bits(9, 3) == 5));
|
|
// Bit(4) == 0: Data Processing
|
|
// Bit(4) == 1: 8, 16, or 32-bit Transfer between ARM Core and VFP
|
|
}
|
|
|
|
// Test for VFP 64-bit transfer instructions of type 6.
|
|
inline bool IsVFPDoubleTransfer() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 6);
|
|
return ((Bits(21, 4) == 2) && (Bits(9, 3) == 5) &&
|
|
((Bits(4, 4) & 0xd) == 1));
|
|
}
|
|
|
|
// Test for VFP load and store instructions of type 6.
|
|
inline bool IsVFPLoadStore() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 6);
|
|
return ((Bits(20, 5) & 0x12) == 0x10) && (Bits(9, 3) == 5);
|
|
}
|
|
|
|
// Only handle mrc of the id_isar0 register.
|
|
inline bool IsMrcIdIsar0() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 7);
|
|
return (Bits(21, 3) == 0) && (Bits(16, 4) == 0) &&
|
|
(Bits(8, 4) == 0xf) && (Bits(5, 3) == 0) &&
|
|
(Bits(0, 4) == 2);
|
|
}
|
|
|
|
// Test for VFP multiple load and store instructions of type 6.
|
|
inline bool IsVFPMultipleLoadStore() const {
|
|
ASSERT(ConditionField() != kSpecialCondition);
|
|
ASSERT(TypeField() == 6);
|
|
int32_t puw = (PUField() << 1) | Bit(21); // don't care about D bit
|
|
return (Bits(9, 3) == 5) && ((puw == 2) || (puw == 3) || (puw == 5));
|
|
}
|
|
|
|
// Special accessors that test for existence of a value.
|
|
inline bool HasS() const { return SField() == 1; }
|
|
inline bool HasB() const { return BField() == 1; }
|
|
inline bool HasW() const { return WField() == 1; }
|
|
inline bool HasL() const { return LField() == 1; }
|
|
inline bool HasSign() const { return SignField() == 1; }
|
|
inline bool HasH() const { return HField() == 1; }
|
|
inline bool HasLink() const { return LinkField() == 1; }
|
|
|
|
// Instructions are read out of a code stream. The only way to get a
|
|
// reference to an instruction is to convert a pointer. There is no way
|
|
// to allocate or create instances of class Instr.
|
|
// Use the At(pc) function to create references to Instr.
|
|
static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
|
|
|
|
private:
|
|
DISALLOW_ALLOCATION();
|
|
DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
|
|
};
|
|
|
|
} // namespace dart
|
|
|
|
#endif // VM_CONSTANTS_ARM_H_
|