zra@google.com
fabc87d633
Now, all VM tests that pass on SIMARM, pass on ARM. Also, more assertions in the ARM disassembler and simulator to make sure that condition codes aren't used with bkpt. R=regis@google.com Review URL: https://codereview.chromium.org//14784011 git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22471 260f80e4-7a28-3924-810f-c04153c831b5
1316 lines
38 KiB
C++
1316 lines
38 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#include "vm/disassembler.h"
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#include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
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#if defined(TARGET_ARCH_ARM)
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#include "platform/assert.h"
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namespace dart {
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class ARMDecoder : public ValueObject {
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public:
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ARMDecoder(char* buffer, size_t buffer_size)
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: buffer_(buffer),
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buffer_size_(buffer_size),
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buffer_pos_(0) {
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buffer_[buffer_pos_] = '\0';
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}
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~ARMDecoder() {}
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// Writes one disassembled instruction into 'buffer' (0-terminated).
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// Returns true if the instruction was successfully decoded, false otherwise.
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void InstructionDecode(uword pc);
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private:
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// Bottleneck functions to print into the out_buffer.
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void Print(const char* str);
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// Printing of common values.
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void PrintRegister(int reg);
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void PrintSRegister(int reg);
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void PrintDRegister(int reg);
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void PrintCondition(Instr* instr);
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void PrintShiftRm(Instr* instr);
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void PrintShiftImm(Instr* instr);
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void PrintPU(Instr* instr);
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// Handle formatting of instructions and their options.
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int FormatRegister(Instr* instr, const char* option);
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int FormatSRegister(Instr* instr, const char* option);
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int FormatDRegister(Instr* instr, const char* option);
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int FormatOption(Instr* instr, const char* option);
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void Format(Instr* instr, const char* format);
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void Unknown(Instr* instr);
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// Each of these functions decodes one particular instruction type, a 3-bit
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// field in the instruction encoding.
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// Types 0 and 1 are combined as they are largely the same except for the way
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// they interpret the shifter operand.
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void DecodeType01(Instr* instr);
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void DecodeType2(Instr* instr);
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void DecodeType3(Instr* instr);
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void DecodeType4(Instr* instr);
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void DecodeType5(Instr* instr);
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void DecodeType6(Instr* instr);
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void DecodeType7(Instr* instr);
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// Convenience functions.
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char* get_buffer() const { return buffer_; }
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char* current_position_in_buffer() { return buffer_ + buffer_pos_; }
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size_t remaining_size_in_buffer() { return buffer_size_ - buffer_pos_; }
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char* buffer_; // Decode instructions into this buffer.
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size_t buffer_size_; // The size of the character buffer.
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size_t buffer_pos_; // Current character position in buffer.
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DISALLOW_ALLOCATION();
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DISALLOW_COPY_AND_ASSIGN(ARMDecoder);
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};
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// Support for assertions in the ARMDecoder formatting functions.
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#define STRING_STARTS_WITH(string, compare_string) \
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(strncmp(string, compare_string, strlen(compare_string)) == 0)
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// Append the str to the output buffer.
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void ARMDecoder::Print(const char* str) {
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char cur = *str++;
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while (cur != '\0' && (buffer_pos_ < (buffer_size_ - 1))) {
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buffer_[buffer_pos_++] = cur;
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cur = *str++;
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}
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buffer_[buffer_pos_] = '\0';
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}
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// These condition names are defined in a way to match the native disassembler
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// formatting. See for example the command "objdump -d <binary file>".
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static const char* cond_names[kMaxCondition] = {
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"eq", "ne", "cs" , "cc" , "mi" , "pl" , "vs" , "vc" ,
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"hi", "ls", "ge", "lt", "gt", "le", "", "invalid",
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};
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// Print the condition guarding the instruction.
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void ARMDecoder::PrintCondition(Instr* instr) {
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Print(cond_names[instr->ConditionField()]);
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}
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// These register names are defined in a way to match the native disassembler
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// formatting, except for register aliases ctx (r9) and pp (r10).
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// See for example the command "objdump -d <binary file>".
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static const char* reg_names[kNumberOfCpuRegisters] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "ctx", "pp", "fp", "ip", "sp", "lr", "pc",
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};
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// Print the register name according to the active name converter.
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void ARMDecoder::PrintRegister(int reg) {
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ASSERT(0 <= reg);
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ASSERT(reg < kNumberOfCpuRegisters);
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Print(reg_names[reg]);
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}
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void ARMDecoder::PrintSRegister(int reg) {
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ASSERT(0 <= reg);
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ASSERT(reg < kNumberOfSRegisters);
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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"s%d", reg);
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}
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void ARMDecoder::PrintDRegister(int reg) {
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ASSERT(0 <= reg);
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ASSERT(reg < kNumberOfDRegisters);
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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"d%d", reg);
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}
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// These shift names are defined in a way to match the native disassembler
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// formatting. See for example the command "objdump -d <binary file>".
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static const char* shift_names[kMaxShift] = {
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"lsl", "lsr", "asr", "ror"
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};
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// Print the register shift operands for the instruction. Generally used for
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// data processing instructions.
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void ARMDecoder::PrintShiftRm(Instr* instr) {
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Shift shift = instr->ShiftField();
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int shift_amount = instr->ShiftAmountField();
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int rm = instr->RmField();
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PrintRegister(rm);
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if ((instr->RegShiftField() == 0) && (shift == LSL) && (shift_amount == 0)) {
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// Special case for using rm only.
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return;
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}
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if (instr->RegShiftField() == 0) {
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// by immediate
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if ((shift == ROR) && (shift_amount == 0)) {
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Print(", RRX");
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return;
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} else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
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shift_amount = 32;
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}
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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", %s #%d",
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shift_names[shift],
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shift_amount);
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} else {
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// by register
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int rs = instr->RsField();
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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", %s ",
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shift_names[shift]);
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PrintRegister(rs);
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}
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}
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// Print the immediate operand for the instruction. Generally used for data
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// processing instructions.
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void ARMDecoder::PrintShiftImm(Instr* instr) {
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int rotate = instr->RotateField() * 2;
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int immed8 = instr->Immed8Field();
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int imm = (immed8 >> rotate) | (immed8 << (32 - rotate));
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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"#%d",
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imm);
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}
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// Print PU formatting to reduce complexity of FormatOption.
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void ARMDecoder::PrintPU(Instr* instr) {
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switch (instr->PUField()) {
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case 0: {
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Print("da");
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break;
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}
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case 1: {
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Print("ia");
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break;
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}
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case 2: {
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Print("db");
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break;
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}
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case 3: {
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Print("ib");
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break;
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}
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default: {
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UNREACHABLE();
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break;
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}
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}
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}
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// Handle all register based formatting in these functions to reduce the
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// complexity of FormatOption.
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int ARMDecoder::FormatRegister(Instr* instr, const char* format) {
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ASSERT(format[0] == 'r');
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if (format[1] == 'n') { // 'rn: Rn register
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int reg = instr->RnField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 'd') { // 'rd: Rd register
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int reg = instr->RdField();
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PrintRegister(reg);
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if (format[2] == '2') { // 'rd2: possibly Rd, Rd+1 register pair
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if (instr->HasSign() && !instr->HasL()) {
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if ((reg % 2) != 0) {
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Print(" *** unknown (odd register pair) ***");
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} else {
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Print(", ");
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PrintRegister(reg + 1);
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}
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}
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return 3;
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}
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return 2;
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} else if (format[1] == 's') { // 'rs: Rs register
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int reg = instr->RsField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 'm') { // 'rm: Rm register
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int reg = instr->RmField();
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PrintRegister(reg);
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return 2;
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} else if (format[1] == 'l') {
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// 'rlist: register list for load and store multiple instructions
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ASSERT(STRING_STARTS_WITH(format, "rlist"));
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int rlist = instr->RlistField();
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int reg = 0;
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Print("{");
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// Print register list in ascending order, by scanning the bit mask.
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while (rlist != 0) {
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if ((rlist & 1) != 0) {
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PrintRegister(reg);
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if ((rlist >> 1) != 0) {
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Print(", ");
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}
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}
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reg++;
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rlist >>= 1;
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}
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Print("}");
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return 5;
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}
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UNREACHABLE();
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return -1;
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}
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int ARMDecoder::FormatSRegister(Instr* instr, const char* format) {
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ASSERT(format[0] == 's');
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if (format[1] == 'n') { // 'sn: Sn register
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int reg = instr->SnField();
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PrintSRegister(reg);
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return 2;
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} else if (format[1] == 'd') { // 'sd: Sd register
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int reg = instr->SdField();
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PrintSRegister(reg);
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return 2;
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} else if (format[1] == 'm') {
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int reg = instr->SmField();
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if (format[2] == '1') { // 'sm1: S[m+1] register
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reg++;
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ASSERT(reg < kNumberOfSRegisters);
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PrintSRegister(reg);
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return 3;
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} else { // 'sm: Sm register
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PrintSRegister(reg);
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return 2;
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}
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} else if (format[1] == 'l') {
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ASSERT(STRING_STARTS_WITH(format, "slist"));
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int reg_count = instr->Bits(0, 8);
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int start = instr->Bit(22) | (instr->Bits(12, 4) << 1);
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Print("{");
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for (int i = start; i < start + reg_count; i++) {
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PrintSRegister(i);
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if (i != start + reg_count - 1) {
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Print(", ");
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}
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}
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Print("}");
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return 5;
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}
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UNREACHABLE();
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return -1;
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}
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int ARMDecoder::FormatDRegister(Instr* instr, const char* format) {
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ASSERT(format[0] == 'd');
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if (format[1] == 'n') { // 'dn: Dn register
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int reg = instr->DnField();
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PrintDRegister(reg);
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return 2;
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} else if (format[1] == 'd') { // 'dd: Dd register
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int reg = instr->DdField();
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PrintDRegister(reg);
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return 2;
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} else if (format[1] == 'm') { // 'dm: Dm register
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int reg = instr->DmField();
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PrintDRegister(reg);
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return 2;
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} else if (format[1] == 'l') {
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ASSERT(STRING_STARTS_WITH(format, "dlist"));
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int reg_count = instr->Bits(0, 8) >> 1;
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int start = (instr->Bit(22) << 4) | instr->Bits(12, 4);
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Print("{");
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for (int i = start; i < start + reg_count; i++) {
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PrintDRegister(i);
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if (i != start + reg_count - 1) {
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Print(", ");
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}
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}
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Print("}");
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return 5;
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}
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UNREACHABLE();
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return -1;
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}
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// FormatOption takes a formatting string and interprets it based on
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// the current instructions. The format string points to the first
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// character of the option string (the option escape has already been
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// consumed by the caller.) FormatOption returns the number of
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// characters that were consumed from the formatting string.
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int ARMDecoder::FormatOption(Instr* instr, const char* format) {
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switch (format[0]) {
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case 'a': { // 'a: accumulate multiplies
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if (instr->Bit(21) == 0) {
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Print("ul");
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} else {
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Print("la");
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}
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return 1;
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}
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case 'b': { // 'b: byte loads or stores
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if (instr->HasB()) {
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Print("b");
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}
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return 1;
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}
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case 'c': { // 'cond: conditional execution
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ASSERT(STRING_STARTS_WITH(format, "cond"));
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PrintCondition(instr);
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return 4;
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}
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case 'd': {
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if (format[1] == 'e') { // 'dest: branch destination
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ASSERT(STRING_STARTS_WITH(format, "dest"));
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int off = (instr->SImmed24Field() << 2) + 8;
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uword destination = reinterpret_cast<uword>(instr) + off;
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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"%#"Px"",
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destination);
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return 4;
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} else {
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return FormatDRegister(instr, format);
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}
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}
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case 'i': { // 'imm12_4, imm4_12, immf, or immd
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uint16_t immed16;
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if (format[3] == 'f') {
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ASSERT(STRING_STARTS_WITH(format, "immf"));
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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"%f",
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instr->ImmFloatField());
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return 4;
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} else if (format[3] == 'd') {
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ASSERT(STRING_STARTS_WITH(format, "immd"));
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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"%g",
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instr->ImmDoubleField());
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return 4;
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} else if (format[3] == '1') {
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ASSERT(STRING_STARTS_WITH(format, "imm12_4"));
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immed16 = instr->BkptField();
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} else {
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ASSERT(STRING_STARTS_WITH(format, "imm4_12"));
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immed16 = instr->MovwField();
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}
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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"0x%x",
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immed16);
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return 7;
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}
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case 'l': { // 'l: branch and link
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if (instr->HasLink()) {
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Print("l");
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}
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return 1;
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}
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case 'm': { // 'memop: load/store instructions
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ASSERT(STRING_STARTS_WITH(format, "memop"));
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if (instr->HasL() ||
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// Extra load/store instructions.
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((instr->TypeField() == 0) && instr->HasSign() && !instr->HasH())) {
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Print("ldr");
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} else {
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Print("str");
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}
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return 5;
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}
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case 'o': {
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if (format[3] == '1') {
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if (format[4] == '0') {
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// 'off10: 10-bit offset for VFP load and store instructions
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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"%d",
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instr->Bits(0, 8) << 2);
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} else {
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// 'off12: 12-bit offset for load and store instructions
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ASSERT(STRING_STARTS_WITH(format, "off12"));
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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"%d",
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instr->Offset12Field());
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}
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return 5;
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}
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// 'off8: 8-bit offset for extra load and store instructions
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ASSERT(STRING_STARTS_WITH(format, "off8"));
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int offs8 = (instr->ImmedHField() << 4) | instr->ImmedLField();
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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"%d",
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offs8);
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return 4;
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}
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case 'p': { // 'pu: P and U bits for load and store instructions
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ASSERT(STRING_STARTS_WITH(format, "pu"));
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PrintPU(instr);
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return 2;
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}
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case 'r': {
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return FormatRegister(instr, format);
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}
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case 's': {
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if (format[1] == 'h') { // 'shift_op or 'shift_rm
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if (format[6] == 'o') { // 'shift_op
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ASSERT(STRING_STARTS_WITH(format, "shift_op"));
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if (instr->TypeField() == 0) {
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PrintShiftRm(instr);
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} else {
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ASSERT(instr->TypeField() == 1);
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PrintShiftImm(instr);
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}
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return 8;
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} else { // 'shift_rm
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ASSERT(STRING_STARTS_WITH(format, "shift_rm"));
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PrintShiftRm(instr);
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return 8;
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}
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} else if (format[1] == 'v') { // 'svc
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ASSERT(STRING_STARTS_WITH(format, "svc"));
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buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
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remaining_size_in_buffer(),
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"0x%x",
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instr->SvcField());
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return 3;
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} else if (format[1] == ' ') {
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// 's: S field of data processing instructions
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if (instr->HasS()) {
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Print("s");
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}
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return 1;
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} else {
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return FormatSRegister(instr, format);
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}
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}
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case 't': { // 'target: target of branch instructions
|
|
ASSERT(STRING_STARTS_WITH(format, "target"));
|
|
int off = (instr->SImmed24Field() << 2) + 8;
|
|
buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
|
|
remaining_size_in_buffer(),
|
|
"%+d",
|
|
off);
|
|
return 6;
|
|
}
|
|
case 'u': { // 'u: signed or unsigned multiplies
|
|
if (instr->Bit(22) == 0) {
|
|
Print("u");
|
|
} else {
|
|
Print("s");
|
|
}
|
|
return 1;
|
|
}
|
|
case 'w': { // 'w: W field of load and store instructions
|
|
if (instr->HasW()) {
|
|
Print("!");
|
|
}
|
|
return 1;
|
|
}
|
|
case 'x': { // 'x: type of extra load/store instructions
|
|
if (!instr->HasSign()) {
|
|
Print("h");
|
|
} else if (instr->HasL()) {
|
|
if (instr->HasH()) {
|
|
Print("sh");
|
|
} else {
|
|
Print("sb");
|
|
}
|
|
} else {
|
|
Print("d");
|
|
}
|
|
return 1;
|
|
}
|
|
default: {
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
UNREACHABLE();
|
|
return -1;
|
|
}
|
|
|
|
|
|
// Format takes a formatting string for a whole instruction and prints it into
|
|
// the output buffer. All escaped options are handed to FormatOption to be
|
|
// parsed further.
|
|
void ARMDecoder::Format(Instr* instr, const char* format) {
|
|
char cur = *format++;
|
|
while ((cur != 0) && (buffer_pos_ < (buffer_size_ - 1))) {
|
|
if (cur == '\'') { // Single quote is used as the formatting escape.
|
|
format += FormatOption(instr, format);
|
|
} else {
|
|
buffer_[buffer_pos_++] = cur;
|
|
}
|
|
cur = *format++;
|
|
}
|
|
buffer_[buffer_pos_] = '\0';
|
|
}
|
|
|
|
|
|
// For currently unimplemented decodings the disassembler calls Unknown(instr)
|
|
// which will just print "unknown" of the instruction bits.
|
|
void ARMDecoder::Unknown(Instr* instr) {
|
|
Format(instr, "unknown");
|
|
}
|
|
|
|
|
|
void ARMDecoder::DecodeType01(Instr* instr) {
|
|
if (!instr->IsDataProcessing()) {
|
|
// miscellaneous, multiply, sync primitives, extra loads and stores.
|
|
if (instr->IsMiscellaneous()) {
|
|
switch (instr->Bits(4, 3)) {
|
|
case 1: {
|
|
if (instr->Bits(21, 2) == 0x3) {
|
|
Format(instr, "clz'cond 'rd, 'rm");
|
|
} else if (instr->Bits(21, 2) == 0x1) {
|
|
Format(instr, "bx'cond 'rm");
|
|
} else {
|
|
Unknown(instr);
|
|
}
|
|
break;
|
|
}
|
|
case 3: {
|
|
if (instr->Bits(21, 2) == 0x1) {
|
|
Format(instr, "blx'cond 'rm");
|
|
} else {
|
|
// Could be inlined constant.
|
|
Unknown(instr);
|
|
}
|
|
break;
|
|
}
|
|
case 7: {
|
|
if ((instr->Bits(21, 2) == 0x1) && (instr->ConditionField() == AL)) {
|
|
Format(instr, "bkpt #'imm12_4");
|
|
} else {
|
|
// Format(instr, "smc'cond");
|
|
Unknown(instr); // Not used.
|
|
}
|
|
break;
|
|
}
|
|
default: {
|
|
Unknown(instr); // Not used.
|
|
break;
|
|
}
|
|
}
|
|
} else if (instr->IsMultiplyOrSyncPrimitive()) {
|
|
if (instr->Bit(24) == 0) {
|
|
// multiply instructions
|
|
switch (instr->Bits(21, 3)) {
|
|
case 0: {
|
|
// Assembler registers rd, rn, rm are encoded as rn, rm, rs.
|
|
Format(instr, "mul'cond's 'rn, 'rm, 'rs");
|
|
break;
|
|
}
|
|
case 1: {
|
|
// Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
|
|
Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
|
|
break;
|
|
}
|
|
case 3: {
|
|
// Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
|
|
Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
|
|
break;
|
|
}
|
|
case 4: {
|
|
// Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
|
|
Format(instr, "umull'cond's 'rd, 'rn, 'rm, 'rs");
|
|
break;
|
|
}
|
|
case 6: {
|
|
// Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
|
|
Format(instr, "smull'cond's 'rd, 'rn, 'rm, 'rs");
|
|
break;
|
|
}
|
|
default: {
|
|
Unknown(instr); // Not used.
|
|
break;
|
|
}
|
|
}
|
|
} else {
|
|
// synchronization primitives
|
|
switch (instr->Bits(20, 4)) {
|
|
case 8: {
|
|
Format(instr, "strex'cond 'rd, 'rm, ['rn]");
|
|
break;
|
|
}
|
|
case 9: {
|
|
Format(instr, "ldrex'cond 'rd, ['rn]");
|
|
break;
|
|
}
|
|
default: {
|
|
Unknown(instr); // Not used.
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
} else if (instr->Bit(25) == 1) {
|
|
// 16-bit immediate loads, msr (immediate), and hints
|
|
switch (instr->Bits(20, 5)) {
|
|
case 16: {
|
|
Format(instr, "movw'cond 'rd, #'imm4_12");
|
|
break;
|
|
}
|
|
case 18: {
|
|
if ((instr->Bits(16, 4) == 0) && (instr->Bits(0, 8) == 0)) {
|
|
Format(instr, "nop'cond");
|
|
} else {
|
|
Unknown(instr); // Not used.
|
|
}
|
|
break;
|
|
}
|
|
case 20: {
|
|
Format(instr, "movt'cond 'rd, #'imm4_12");
|
|
break;
|
|
}
|
|
default: {
|
|
Unknown(instr); // Not used.
|
|
break;
|
|
}
|
|
}
|
|
} else {
|
|
// extra load/store instructions
|
|
switch (instr->PUField()) {
|
|
case 0: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond'x 'rd2, ['rn], -'rm");
|
|
} else {
|
|
Format(instr, "'memop'cond'x 'rd2, ['rn], #-'off8");
|
|
}
|
|
break;
|
|
}
|
|
case 1: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond'x 'rd2, ['rn], +'rm");
|
|
} else {
|
|
Format(instr, "'memop'cond'x 'rd2, ['rn], #+'off8");
|
|
}
|
|
break;
|
|
}
|
|
case 2: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond'x 'rd2, ['rn, -'rm]'w");
|
|
} else {
|
|
Format(instr, "'memop'cond'x 'rd2, ['rn, #-'off8]'w");
|
|
}
|
|
break;
|
|
}
|
|
case 3: {
|
|
if (instr->Bit(22) == 0) {
|
|
Format(instr, "'memop'cond'x 'rd2, ['rn, +'rm]'w");
|
|
} else {
|
|
Format(instr, "'memop'cond'x 'rd2, ['rn, #+'off8]'w");
|
|
}
|
|
break;
|
|
}
|
|
default: {
|
|
// The PU field is a 2-bit field.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
switch (instr->OpcodeField()) {
|
|
case AND: {
|
|
Format(instr, "and'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case EOR: {
|
|
Format(instr, "eor'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case SUB: {
|
|
Format(instr, "sub'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case RSB: {
|
|
Format(instr, "rsb'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case ADD: {
|
|
Format(instr, "add'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case ADC: {
|
|
Format(instr, "adc'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case SBC: {
|
|
Format(instr, "sbc'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case RSC: {
|
|
Format(instr, "rsc'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case TST: {
|
|
if (instr->HasS()) {
|
|
Format(instr, "tst'cond 'rn, 'shift_op");
|
|
} else {
|
|
Unknown(instr); // Not used.
|
|
}
|
|
break;
|
|
}
|
|
case TEQ: {
|
|
if (instr->HasS()) {
|
|
Format(instr, "teq'cond 'rn, 'shift_op");
|
|
} else {
|
|
Unknown(instr); // Not used.
|
|
}
|
|
break;
|
|
}
|
|
case CMP: {
|
|
if (instr->HasS()) {
|
|
Format(instr, "cmp'cond 'rn, 'shift_op");
|
|
} else {
|
|
Unknown(instr); // Not used.
|
|
}
|
|
break;
|
|
}
|
|
case CMN: {
|
|
if (instr->HasS()) {
|
|
Format(instr, "cmn'cond 'rn, 'shift_op");
|
|
} else {
|
|
Unknown(instr); // Not used.
|
|
}
|
|
break;
|
|
}
|
|
case ORR: {
|
|
Format(instr, "orr'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case MOV: {
|
|
Format(instr, "mov'cond's 'rd, 'shift_op");
|
|
break;
|
|
}
|
|
case BIC: {
|
|
Format(instr, "bic'cond's 'rd, 'rn, 'shift_op");
|
|
break;
|
|
}
|
|
case MVN: {
|
|
Format(instr, "mvn'cond's 'rd, 'shift_op");
|
|
break;
|
|
}
|
|
default: {
|
|
// The Opcode field is a 4-bit field.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void ARMDecoder::DecodeType2(Instr* instr) {
|
|
switch (instr->PUField()) {
|
|
case 0: {
|
|
if (instr->HasW()) {
|
|
Unknown(instr); // Not used.
|
|
} else {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
|
|
}
|
|
break;
|
|
}
|
|
case 1: {
|
|
if (instr->HasW()) {
|
|
Unknown(instr); // Not used.
|
|
} else {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
|
|
}
|
|
break;
|
|
}
|
|
case 2: {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
|
|
break;
|
|
}
|
|
case 3: {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
|
|
break;
|
|
}
|
|
default: {
|
|
// The PU field is a 2-bit field.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void ARMDecoder::DecodeType3(Instr* instr) {
|
|
if (instr->IsDivision()) {
|
|
if (instr->Bit(21)) {
|
|
Format(instr, "udiv'cond 'rn, 'rs, 'rm");
|
|
} else {
|
|
Format(instr, "sdiv'cond 'rn, 'rs, 'rm");
|
|
}
|
|
return;
|
|
}
|
|
switch (instr->PUField()) {
|
|
case 0: {
|
|
if (instr->HasW()) {
|
|
Unknown(instr);
|
|
} else {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
|
|
}
|
|
break;
|
|
}
|
|
case 1: {
|
|
if (instr->HasW()) {
|
|
Unknown(instr);
|
|
} else {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
|
|
}
|
|
break;
|
|
}
|
|
case 2: {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
|
|
break;
|
|
}
|
|
case 3: {
|
|
Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
|
|
break;
|
|
}
|
|
default: {
|
|
// The PU field is a 2-bit field.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void ARMDecoder::DecodeType4(Instr* instr) {
|
|
if (instr->Bit(22) == 1) {
|
|
Unknown(instr); // Privileged mode currently not supported.
|
|
} else if (instr->HasL()) {
|
|
Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
|
|
} else {
|
|
Format(instr, "stm'cond'pu 'rn'w, 'rlist");
|
|
}
|
|
}
|
|
|
|
|
|
void ARMDecoder::DecodeType5(Instr* instr) {
|
|
Format(instr, "b'l'cond 'target ; 'dest");
|
|
}
|
|
|
|
|
|
void ARMDecoder::DecodeType6(Instr* instr) {
|
|
if (instr->IsVFPDoubleTransfer()) {
|
|
if (instr->Bit(8) == 0) {
|
|
if (instr->Bit(20) == 1) {
|
|
Format(instr, "vmovrrs'cond 'rd, 'rn, {'sm, 'sm1}");
|
|
} else {
|
|
Format(instr, "vmovsrr'cond {'sm, 'sm1}, 'rd, 'rn");
|
|
}
|
|
} else {
|
|
if (instr->Bit(20) == 1) {
|
|
Format(instr, "vmovrrd'cond 'rd, 'rn, 'dm");
|
|
} else {
|
|
Format(instr, "vmovdrr'cond 'dm, 'rd, 'rn");
|
|
}
|
|
}
|
|
} else if (instr-> IsVFPLoadStore()) {
|
|
if (instr->Bit(8) == 0) {
|
|
if (instr->Bit(20) == 1) { // vldrs
|
|
if (instr->Bit(23) == 1) {
|
|
Format(instr, "vldrs'cond 'sd, ['rn, #+'off10]");
|
|
} else {
|
|
Format(instr, "vldrs'cond 'sd, ['rn, #-'off10]");
|
|
}
|
|
} else { // vstrs
|
|
if (instr->Bit(23) == 1) {
|
|
Format(instr, "vstrs'cond 'sd, ['rn, #+'off10]");
|
|
} else {
|
|
Format(instr, "vstrs'cond 'sd, ['rn, #-'off10]");
|
|
}
|
|
}
|
|
} else {
|
|
if (instr->Bit(20) == 1) { // vldrd
|
|
if (instr->Bit(23) == 1) {
|
|
Format(instr, "vldrd'cond 'dd, ['rn, #+'off10]");
|
|
} else {
|
|
Format(instr, "vldrd'cond 'dd, ['rn, #-'off10]");
|
|
}
|
|
} else { // vstrd
|
|
if (instr->Bit(23) == 1) {
|
|
Format(instr, "vstrd'cond 'dd, ['rn, #+'off10]");
|
|
} else {
|
|
Format(instr, "vstrd'cond 'dd, ['rn, #-'off10]");
|
|
}
|
|
}
|
|
}
|
|
} else if (instr->IsVFPMultipleLoadStore()) {
|
|
if (instr->HasL()) { // vldm
|
|
if (instr->Bit(8)) { // vldmd
|
|
Format(instr, "vldmd'cond'pu 'rn'w, 'dlist");
|
|
} else { // vldms
|
|
Format(instr, "vldms'cond'pu 'rn'w, 'slist");
|
|
}
|
|
} else { // vstm
|
|
if (instr->Bit(8)) { // vstmd
|
|
Format(instr, "vstmd'cond'pu 'rn'w, 'dlist");
|
|
} else { // vstms
|
|
Format(instr, "vstms'cond'pu 'rn'w, 'slist");
|
|
}
|
|
}
|
|
} else {
|
|
Unknown(instr);
|
|
}
|
|
}
|
|
|
|
|
|
void ARMDecoder::DecodeType7(Instr* instr) {
|
|
if (instr->Bit(24) == 1) {
|
|
Format(instr, "svc'cond #'svc");
|
|
if (instr->SvcField() == kStopMessageSvcCode) {
|
|
const char* message = *reinterpret_cast<const char**>(
|
|
reinterpret_cast<intptr_t>(instr) - Instr::kInstrSize);
|
|
buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
|
|
remaining_size_in_buffer(),
|
|
" ; \"%s\"",
|
|
message);
|
|
}
|
|
} else if (instr->IsVFPDataProcessingOrSingleTransfer()) {
|
|
if (instr->Bit(4) == 0) {
|
|
// VFP Data Processing
|
|
switch (instr->Bits(20, 4) & 0xb) {
|
|
case 0: { // vmla, vmls floating-point
|
|
if (instr->Bit(8) == 0) {
|
|
if (instr->Bit(6) == 0) {
|
|
Format(instr, "vmlas'cond 'sd, 'sn, 'sm");
|
|
} else {
|
|
Format(instr, "vmlss'cond 'sd, 'sn, 'sm");
|
|
}
|
|
} else {
|
|
if (instr->Bit(6) == 0) {
|
|
Format(instr, "vmlad'cond 'dd, 'dn, 'dm");
|
|
} else {
|
|
Format(instr, "vmlsd'cond 'dd, 'dn, 'dm");
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case 1: // vnmla, vnmls, vnmul
|
|
default: {
|
|
Unknown(instr);
|
|
break;
|
|
}
|
|
case 2: { // vmul
|
|
if (instr->Bit(8) == 0) {
|
|
Format(instr, "vmuls'cond 'sd, 'sn, 'sm");
|
|
} else {
|
|
Format(instr, "vmuld'cond 'dd, 'dn, 'dm");
|
|
}
|
|
break;
|
|
}
|
|
case 8: { // vdiv
|
|
if (instr->Bit(8) == 0) {
|
|
Format(instr, "vdivs'cond 'sd, 'sn, 'sm");
|
|
} else {
|
|
Format(instr, "vdivd'cond 'dd, 'dn, 'dm");
|
|
}
|
|
break;
|
|
}
|
|
case 3: { // vadd, vsub floating-point
|
|
if (instr->Bit(8) == 0) {
|
|
if (instr->Bit(6) == 0) {
|
|
Format(instr, "vadds'cond 'sd, 'sn, 'sm");
|
|
} else {
|
|
Format(instr, "vsubs'cond 'sd, 'sn, 'sm");
|
|
}
|
|
} else {
|
|
if (instr->Bit(6) == 0) {
|
|
Format(instr, "vaddd'cond 'dd, 'dn, 'dm");
|
|
} else {
|
|
Format(instr, "vsubd'cond 'dd, 'dn, 'dm");
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case 0xb: { // Other VFP data-processing instructions
|
|
if (instr->Bit(6) == 0) { // vmov immediate
|
|
if (instr->Bit(8) == 0) {
|
|
Format(instr, "vmovs'cond 'sd, #'immf");
|
|
} else {
|
|
Format(instr, "vmovd'cond 'dd, #'immd");
|
|
}
|
|
break;
|
|
}
|
|
switch (instr->Bits(16, 4)) {
|
|
case 0: { // vmov register, vabs
|
|
switch (instr->Bits(6, 2)) {
|
|
case 1: { // vmov register
|
|
if (instr->Bit(8) == 0) {
|
|
Format(instr, "vmovs'cond 'sd, 'sm");
|
|
} else {
|
|
Format(instr, "vmovd'cond 'dd, 'dm");
|
|
}
|
|
break;
|
|
}
|
|
case 3: { // vabs
|
|
if (instr->Bit(8) == 0) {
|
|
Format(instr, "vabss'cond 'sd, 'sm");
|
|
} else {
|
|
Format(instr, "vabsd'cond 'dd, 'dm");
|
|
}
|
|
break;
|
|
}
|
|
default: {
|
|
Unknown(instr);
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case 1: { // vneg, vsqrt
|
|
switch (instr->Bits(6, 2)) {
|
|
case 1: { // vneg
|
|
if (instr->Bit(8) == 0) {
|
|
Format(instr, "vnegs'cond 'sd, 'sm");
|
|
} else {
|
|
Format(instr, "vnegd'cond 'dd, 'dm");
|
|
}
|
|
break;
|
|
}
|
|
case 3: { // vsqrt
|
|
if (instr->Bit(8) == 0) {
|
|
Format(instr, "vsqrts'cond 'sd, 'sm");
|
|
} else {
|
|
Format(instr, "vsqrtd'cond 'dd, 'dm");
|
|
}
|
|
break;
|
|
}
|
|
default: {
|
|
Unknown(instr);
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case 4: // vcmp, vcmpe
|
|
case 5: { // vcmp #0.0, vcmpe #0.0
|
|
if (instr->Bit(7) == 1) { // vcmpe
|
|
Unknown(instr);
|
|
} else {
|
|
if (instr->Bit(8) == 0) { // vcmps
|
|
if (instr->Bit(16) == 0) {
|
|
Format(instr, "vcmps'cond 'sd, 'sm");
|
|
} else {
|
|
Format(instr, "vcmps'cond 'sd, #0.0");
|
|
}
|
|
} else { // vcmpd
|
|
if (instr->Bit(16) == 0) {
|
|
Format(instr, "vcmpd'cond 'dd, 'dm");
|
|
} else {
|
|
Format(instr, "vcmpd'cond 'dd, #0.0");
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case 7: { // vcvt between double-precision and single-precision
|
|
if (instr->Bit(8) == 0) {
|
|
Format(instr, "vcvtds'cond 'dd, 'sm");
|
|
} else {
|
|
Format(instr, "vcvtsd'cond 'sd, 'dm");
|
|
}
|
|
break;
|
|
}
|
|
case 8: { // vcvt, vcvtr between floating-point and integer
|
|
if (instr->Bit(8) == 0) {
|
|
if (instr->Bit(7) == 0) {
|
|
Format(instr, "vcvtsu'cond 'sd, 'sm");
|
|
} else {
|
|
Format(instr, "vcvtsi'cond 'sd, 'sm");
|
|
}
|
|
} else {
|
|
if (instr->Bit(7) == 0) {
|
|
Format(instr, "vcvtdu'cond 'dd, 'sm");
|
|
} else {
|
|
Format(instr, "vcvtdi'cond 'dd, 'sm");
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case 12:
|
|
case 13: { // vcvt, vcvtr between floating-point and integer
|
|
if (instr->Bit(7) == 0) {
|
|
// We only support round-to-zero mode
|
|
Unknown(instr);
|
|
break;
|
|
}
|
|
if (instr->Bit(8) == 0) {
|
|
if (instr->Bit(16) == 0) {
|
|
Format(instr, "vcvtus'cond 'sd, 'sm");
|
|
} else {
|
|
Format(instr, "vcvtis'cond 'sd, 'sm");
|
|
}
|
|
} else {
|
|
if (instr->Bit(16) == 0) {
|
|
Format(instr, "vcvtud'cond 'sd, 'dm");
|
|
} else {
|
|
Format(instr, "vcvtid'cond 'sd, 'dm");
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case 2: // vcvtb, vcvtt
|
|
case 3: // vcvtb, vcvtt
|
|
case 9: // undefined
|
|
case 10: // vcvt between floating-point and fixed-point
|
|
case 11: // vcvt between floating-point and fixed-point
|
|
case 14: // vcvt between floating-point and fixed-point
|
|
case 15: // vcvt between floating-point and fixed-point
|
|
default: {
|
|
Unknown(instr);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
} else {
|
|
// 8, 16, or 32-bit Transfer between ARM Core and VFP
|
|
if ((instr->Bits(21, 3) == 0) && (instr->Bit(8) == 0)) {
|
|
if (instr->Bit(20) == 0) {
|
|
Format(instr, "vmovs'cond 'sn, 'rd");
|
|
} else {
|
|
Format(instr, "vmovr'cond 'rd, 'sn");
|
|
}
|
|
} else if ((instr->Bits(20, 4) == 0xf) && (instr->Bit(8) == 0) &&
|
|
(instr->Bits(12, 4) == 0xf)) {
|
|
Format(instr, "vmstat'cond");
|
|
} else {
|
|
Unknown(instr);
|
|
}
|
|
}
|
|
} else if (instr->IsMrcIdIsar0()) {
|
|
Format(instr, "mrc'cond p15, 0, 'rd, c0, c2, 0");
|
|
} else {
|
|
Unknown(instr);
|
|
}
|
|
}
|
|
|
|
|
|
void ARMDecoder::InstructionDecode(uword pc) {
|
|
Instr* instr = Instr::At(pc);
|
|
|
|
if (instr->ConditionField() == kSpecialCondition) {
|
|
if (instr->InstructionBits() == static_cast<int32_t>(0xf57ff01f)) {
|
|
Format(instr, "clrex");
|
|
} else {
|
|
Unknown(instr);
|
|
}
|
|
} else {
|
|
switch (instr->TypeField()) {
|
|
case 0:
|
|
case 1: {
|
|
DecodeType01(instr);
|
|
break;
|
|
}
|
|
case 2: {
|
|
DecodeType2(instr);
|
|
break;
|
|
}
|
|
case 3: {
|
|
DecodeType3(instr);
|
|
break;
|
|
}
|
|
case 4: {
|
|
DecodeType4(instr);
|
|
break;
|
|
}
|
|
case 5: {
|
|
DecodeType5(instr);
|
|
break;
|
|
}
|
|
case 6: {
|
|
DecodeType6(instr);
|
|
break;
|
|
}
|
|
case 7: {
|
|
DecodeType7(instr);
|
|
break;
|
|
}
|
|
default: {
|
|
// The type field is 3-bits in the ARM encoding.
|
|
UNREACHABLE();
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void Disassembler::DecodeInstruction(char* hex_buffer, intptr_t hex_size,
|
|
char* human_buffer, intptr_t human_size,
|
|
int* out_instr_size, uword pc) {
|
|
ARMDecoder decoder(human_buffer, human_size);
|
|
decoder.InstructionDecode(pc);
|
|
int32_t instruction_bits = Instr::At(pc)->InstructionBits();
|
|
OS::SNPrint(hex_buffer, hex_size, "%08x", instruction_bits);
|
|
if (out_instr_size) {
|
|
*out_instr_size = Instr::kInstrSize;
|
|
}
|
|
}
|
|
|
|
|
|
void Disassembler::Disassemble(uword start,
|
|
uword end,
|
|
DisassemblyFormatter* formatter,
|
|
const Code::Comments& comments) {
|
|
ASSERT(formatter != NULL);
|
|
char hex_buffer[kHexadecimalBufferSize]; // Instruction in hexadecimal form.
|
|
char human_buffer[kUserReadableBufferSize]; // Human-readable instruction.
|
|
uword pc = start;
|
|
intptr_t comment_finger = 0;
|
|
while (pc < end) {
|
|
const intptr_t offset = pc - start;
|
|
while (comment_finger < comments.Length() &&
|
|
comments.PCOffsetAt(comment_finger) <= offset) {
|
|
formatter->Print(
|
|
" ;; %s\n",
|
|
String::Handle(comments.CommentAt(comment_finger)).ToCString());
|
|
comment_finger++;
|
|
}
|
|
int instruction_length;
|
|
DecodeInstruction(hex_buffer, sizeof(hex_buffer),
|
|
human_buffer, sizeof(human_buffer),
|
|
&instruction_length, pc);
|
|
|
|
formatter->ConsumeInstruction(hex_buffer,
|
|
sizeof(hex_buffer),
|
|
human_buffer,
|
|
sizeof(human_buffer),
|
|
pc);
|
|
pc += instruction_length;
|
|
}
|
|
}
|
|
|
|
} // namespace dart
|
|
|
|
#endif // defined TARGET_ARCH_ARM
|