zra@google.com
3c10f6b796
On MIPS, we have a lot of registers, and we don't use very many of them. This change removes the second temporary register TMP2, and instead dedicates a register to holding Object::null(), which is used frequently for comparisons, etc.. Also, uses branch delay slot when leaving a dart frame and returning. R=regis@google.com Review URL: https://codereview.chromium.org//14854010 git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22331 260f80e4-7a28-3924-810f-c04153c831b5
88 lines
3.2 KiB
C++
88 lines
3.2 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#include "vm/globals.h"
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#if defined(TARGET_ARCH_MIPS)
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#include "vm/cpu.h"
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#include "vm/debugger.h"
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#include "vm/instructions.h"
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#include "vm/stub_code.h"
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namespace dart {
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// TODO(hausner): Handle captured variables.
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RawInstance* ActivationFrame::GetLocalVarValue(intptr_t slot_index) {
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uword var_address = fp() + slot_index * kWordSize;
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return reinterpret_cast<RawInstance*>(
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*reinterpret_cast<uword*>(var_address));
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}
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RawInstance* ActivationFrame::GetInstanceCallReceiver(
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intptr_t num_actual_args) {
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ASSERT(num_actual_args > 0); // At minimum we have a receiver on the stack.
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// Stack pointer points to last argument that was pushed on the stack.
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uword receiver_addr = sp() + ((num_actual_args - 1) * kWordSize);
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return reinterpret_cast<RawInstance*>(
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*reinterpret_cast<uword*>(receiver_addr));
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}
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void CodeBreakpoint::PatchFunctionReturn() {
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Instr* instr1 = Instr::At(pc_ - 5 * Instr::kInstrSize);
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Instr* instr2 = Instr::At(pc_ - 4 * Instr::kInstrSize);
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Instr* instr3 = Instr::At(pc_ - 3 * Instr::kInstrSize);
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Instr* instr4 = Instr::At(pc_ - 2 * Instr::kInstrSize);
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Instr* instr5 = Instr::At(pc_ - 1 * Instr::kInstrSize);
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#if defined(DEBUG)
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instr1->AssertIsImmInstr(LW, SP, RA, 2 * kWordSize);
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instr2->AssertIsImmInstr(LW, SP, FP, 1 * kWordSize);
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instr3->AssertIsImmInstr(LW, SP, PP, 0 * kWordSize);
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instr4->AssertIsSpecialInstr(JR, RA, ZR, ZR);
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instr5->AssertIsImmInstr(ADDIU, SP, SP, 4 * kWordSize);
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#endif // defined(DEBUG)
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// Smash code with call instruction and target address.
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uword stub_addr = StubCode::BreakpointReturnEntryPoint();
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uint16_t target_lo = stub_addr & 0xffff;
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uint16_t target_hi = stub_addr >> 16;
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// Unlike other architectures, the sequence we are patching in is shorter
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// than the sequence we are replacing. We pad at the top with nops so that
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// the end of the new sequence is lined up with the code descriptor.
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instr1->SetInstructionBits(Instr::kNopInstruction);
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instr2->SetImmInstrBits(LUI, ZR, TMP1, target_hi);
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instr3->SetImmInstrBits(ORI, TMP1, TMP1, target_lo);
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instr4->SetSpecialInstrBits(JALR, TMP1, ZR, RA);
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instr5->SetInstructionBits(Instr::kNopInstruction);
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CPU::FlushICache(pc_ - 5 * Instr::kInstrSize, 5 * Instr::kInstrSize);
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}
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void CodeBreakpoint::RestoreFunctionReturn() {
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Instr* instr1 = Instr::At(pc_ - 5 * Instr::kInstrSize);
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Instr* instr2 = Instr::At(pc_ - 4 * Instr::kInstrSize);
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Instr* instr3 = Instr::At(pc_ - 3 * Instr::kInstrSize);
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Instr* instr4 = Instr::At(pc_ - 2 * Instr::kInstrSize);
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Instr* instr5 = Instr::At(pc_ - 1 * Instr::kInstrSize);
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ASSERT(instr2->OpcodeField() == LUI && instr2->RtField() == TMP1);
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instr1->SetImmInstrBits(LW, SP, RA, 2 * kWordSize);
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instr2->SetImmInstrBits(LW, SP, FP, 1 * kWordSize);
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instr3->SetImmInstrBits(LW, SP, PP, 0 * kWordSize);
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instr4->SetSpecialInstrBits(JR, RA, ZR, ZR);
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instr5->SetImmInstrBits(ADDIU, SP, SP, 4 * kWordSize);
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CPU::FlushICache(pc_ - 5 * Instr::kInstrSize, 5 * Instr::kInstrSize);
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}
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} // namespace dart
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#endif // defined TARGET_ARCH_MIPS
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