Martin Kustermann 5c7e561a81 [gardening] Fix StoreReleaseLoadAcquire tests in tsan ...

In tsan mode, the load-acquire/store-release assembler implementation
will make a runtime call to let TSAN know about the operation.

In order to perform the runtime call the THR register needs to be
populated, which it wasn't.

TEST=Fixes crashing vm/cc/StoreReleaseLoadAcquire tests in tsan mode

Change-Id: I1f45fee9c8e40b8069bf32b13caa97a02f13a6a1
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/256261
Commit-Queue: Martin Kustermann <kustermann@google.com>
Reviewed-by: Daco Harkes <dacoharkes@google.com>

2022-08-26 10:02:51 +00:00

..

assembler_arm64_test.cc

[vm, compiler] Make more use of the zero register on ARM64 and RV.

2022-05-24 22:12:17 +00:00

assembler_arm64.cc

[vm] Appease UBSAN for ARM64 and RV64.

2022-08-25 17:15:33 +00:00

assembler_arm64.h

Revert "[vm, compiler] Implement unboxed SIMD for RISC-V via lowering."

2022-08-03 10:32:46 +00:00

assembler_arm_test.cc

[vm/sim/simd] Fix vmin/vmax implementation on simulator.

2022-05-11 16:59:24 +00:00

assembler_arm.cc

[vm] New async/async* implementation in JIT mode

2022-06-02 23:39:45 +00:00

assembler_arm.h

Fix typos

2022-06-15 11:08:28 +00:00

assembler_base.cc

[vm, compiler] Load unboxed doubles directly from the literal pool.

2022-05-10 21:31:40 +00:00

assembler_base.h

[vm] Appease UBSAN for ARM64 and RV64.

2022-08-25 17:15:33 +00:00

assembler_ia32_test.cc

[vm, compiler] Emit constant-width addresses in IA32 disassembly for the absolute addressing mode.

2022-06-16 16:03:19 +00:00

assembler_ia32.cc

Revert "[vm, compiler] Implement unboxed SIMD for RISC-V via lowering."

2022-08-03 10:32:46 +00:00

assembler_ia32.h

Revert "[vm, compiler] Implement unboxed SIMD for RISC-V via lowering."

2022-08-03 10:32:46 +00:00

assembler_riscv_test.cc

[vm, compiler] Use RISC-V's compare-and-branch for a shorter write barrier sequence.

2022-06-23 15:58:15 +00:00

assembler_riscv.cc

[vm] Appease UBSAN for ARM64 and RV64.

2022-08-25 17:15:33 +00:00

assembler_riscv.h

Revert "[vm, compiler] Implement unboxed SIMD for RISC-V via lowering."

2022-08-03 10:32:46 +00:00

assembler_test.cc

[vm] Fix vm/cc/AllocationSinking_Arrays and StoreIntoObject with compressed pointers.

2021-07-12 21:10:37 +00:00

assembler_x64_test.cc

[gardening] Fix StoreReleaseLoadAcquire tests in tsan

2022-08-26 10:02:51 +00:00

assembler_x64.cc

Revert "[vm, compiler] Implement unboxed SIMD for RISC-V via lowering."

2022-08-03 10:32:46 +00:00

assembler_x64.h

Revert "[vm, compiler] Implement unboxed SIMD for RISC-V via lowering."

2022-08-03 10:32:46 +00:00

assembler.h

[vm] Support RISC-V.

2022-01-20 00:57:57 +00:00

disassembler_arm64.cc

[vm, compiler] Make more use of the zero register on ARM64 and RV.

2022-05-24 22:12:17 +00:00

disassembler_arm.cc

Reland "[build] Fix Android build for ARM64 Mac."

2022-05-10 16:11:53 +00:00

disassembler_riscv.cc

[vm] Appease UBSAN for ARM64 and RV64.

2022-08-25 17:15:33 +00:00

disassembler_test.cc

[vm] DBC is obsolete. Remove dead code.

2019-10-27 18:18:29 +00:00

disassembler_x86.cc

[vm, compiler] Emit constant-width addresses in IA32 disassembly for the absolute addressing mode.

2022-06-16 16:03:19 +00:00

disassembler.cc

[vm, compiler] Include the global object pool in AOT's --disassemble.

2022-05-12 17:38:35 +00:00

disassembler.h

[vm] Small fixes

2022-07-04 07:53:39 +00:00

object_pool_builder.h

[vm, compiler] Load unboxed doubles directly from the literal pool.

2022-05-10 21:31:40 +00:00