zra@google.com
7c91e88e6e
When we detect ARMv6, instead of using movw and movt, this change loads each individual byte. Although this is not the best way to achieve this, a modification to store large constants in the object pool would be more invasive. Further, this change will be easier to back-out once ARMv6 is obsolete. R=regis@google.com Review URL: https://codereview.chromium.org//183803024 git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@33442 260f80e4-7a28-3924-810f-c04153c831b5
343 lines
13 KiB
C++
343 lines
13 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
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#if defined(TARGET_ARCH_ARM)
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#include "vm/assembler.h"
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#include "vm/constants_arm.h"
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#include "vm/cpu.h"
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#include "vm/instructions.h"
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#include "vm/object.h"
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namespace dart {
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CallPattern::CallPattern(uword pc, const Code& code)
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: object_pool_(Array::Handle(code.ObjectPool())),
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end_(pc),
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args_desc_load_end_(0),
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ic_data_load_end_(0),
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target_address_pool_index_(-1),
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args_desc_(Array::Handle()),
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ic_data_(ICData::Handle()) {
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ASSERT(code.ContainsInstructionAt(pc));
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// Last instruction: blx lr.
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ASSERT(*(reinterpret_cast<uword*>(end_) - 1) == 0xe12fff3e);
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Register reg;
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ic_data_load_end_ =
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InstructionPattern::DecodeLoadWordFromPool(end_ - Instr::kInstrSize,
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®,
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&target_address_pool_index_);
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ASSERT(reg == LR);
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}
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int CallPattern::LengthInBytes() {
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if (TargetCPUFeatures::arm_version() == ARMv6) {
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return 5 * Instr::kInstrSize;
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} else {
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ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
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return 3 * Instr::kInstrSize;
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}
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the loaded object in the output parameters 'reg' and 'obj'
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// respectively.
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uword InstructionPattern::DecodeLoadObject(uword end,
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const Array& object_pool,
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Register* reg,
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Object* obj) {
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uword start = 0;
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Instr* instr = Instr::At(end - Instr::kInstrSize);
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if ((instr->InstructionBits() & 0xfff00000) == 0xe5900000) {
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// ldr reg, [reg, #+offset]
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intptr_t index = 0;
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start = DecodeLoadWordFromPool(end, reg, &index);
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*obj = object_pool.At(index);
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} else {
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intptr_t value = 0;
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start = DecodeLoadWordImmediate(end, reg, &value);
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*obj = reinterpret_cast<RawObject*>(value);
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}
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return start;
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the loaded immediate value in the output parameters 'reg' and 'value'
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// respectively.
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uword InstructionPattern::DecodeLoadWordImmediate(uword end,
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Register* reg,
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intptr_t* value) {
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uword start = end - Instr::kInstrSize;
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int32_t instr = Instr::At(start)->InstructionBits();
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intptr_t imm = 0;
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if (TargetCPUFeatures::arm_version() == ARMv6) {
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ASSERT((instr & 0xfff00000) == 0xe3800000); // orr rd, rd, byte0
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imm |= (instr & 0x000000ff);
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start -= Instr::kInstrSize;
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instr = Instr::At(start)->InstructionBits();
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ASSERT((instr & 0xfff00000) == 0xe3800c00); // orr rd, rd, (byte1 rot 12)
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imm |= (instr & 0x000000ff);
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start -= Instr::kInstrSize;
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instr = Instr::At(start)->InstructionBits();
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ASSERT((instr & 0xfff00f00) == 0xe3800800); // orr rd, rd, (byte2 rot 8)
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imm |= (instr & 0x000000ff);
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start -= Instr::kInstrSize;
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instr = Instr::At(start)->InstructionBits();
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ASSERT((instr & 0xffff0f00) == 0xe3a00400); // mov rd, (byte3 rot 4)
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imm |= (instr & 0x000000ff);
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*reg = static_cast<Register>((instr & 0x0000f000) >> 12);
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*value = imm;
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} else {
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ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
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if ((instr & 0xfff00000) == 0xe3400000) { // movt reg, #imm_hi
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imm |= (instr & 0xf0000) << 12;
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imm |= (instr & 0xfff) << 16;
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start -= Instr::kInstrSize;
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instr = Instr::At(start)->InstructionBits();
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}
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ASSERT((instr & 0xfff00000) == 0xe3000000); // movw reg, #imm_lo
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imm |= (instr & 0xf0000) >> 4;
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imm |= instr & 0xfff;
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*reg = static_cast<Register>((instr & 0xf000) >> 12);
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*value = imm;
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}
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return start;
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}
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// Decodes a load sequence ending at 'end' (the last instruction of the load
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// sequence is the instruction before the one at end). Returns a pointer to
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// the first instruction in the sequence. Returns the register being loaded
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// and the index in the pool being read from in the output parameters 'reg'
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// and 'index' respectively.
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uword InstructionPattern::DecodeLoadWordFromPool(uword end,
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Register* reg,
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intptr_t* index) {
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uword start = end - Instr::kInstrSize;
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int32_t instr = Instr::At(start)->InstructionBits();
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intptr_t offset = 0;
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if ((instr & 0xffff0000) == 0xe59a0000) { // ldr reg, [pp, #+offset]
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offset = instr & 0xfff;
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*reg = static_cast<Register>((instr & 0xf000) >> 12);
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} else {
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ASSERT((instr & 0xfff00000) == 0xe5900000); // ldr reg, [reg, #+offset]
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offset = instr & 0xfff;
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start -= Instr::kInstrSize;
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instr = Instr::At(start)->InstructionBits();
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if ((instr & 0xffff0000) == 0xe28a0000) { // add reg, pp, shifter_op
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const intptr_t rot = (instr & 0xf00) >> 7;
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const intptr_t imm8 = instr & 0xff;
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offset += (imm8 >> rot) | (imm8 << (32 - rot));
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*reg = static_cast<Register>((instr & 0xf000) >> 12);
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} else {
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ASSERT((instr & 0xffff0000) == 0xe08a0000); // add reg, pp, reg
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end = DecodeLoadWordImmediate(end, reg, &offset);
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}
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}
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offset += kHeapObjectTag;
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ASSERT(Utils::IsAligned(offset, 4));
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*index = (offset - Array::data_offset()) / 4;
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return start;
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}
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RawICData* CallPattern::IcData() {
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if (ic_data_.IsNull()) {
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Register reg;
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args_desc_load_end_ =
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InstructionPattern::DecodeLoadObject(ic_data_load_end_,
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object_pool_,
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®,
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&ic_data_);
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ASSERT(reg == R5);
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}
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return ic_data_.raw();
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}
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RawArray* CallPattern::ClosureArgumentsDescriptor() {
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if (args_desc_.IsNull()) {
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IcData(); // Loading of the ic_data must be decoded first, if not already.
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Register reg;
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InstructionPattern::DecodeLoadObject(args_desc_load_end_,
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object_pool_,
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®,
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&args_desc_);
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ASSERT(reg == R4);
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}
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return args_desc_.raw();
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}
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uword CallPattern::TargetAddress() const {
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ASSERT(target_address_pool_index_ >= 0);
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const Object& target_address =
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Object::Handle(object_pool_.At(target_address_pool_index_));
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ASSERT(target_address.IsSmi());
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// The address is stored in the object array as a RawSmi.
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return reinterpret_cast<uword>(target_address.raw());
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}
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void CallPattern::SetTargetAddress(uword target_address) const {
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ASSERT(Utils::IsAligned(target_address, 4));
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// The address is stored in the object array as a RawSmi.
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const Smi& smi = Smi::Handle(reinterpret_cast<RawSmi*>(target_address));
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object_pool_.SetAt(target_address_pool_index_, smi);
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// No need to flush the instruction cache, since the code is not modified.
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}
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void CallPattern::InsertAt(uword pc, uword target_address) {
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if (TargetCPUFeatures::arm_version() == ARMv6) {
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const uint32_t byte0 = (target_address & 0x000000ff);
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const uint32_t byte1 = (target_address & 0x0000ff00) >> 8;
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const uint32_t byte2 = (target_address & 0x00ff0000) >> 16;
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const uint32_t byte3 = (target_address & 0xff000000) >> 24;
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const uword mov_ip = 0xe3a0c400 | byte3; // mov ip, (byte3 rot 4)
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const uword or1_ip = 0xe38cc800 | byte2; // orr ip, ip, (byte2 rot 8)
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const uword or2_ip = 0xe38ccc00 | byte1; // orr ip, ip, (byte1 rot 12)
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const uword or3_ip = 0xe38cc000 | byte0; // orr ip, ip, byte0
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const uword blx_ip = 0xe12fff3c;
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*reinterpret_cast<uword*>(pc + (0 * Instr::kInstrSize)) = mov_ip;
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*reinterpret_cast<uword*>(pc + (1 * Instr::kInstrSize)) = or1_ip;
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*reinterpret_cast<uword*>(pc + (2 * Instr::kInstrSize)) = or2_ip;
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*reinterpret_cast<uword*>(pc + (3 * Instr::kInstrSize)) = or3_ip;
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*reinterpret_cast<uword*>(pc + (4 * Instr::kInstrSize)) = blx_ip;
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ASSERT(LengthInBytes() == 5 * Instr::kInstrSize);
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CPU::FlushICache(pc, LengthInBytes());
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} else {
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ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
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const uint16_t target_lo = target_address & 0xffff;
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const uint16_t target_hi = target_address >> 16;
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const uword movw_ip =
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0xe300c000 | ((target_lo >> 12) << 16) | (target_lo & 0xfff);
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const uword movt_ip =
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0xe340c000 | ((target_hi >> 12) << 16) | (target_hi & 0xfff);
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const uword blx_ip = 0xe12fff3c;
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*reinterpret_cast<uword*>(pc + (0 * Instr::kInstrSize)) = movw_ip;
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*reinterpret_cast<uword*>(pc + (1 * Instr::kInstrSize)) = movt_ip;
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*reinterpret_cast<uword*>(pc + (2 * Instr::kInstrSize)) = blx_ip;
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ASSERT(LengthInBytes() == 3 * Instr::kInstrSize);
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CPU::FlushICache(pc, LengthInBytes());
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}
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}
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JumpPattern::JumpPattern(uword pc, const Code& code) : pc_(pc) { }
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int JumpPattern::pattern_length_in_bytes() {
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if (TargetCPUFeatures::arm_version() == ARMv6) {
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return 5 * Instr::kInstrSize;
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} else {
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ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
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return 3 * Instr::kInstrSize;
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}
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}
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bool JumpPattern::IsValid() const {
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if (TargetCPUFeatures::arm_version() == ARMv6) {
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Instr* mov_ip = Instr::At(pc_ + (0 * Instr::kInstrSize));
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Instr* or1_ip = Instr::At(pc_ + (1 * Instr::kInstrSize));
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Instr* or2_ip = Instr::At(pc_ + (2 * Instr::kInstrSize));
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Instr* or3_ip = Instr::At(pc_ + (3 * Instr::kInstrSize));
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Instr* bx_ip = Instr::At(pc_ + (4 * Instr::kInstrSize));
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return ((mov_ip->InstructionBits() & 0xffffff00) == 0xe3a0c400) &&
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((or1_ip->InstructionBits() & 0xffffff00) == 0xe38cc800) &&
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((or2_ip->InstructionBits() & 0xffffff00) == 0xe38ccc00) &&
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((or3_ip->InstructionBits() & 0xffffff00) == 0xe38cc000) &&
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((bx_ip->InstructionBits() & 0xffffffff) == 0xe12fff1c);
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} else {
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ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
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Instr* movw_ip = Instr::At(pc_ + (0 * Instr::kInstrSize)); // target_lo
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Instr* movt_ip = Instr::At(pc_ + (1 * Instr::kInstrSize)); // target_hi
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Instr* bx_ip = Instr::At(pc_ + (2 * Instr::kInstrSize));
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return (movw_ip->InstructionBits() & 0xfff0f000) == 0xe300c000 &&
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(movt_ip->InstructionBits() & 0xfff0f000) == 0xe340c000 &&
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(bx_ip->InstructionBits() & 0xffffffff) == 0xe12fff1c;
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}
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}
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uword JumpPattern::TargetAddress() const {
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if (TargetCPUFeatures::arm_version() == ARMv6) {
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Instr* mov_ip = Instr::At(pc_ + (0 * Instr::kInstrSize));
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Instr* or1_ip = Instr::At(pc_ + (1 * Instr::kInstrSize));
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Instr* or2_ip = Instr::At(pc_ + (2 * Instr::kInstrSize));
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Instr* or3_ip = Instr::At(pc_ + (3 * Instr::kInstrSize));
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uword imm = 0;
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imm |= or3_ip->Immed8Field();
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imm |= or2_ip->Immed8Field() << 8;
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imm |= or1_ip->Immed8Field() << 16;
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imm |= mov_ip->Immed8Field() << 24;
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return imm;
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} else {
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ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
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Instr* movw_ip = Instr::At(pc_ + (0 * Instr::kInstrSize)); // target_lo
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Instr* movt_ip = Instr::At(pc_ + (1 * Instr::kInstrSize)); // target_hi
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uint16_t target_lo = movw_ip->MovwField();
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uint16_t target_hi = movt_ip->MovwField();
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return (target_hi << 16) | target_lo;
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}
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}
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void JumpPattern::SetTargetAddress(uword target_address) const {
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if (TargetCPUFeatures::arm_version() == ARMv6) {
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const uint32_t byte0 = (target_address & 0x000000ff);
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const uint32_t byte1 = (target_address & 0x0000ff00) >> 8;
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const uint32_t byte2 = (target_address & 0x00ff0000) >> 16;
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const uint32_t byte3 = (target_address & 0xff000000) >> 24;
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const uword mov_ip = 0xe3a0c400 | byte3; // mov ip, (byte3 rot 4)
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const uword or1_ip = 0xe38cc800 | byte2; // orr ip, ip, (byte2 rot 8)
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const uword or2_ip = 0xe38ccc00 | byte1; // orr ip, ip, (byte1 rot 12)
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const uword or3_ip = 0xe38cc000 | byte0; // orr ip, ip, byte0
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*reinterpret_cast<uword*>(pc_ + (0 * Instr::kInstrSize)) = mov_ip;
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*reinterpret_cast<uword*>(pc_ + (1 * Instr::kInstrSize)) = or1_ip;
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*reinterpret_cast<uword*>(pc_ + (2 * Instr::kInstrSize)) = or2_ip;
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*reinterpret_cast<uword*>(pc_ + (3 * Instr::kInstrSize)) = or3_ip;
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CPU::FlushICache(pc_, 4 * Instr::kInstrSize);
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} else {
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ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
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const uint16_t target_lo = target_address & 0xffff;
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const uint16_t target_hi = target_address >> 16;
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const uword movw_ip =
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0xe300c000 | ((target_lo >> 12) << 16) | (target_lo & 0xfff);
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const uword movt_ip =
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0xe340c000 | ((target_hi >> 12) << 16) | (target_hi & 0xfff);
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*reinterpret_cast<uword*>(pc_ + (0 * Instr::kInstrSize)) = movw_ip;
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*reinterpret_cast<uword*>(pc_ + (1 * Instr::kInstrSize)) = movt_ip;
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CPU::FlushICache(pc_, 2 * Instr::kInstrSize);
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}
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}
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} // namespace dart
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#endif // defined TARGET_ARCH_ARM
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