Tess Strickland 2b1e82b4fe [gardening] Satisfy UBSAN for possibly negative left shifts. ...

TEST=vm/cc/Assembler_LslImmediate on ubsan trybots

Fixes: https://github.com/dart-lang/sdk/issues/56860
Cq-Include-Trybots: luci.dart.try:vm-ubsan-linux-release-x64-try,vm-ubsan-linux-release-arm64-try,vm-aot-ubsan-linux-release-x64-try
Change-Id: Iad1332d638af633373bbb588ea554e6a0da71c93
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/388840
Reviewed-by: Daco Harkes <dacoharkes@google.com>
Commit-Queue: Tess Strickland <sstrickl@google.com>

2024-10-08 09:47:59 +00:00

..

assembler_arm64_test.cc

[gardening] Satisfy UBSAN for possibly negative left shifts.

2024-10-08 09:47:59 +00:00

assembler_arm64.cc

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler_arm64.h

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler_arm_test.cc

[gardening] Satisfy UBSAN for possibly negative left shifts.

2024-10-08 09:47:59 +00:00

assembler_arm.cc

[vm/compiler] Add requested change to ARM7 ArithmeticShiftRightImmediate.

2024-10-04 11:10:45 +00:00

assembler_arm.h

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler_base.cc

[vm, compiler] Make use of the zero register for unboxed stores too.

2024-09-23 21:51:31 +00:00

assembler_base.h

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler_ia32_test.cc

[gardening] Satisfy UBSAN for possibly negative left shifts.

2024-10-08 09:47:59 +00:00

assembler_ia32.cc

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler_ia32.h

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler_riscv_test.cc

[gardening] Satisfy UBSAN for possibly negative left shifts.

2024-10-08 09:47:59 +00:00

assembler_riscv.cc

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler_riscv.h

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler_test.cc

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler_test.h

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler_x64_test.cc

[gardening] Satisfy UBSAN for possibly negative left shifts.

2024-10-08 09:47:59 +00:00

assembler_x64.cc

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler_x64.h

[vm/compiler] Add reg, reg, imm forms for lsl/asr/and assembler macros.

2024-10-04 10:07:51 +00:00

assembler.h

[vm] Support RISC-V.

2022-01-20 00:57:57 +00:00

disassembler_arm64.cc

[vm, compiler] Fix Undefined Behavior accessing the wrong bit in ARM64 disassembler.

2024-07-16 18:21:02 +00:00

disassembler_arm.cc

[vm] Run clang-format on code base

2024-04-17 19:14:41 +00:00

disassembler_kbc.cc

[dart2bytecode, vm/interpreter] Small fixes

2024-08-29 14:28:40 +00:00

disassembler_kbc.h

[vm] Initial implementation of dynamic modules in the VM/AOT

2024-08-15 14:09:52 +00:00

disassembler_riscv.cc

[vm] Add support for the Zalasr extension.

2024-05-14 16:40:59 +00:00

disassembler_test.cc

[vm] Fix asan errors in Disassembler_InvalidInput

2023-05-17 22:36:03 +00:00

disassembler_x86.cc

Roll Clang to 3928edecfbd116d56bbe7411365d50bb567380a1.

2024-09-23 23:36:48 +00:00

disassembler.cc

[vm] Short-circuit disassembly instead of disassembling into the no-op log.

2024-04-10 23:09:37 +00:00

disassembler.h

[vm] Update to constexpr in runtime/vm/compiler.

2023-04-11 21:50:56 +00:00

object_pool_builder.h

[vm] Introduce cachable idempotent calls

2023-10-27 07:55:47 +00:00