Files
sdk/runtime/platform/atomic.h
T
Siva Annamalai 94c8d341d7 Revert "[vm, gc] Mark through new-space."
This reverts commit a3b7c323b0.

Reason for revert: We are seeing crashes in some internal testing
si_signo=Segmentation fault(11), si_code=SEGV_ACCERR(2), si_addr=0x7f1cadb85bc6
version=3.3.0-edge+google3-v2 (google3) (google3) on "linux_x64"
pid=8967, thread=8969, isolate_group=main(0x5583571aaaf0), isolate=(nil)((nil))
os=linux, arch=x64, comp=no, sim=no
isolate_instructions=7f1cad8b7e40, vm_instructions=7f1cad8b1000
fp=7f1cacc7ebc0, sp=7f1cacc7eb90, pc=5583568155bc
  pc 0x00005583568155bc fp 0x00007f1cacc7ebc0 dart::MarkingVisitorBase<true>::VisitPointers(dart::ObjectPtr*, dart::ObjectPtr*)+0x15c
  pc 0x0000558356975a1d fp 0x00007f1cacc7ec60 dart::StackFrame::VisitObjectPointers(dart::ObjectPointerVisitor*)+0x1bd
  pc 0x0000558356935c29 fp 0x00007f1cacc7ecc0 dart::UntaggedSuspendState::VisitSuspendStatePointers(dart::SuspendStatePtr, dart::ObjectPointerVisitor*)+0x89
  pc 0x0000558356815948 fp 0x00007f1cacc7ed10 dart::MarkingVisitorBase<true>::DrainMarkingStackWithPauseChecks()+0x128
  pc 0x0000558356815749 fp 0x00007f1cacc7ed80 dart::ConcurrentMarkTask::Run()+0x69

Original change's description:
> [vm, gc] Mark through new-space.
>
>  - Initial and final marking no longer visit all of new-space, reducing the STW pause for major GC.
>  - A scavenge during concurrent marking must forward / filter objects in the marking worklist that are moved / collected, increasing the STW pause for minor GC.
>  - Unreachable intergenerational cycles and weak references are collected in the next mark-sweep instead of first requiring enough scavenges to promote the whole cycle or weak target into old-space.
>  - Artificial minor GCs are no longer needed to avoid memory leaks from back-to-back major GCs.
>  - reachabilityBarrier is now just a count of major GCs.
>
> TEST=ci
> Change-Id: Ic7754e8d972763654eae2b7faa8670735d9cda3f
> Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/340644
> Reviewed-by: Siva Annamalai <asiva@google.com>
> Commit-Queue: Ryan Macnak <rmacnak@google.com>

Change-Id: Ice07b4eb5bef3b41c9618ef0ca7759de006ffe00
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/343060
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Commit-Queue: Siva Annamalai <asiva@google.com>
Reviewed-by: Alexander Aprelev <aam@google.com>
2023-12-21 21:02:38 +00:00

152 lines
4.9 KiB
C++

// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
// for details. All rights reserved. Use of this source code is governed by a
// BSD-style license that can be found in the LICENSE file.
#ifndef RUNTIME_PLATFORM_ATOMIC_H_
#define RUNTIME_PLATFORM_ATOMIC_H_
#include <atomic>
namespace dart {
// Like std::atomic, but operations default to relaxed ordering instead of
// sequential consistency.
template <typename T>
class RelaxedAtomic {
public:
constexpr RelaxedAtomic() : value_() {}
constexpr RelaxedAtomic(T arg) : value_(arg) {} // NOLINT
RelaxedAtomic(const RelaxedAtomic& arg) : value_(arg) {} // NOLINT
T load(std::memory_order order = std::memory_order_relaxed) const {
return value_.load(order);
}
T load(std::memory_order order = std::memory_order_relaxed) const volatile {
return value_.load(order);
}
void store(T arg, std::memory_order order = std::memory_order_relaxed) {
value_.store(arg, order);
}
void store(T arg,
std::memory_order order = std::memory_order_relaxed) volatile {
value_.store(arg, order);
}
T fetch_add(T arg, std::memory_order order = std::memory_order_relaxed) {
return value_.fetch_add(arg, order);
}
T fetch_sub(T arg, std::memory_order order = std::memory_order_relaxed) {
return value_.fetch_sub(arg, order);
}
T fetch_or(T arg, std::memory_order order = std::memory_order_relaxed) {
return value_.fetch_or(arg, order);
}
T fetch_and(T arg, std::memory_order order = std::memory_order_relaxed) {
return value_.fetch_and(arg, order);
}
T exchange(T arg, std::memory_order order = std::memory_order_relaxed) {
return value_.exchange(arg, order);
}
bool compare_exchange_weak(
T& expected, // NOLINT
T desired,
std::memory_order order = std::memory_order_relaxed) {
return value_.compare_exchange_weak(expected, desired, order, order);
}
bool compare_exchange_weak(
T& expected, // NOLINT
T desired,
std::memory_order order = std::memory_order_relaxed) volatile {
return value_.compare_exchange_weak(expected, desired, order, order);
}
bool compare_exchange_strong(
T& expected, // NOLINT
T desired,
std::memory_order order = std::memory_order_relaxed) {
return value_.compare_exchange_strong(expected, desired, order, order);
}
operator T() const { return load(); }
T operator=(T arg) {
store(arg);
return arg;
}
T operator=(const RelaxedAtomic& arg) {
T loaded_once = arg;
store(loaded_once);
return loaded_once;
}
T operator+=(T arg) { return fetch_add(arg) + arg; }
T operator-=(T arg) { return fetch_sub(arg) - arg; }
T& operator++() { return fetch_add(1) + 1; }
T& operator--() { return fetch_sub(1) - 1; }
T operator++(int) { return fetch_add(1); }
T operator--(int) { return fetch_sub(1); }
private:
std::atomic<T> value_;
};
// Like std::atomic, but operations default to acquire for load, release for
// stores, and acquire-release for read-and-updates.
template <typename T>
class AcqRelAtomic {
public:
constexpr AcqRelAtomic() : value_() {}
constexpr AcqRelAtomic(T arg) : value_(arg) {} // NOLINT
AcqRelAtomic(const AcqRelAtomic& arg) = delete;
T load(std::memory_order order = std::memory_order_acquire) const {
return value_.load(order);
}
void store(T arg, std::memory_order order = std::memory_order_release) {
value_.store(arg, order);
}
T fetch_add(T arg, std::memory_order order = std::memory_order_acq_rel) {
return value_.fetch_add(arg, order);
}
T fetch_sub(T arg, std::memory_order order = std::memory_order_acq_rel) {
return value_.fetch_sub(arg, order);
}
T fetch_or(T arg, std::memory_order order = std::memory_order_acq_rel) {
return value_.fetch_or(arg, order);
}
T fetch_and(T arg, std::memory_order order = std::memory_order_acq_rel) {
return value_.fetch_and(arg, order);
}
bool compare_exchange_weak(
T& expected, // NOLINT
T desired,
std::memory_order success_order = std::memory_order_acq_rel,
std::memory_order failure_order = std::memory_order_seq_cst) {
return value_.compare_exchange_weak(expected, desired, success_order,
failure_order);
}
bool compare_exchange_strong(
T& expected, // NOLINT
T desired,
std::memory_order success_order = std::memory_order_acq_rel,
std::memory_order failure_order = std::memory_order_seq_cst) {
return value_.compare_exchange_strong(expected, desired, success_order,
failure_order);
}
// Require explicit loads and stores.
operator T() const = delete;
T operator=(T arg) = delete;
T operator=(const AcqRelAtomic& arg) = delete;
T operator+=(T arg) = delete;
T operator-=(T arg) = delete;
private:
std::atomic<T> value_;
};
} // namespace dart
#endif // RUNTIME_PLATFORM_ATOMIC_H_