Vyacheslav Egorov
8085a97a63
Instead of handling FFI related execution state and safepoint in assembly handle it in runtime code. The transition needs to be done before JumpToFrame unwinds stack because unwinding destroys exit frame and this can't be done at safepoint as GC might be traversing the stack. An incorrect order of operation was manifesting as crashes in GC when one isolate in a group was encountering a lot of exceptions thrown from an FFI call and another isolate is triggering GCs. To catch this in the future added a bit of validation to ExitSafepoint runtime call which triggers when --use-slow-path is enabled. Though after refactoring this code does not trigger this code path anymore because it was completely removed - but it is better than nothing. This CL also removes a lot of unnecessary complexity which was associated with handling this transition in the stub itself. TEST=ffi/vmspecific_handle_test Bug: b/408377905 Cq-Include-Trybots: dart/try:vm-aot-android-release-arm64c-try,vm-aot-android-release-arm_x64-try,vm-aot-asan-linux-release-x64-try,vm-aot-linux-debug-x64-try,vm-aot-linux-debug-x64c-try,vm-aot-mac-release-arm64-try,vm-aot-msan-linux-release-x64-try,vm-aot-obfuscate-linux-release-x64-try,vm-aot-optimization-level-linux-release-x64-try,vm-aot-tsan-linux-release-x64-try,vm-aot-ubsan-linux-release-x64-try,vm-aot-win-debug-x64-try,vm-aot-win-debug-x64c-try,vm-appjit-linux-debug-x64-try,vm-asan-linux-release-arm64-try,vm-asan-linux-release-x64-try,vm-checked-mac-release-arm64-try,vm-eager-optimization-linux-release-ia32-try,vm-eager-optimization-linux-release-x64-try,vm-ffi-android-debug-arm-try,vm-ffi-android-debug-arm64c-try,vm-ffi-mac-debug-simarm64_arm64-try,vm-ffi-qemu-linux-release-arm-try,vm-ffi-qemu-linux-release-riscv64-try,vm-fuchsia-release-x64-try,vm-linux-debug-ia32-try,vm-linux-debug-x64-try,vm-linux-debug-x64c-try,vm-mac-debug-arm64-try,vm-mac-debug-x64-try,vm-msan-linux-release-arm64-try,vm-msan-linux-release-x64-try,vm-reload-linux-debug-x64-try,vm-reload-rollback-linux-debug-x64-try,vm-tsan-linux-release-arm64-try,vm-tsan-linux-release-x64-try,vm-ubsan-linux-release-arm64-try,vm-ubsan-linux-release-x64-try,vm-win-debug-x64-try,vm-win-debug-x64c-try,vm-win-release-ia32-try Change-Id: Ia073cb6bb9e1b5a0ea8514c7e048cee6019b84d6 Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/420324 Commit-Queue: Slava Egorov <vegorov@google.com> Reviewed-by: Daco Harkes <dacoharkes@google.com>
1276 lines
43 KiB
C++
1276 lines
43 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#ifndef RUNTIME_VM_COMPILER_ASSEMBLER_ASSEMBLER_IA32_H_
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#define RUNTIME_VM_COMPILER_ASSEMBLER_ASSEMBLER_IA32_H_
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#if defined(DART_PRECOMPILED_RUNTIME)
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#error "AOT runtime should not use compiler sources (including header files)"
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#endif // defined(DART_PRECOMPILED_RUNTIME)
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#ifndef RUNTIME_VM_COMPILER_ASSEMBLER_ASSEMBLER_H_
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#error Do not include assembler_ia32.h directly; use assembler.h instead.
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#endif
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#include <functional>
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#include "platform/assert.h"
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#include "platform/utils.h"
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#include "vm/compiler/assembler/assembler_base.h"
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#include "vm/constants.h"
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#include "vm/constants_x86.h"
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#include "vm/pointer_tagging.h"
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namespace dart {
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namespace compiler {
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class Immediate : public ValueObject {
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public:
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explicit Immediate(int32_t value) : value_(value) {}
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Immediate(const Immediate& other) : ValueObject(), value_(other.value_) {}
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int32_t value() const { return value_; }
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bool is_int8() const { return Utils::IsInt(8, value_); }
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bool is_uint8() const { return Utils::IsUint(8, value_); }
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bool is_uint16() const { return Utils::IsUint(16, value_); }
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private:
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const int32_t value_;
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// TODO(5411081): Add DISALLOW_COPY_AND_ASSIGN(Immediate) once the mac
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// build issue is resolved.
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// And remove the unnecessary copy constructor.
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};
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class Operand : public ValueObject {
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public:
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uint8_t mod() const { return (encoding_at(0) >> 6) & 3; }
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Register rm() const { return static_cast<Register>(encoding_at(0) & 7); }
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ScaleFactor scale() const {
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return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3);
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}
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Register index() const {
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return static_cast<Register>((encoding_at(1) >> 3) & 7);
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}
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Register base() const { return static_cast<Register>(encoding_at(1) & 7); }
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int8_t disp8() const {
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ASSERT(length_ >= 2);
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return static_cast<int8_t>(encoding_[length_ - 1]);
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}
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int32_t disp32() const {
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ASSERT(length_ >= 5);
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return bit_copy<int32_t>(encoding_[length_ - 4]);
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}
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Operand(const Operand& other) : ValueObject(), length_(other.length_) {
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memmove(&encoding_[0], &other.encoding_[0], other.length_);
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}
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Operand& operator=(const Operand& other) {
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length_ = other.length_;
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memmove(&encoding_[0], &other.encoding_[0], other.length_);
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return *this;
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}
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bool Equals(const Operand& other) const {
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if (length_ != other.length_) return false;
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for (uint8_t i = 0; i < length_; i++) {
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if (encoding_[i] != other.encoding_[i]) return false;
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}
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return true;
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}
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protected:
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Operand() : length_(0) {} // Needed by subclass Address.
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void SetModRM(int mod, Register rm) {
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ASSERT((mod & ~3) == 0);
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encoding_[0] = (mod << 6) | rm;
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length_ = 1;
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}
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void SetSIB(ScaleFactor scale, Register index, Register base) {
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ASSERT(length_ == 1);
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ASSERT((scale & ~3) == 0);
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encoding_[1] = (scale << 6) | (index << 3) | base;
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length_ = 2;
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}
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void SetDisp8(int8_t disp) {
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ASSERT(length_ == 1 || length_ == 2);
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encoding_[length_++] = static_cast<uint8_t>(disp);
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}
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void SetDisp32(int32_t disp) {
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ASSERT(length_ == 1 || length_ == 2);
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intptr_t disp_size = sizeof(disp);
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memmove(&encoding_[length_], &disp, disp_size);
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length_ += disp_size;
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}
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private:
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uint8_t length_;
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uint8_t encoding_[6];
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uint8_t padding_;
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explicit Operand(Register reg) { SetModRM(3, reg); }
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// Get the operand encoding byte at the given index.
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uint8_t encoding_at(intptr_t index) const {
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ASSERT(index >= 0 && index < length_);
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return encoding_[index];
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}
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// Returns whether or not this operand is really the given register in
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// disguise. Used from the assembler to generate better encodings.
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bool IsRegister(Register reg) const {
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return ((encoding_[0] & 0xF8) == 0xC0) // Addressing mode is register only.
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&& ((encoding_[0] & 0x07) == reg); // Register codes match.
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}
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friend class Assembler;
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};
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class Address : public Operand {
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public:
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Address(Register base, int32_t disp) {
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if (disp == 0 && base != EBP) {
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SetModRM(0, base);
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if (base == ESP) SetSIB(TIMES_1, ESP, base);
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} else if (Utils::IsInt(8, disp)) {
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SetModRM(1, base);
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if (base == ESP) SetSIB(TIMES_1, ESP, base);
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SetDisp8(disp);
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} else {
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SetModRM(2, base);
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if (base == ESP) SetSIB(TIMES_1, ESP, base);
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SetDisp32(disp);
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}
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}
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Address(Register index, ScaleFactor scale, int32_t disp) {
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ASSERT(index != ESP); // Illegal addressing mode.
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ASSERT(scale != TIMES_16); // Unsupported scale factor.
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SetModRM(0, ESP);
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SetSIB(scale, index, EBP);
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SetDisp32(disp);
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}
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// This addressing mode does not exist.
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Address(Register index, ScaleFactor scale, Register r);
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Address(Register base, Register index, ScaleFactor scale, int32_t disp) {
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ASSERT(index != ESP); // Illegal addressing mode.
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ASSERT(scale != TIMES_16); // Unsupported scale factor.
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if (disp == 0 && base != EBP) {
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SetModRM(0, ESP);
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SetSIB(scale, index, base);
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} else if (Utils::IsInt(8, disp)) {
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SetModRM(1, ESP);
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SetSIB(scale, index, base);
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SetDisp8(disp);
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} else {
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SetModRM(2, ESP);
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SetSIB(scale, index, base);
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SetDisp32(disp);
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}
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}
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// This addressing mode does not exist.
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Address(Register base, Register index, ScaleFactor scale, Register r);
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Address(const Address& other) : Operand(other) {}
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Address& operator=(const Address& other) {
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Operand::operator=(other);
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return *this;
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}
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static Address Absolute(const uword addr) {
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Address result;
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result.SetModRM(0, EBP);
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result.SetDisp32(addr);
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return result;
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}
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private:
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Address() {} // Needed by Address::Absolute.
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};
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class FieldAddress : public Address {
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public:
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FieldAddress(Register base, int32_t disp)
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: Address(base, disp - kHeapObjectTag) {}
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// This addressing mode does not exist.
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FieldAddress(Register base, Register r);
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FieldAddress(Register base, Register index, ScaleFactor scale, int32_t disp)
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: Address(base, index, scale, disp - kHeapObjectTag) {}
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// This addressing mode does not exist.
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FieldAddress(Register base, Register index, ScaleFactor scale, Register r);
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FieldAddress(const FieldAddress& other) : Address(other) {}
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FieldAddress& operator=(const FieldAddress& other) {
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Address::operator=(other);
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return *this;
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}
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};
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class Assembler : public AssemblerBase {
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public:
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explicit Assembler(ObjectPoolBuilder* object_pool_builder,
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intptr_t far_branch_level = 0)
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: AssemblerBase(object_pool_builder),
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jit_cookie_(0),
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code_(NewZoneHandle(ThreadState::Current()->zone())) {
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// This mode is only needed and implemented for ARM.
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ASSERT(far_branch_level == 0);
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}
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~Assembler() {}
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/*
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* Emit Machine Instructions.
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*/
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void call(Register reg);
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void call(const Address& address);
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void call(Label* label);
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void call(const ExternalLabel* label);
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static constexpr intptr_t kCallExternalLabelSize = 5;
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void pushl(Register reg);
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void pushl(const Address& address);
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void pushl(const Immediate& imm);
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void PushImmediate(int32_t value) { pushl(Immediate(value)); }
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void popl(Register reg);
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void popl(const Address& address);
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void pushal();
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void popal();
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void setcc(Condition condition, ByteRegister dst);
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void movl(Register dst, const Immediate& src);
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void movl(Register dst, Register src);
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void movl(Register dst, const Address& src);
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void movl(const Address& dst, Register src);
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void movl(const Address& dst, const Immediate& imm);
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void movzxb(Register dst, ByteRegister src);
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void movzxb(Register dst, const Address& src);
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void movsxb(Register dst, ByteRegister src);
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void movsxb(Register dst, const Address& src);
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void movb(Register dst, const Address& src);
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void movb(const Address& dst, Register src);
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void movb(const Address& dst, ByteRegister src);
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void movb(const Address& dst, const Immediate& imm);
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void movzxw(Register dst, Register src);
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void movzxw(Register dst, const Address& src);
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void movsxw(Register dst, Register src);
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void movsxw(Register dst, const Address& src);
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void movw(Register dst, const Address& src);
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void movw(const Address& dst, Register src);
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void movw(const Address& dst, const Immediate& imm);
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void leal(Register dst, const Address& src);
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void cmovno(Register dst, Register src);
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void cmove(Register dst, Register src);
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void cmovne(Register dst, Register src);
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void cmovs(Register dst, Register src);
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void cmovns(Register dst, Register src);
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void cmovgel(Register dst, Register src);
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void cmovlessl(Register dst, Register src);
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void rep_movsb();
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void rep_movsw();
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void rep_movsd();
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void movss(XmmRegister dst, const Address& src);
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void movss(const Address& dst, XmmRegister src);
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void movss(XmmRegister dst, XmmRegister src);
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void movd(XmmRegister dst, Register src);
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void movd(Register dst, XmmRegister src);
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void movq(const Address& dst, XmmRegister src);
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void movq(XmmRegister dst, const Address& src);
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void addss(XmmRegister dst, XmmRegister src);
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void addss(XmmRegister dst, const Address& src);
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void subss(XmmRegister dst, XmmRegister src);
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void subss(XmmRegister dst, const Address& src);
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void mulss(XmmRegister dst, XmmRegister src);
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void mulss(XmmRegister dst, const Address& src);
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void divss(XmmRegister dst, XmmRegister src);
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void divss(XmmRegister dst, const Address& src);
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void movsd(XmmRegister dst, const Address& src);
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void movsd(const Address& dst, XmmRegister src);
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void movsd(XmmRegister dst, XmmRegister src);
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void movaps(XmmRegister dst, XmmRegister src);
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void movups(XmmRegister dst, const Address& src);
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void movups(const Address& dst, XmmRegister src);
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void addsd(XmmRegister dst, XmmRegister src);
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void addsd(XmmRegister dst, const Address& src);
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void subsd(XmmRegister dst, XmmRegister src);
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void subsd(XmmRegister dst, const Address& src);
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void mulsd(XmmRegister dst, XmmRegister src);
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void mulsd(XmmRegister dst, const Address& src);
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void divsd(XmmRegister dst, XmmRegister src);
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void divsd(XmmRegister dst, const Address& src);
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void addpl(XmmRegister dst, XmmRegister src);
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void subpl(XmmRegister dst, XmmRegister src);
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void addps(XmmRegister dst, XmmRegister src);
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void subps(XmmRegister dst, XmmRegister src);
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void divps(XmmRegister dst, XmmRegister src);
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void mulps(XmmRegister dst, XmmRegister src);
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void minps(XmmRegister dst, XmmRegister src);
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void maxps(XmmRegister dst, XmmRegister src);
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void andps(XmmRegister dst, XmmRegister src);
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void andps(XmmRegister dst, const Address& src);
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void orps(XmmRegister dst, XmmRegister src);
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void notps(XmmRegister dst);
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void negateps(XmmRegister dst);
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void absps(XmmRegister dst);
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void zerowps(XmmRegister dst);
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void cmppseq(XmmRegister dst, XmmRegister src);
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void cmppsneq(XmmRegister dst, XmmRegister src);
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void cmppslt(XmmRegister dst, XmmRegister src);
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void cmppsle(XmmRegister dst, XmmRegister src);
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void cmppsnlt(XmmRegister dst, XmmRegister src);
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void cmppsnle(XmmRegister dst, XmmRegister src);
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void sqrtps(XmmRegister dst);
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void rsqrtps(XmmRegister dst);
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void reciprocalps(XmmRegister dst);
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void movhlps(XmmRegister dst, XmmRegister src);
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void movlhps(XmmRegister dst, XmmRegister src);
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void unpcklps(XmmRegister dst, XmmRegister src);
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void unpckhps(XmmRegister dst, XmmRegister src);
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void unpcklpd(XmmRegister dst, XmmRegister src);
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void unpckhpd(XmmRegister dst, XmmRegister src);
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void set1ps(XmmRegister dst, Register tmp, const Immediate& imm);
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void shufps(XmmRegister dst, XmmRegister src, const Immediate& mask);
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void addpd(XmmRegister dst, XmmRegister src);
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void negatepd(XmmRegister dst);
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void subpd(XmmRegister dst, XmmRegister src);
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void mulpd(XmmRegister dst, XmmRegister src);
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void divpd(XmmRegister dst, XmmRegister src);
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void abspd(XmmRegister dst);
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void minpd(XmmRegister dst, XmmRegister src);
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void maxpd(XmmRegister dst, XmmRegister src);
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void sqrtpd(XmmRegister dst);
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void cvtps2pd(XmmRegister dst, XmmRegister src);
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void cvtpd2ps(XmmRegister dst, XmmRegister src);
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void shufpd(XmmRegister dst, XmmRegister src, const Immediate& mask);
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void cvtsi2ss(XmmRegister dst, Register src);
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void cvtsi2sd(XmmRegister dst, Register src);
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void cvtss2si(Register dst, XmmRegister src);
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void cvtss2sd(XmmRegister dst, XmmRegister src);
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void cvtsd2si(Register dst, XmmRegister src);
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void cvtsd2ss(XmmRegister dst, XmmRegister src);
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void cvttss2si(Register dst, XmmRegister src);
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void cvttsd2si(Register dst, XmmRegister src);
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void cvtdq2pd(XmmRegister dst, XmmRegister src);
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void comiss(XmmRegister a, XmmRegister b);
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void comisd(XmmRegister a, XmmRegister b);
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void movmskpd(Register dst, XmmRegister src);
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void movmskps(Register dst, XmmRegister src);
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void pmovmskb(Register dst, XmmRegister src);
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void sqrtsd(XmmRegister dst, XmmRegister src);
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void sqrtss(XmmRegister dst, XmmRegister src);
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void xorpd(XmmRegister dst, const Address& src);
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void xorpd(XmmRegister dst, XmmRegister src);
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void xorps(XmmRegister dst, const Address& src);
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void xorps(XmmRegister dst, XmmRegister src);
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void andpd(XmmRegister dst, const Address& src);
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void andpd(XmmRegister dst, XmmRegister src);
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void orpd(XmmRegister dst, XmmRegister src);
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void pextrd(Register dst, XmmRegister src, const Immediate& imm);
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void pmovsxdq(XmmRegister dst, XmmRegister src);
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void pcmpeqq(XmmRegister dst, XmmRegister src);
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void pxor(XmmRegister dst, XmmRegister src);
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enum RoundingMode {
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kRoundToNearest = 0x0,
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kRoundDown = 0x1,
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kRoundUp = 0x2,
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kRoundToZero = 0x3
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};
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void roundsd(XmmRegister dst, XmmRegister src, RoundingMode mode);
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void flds(const Address& src);
|
|
void fstps(const Address& dst);
|
|
|
|
void fldl(const Address& src);
|
|
void fstpl(const Address& dst);
|
|
|
|
void fnstcw(const Address& dst);
|
|
void fldcw(const Address& src);
|
|
|
|
void fistpl(const Address& dst);
|
|
void fistps(const Address& dst);
|
|
void fildl(const Address& src);
|
|
void filds(const Address& src);
|
|
|
|
void fincstp();
|
|
void ffree(intptr_t value);
|
|
|
|
void fsin();
|
|
void fcos();
|
|
void fsincos();
|
|
void fptan();
|
|
|
|
void xchgl(Register dst, Register src);
|
|
|
|
void cmpw(const Address& address, const Immediate& imm);
|
|
void cmpb(const Address& address, const Immediate& imm);
|
|
|
|
void testl(Register reg1, Register reg2);
|
|
void testl(Register reg, const Immediate& imm);
|
|
void testl(const Address& address, const Immediate& imm);
|
|
void testl(const Address& address, Register reg);
|
|
void testb(const Address& address, const Immediate& imm);
|
|
void testb(const Address& address, ByteRegister reg);
|
|
|
|
// clang-format off
|
|
// Macro for handling common ALU instructions. Arguments to F:
|
|
// name, opcode, reversed opcode, opcode for the reg field of the modrm byte.
|
|
#define ALU_OPS(F) \
|
|
F(and, 0x23, 0x21, 4) \
|
|
F(or, 0x0b, 0x09, 1) \
|
|
F(xor, 0x33, 0x31, 6) \
|
|
F(add, 0x03, 0x01, 0) \
|
|
F(adc, 0x13, 0x11, 2) \
|
|
F(sub, 0x2b, 0x29, 5) \
|
|
F(sbb, 0x1b, 0x19, 3) \
|
|
F(cmp, 0x3b, 0x39, 7)
|
|
// clang-format on
|
|
|
|
#define DECLARE_ALU(op, opcode, opcode2, modrm_opcode) \
|
|
void op##l(Register dst, Register src) { Alu(4, opcode, dst, src); } \
|
|
void op##w(Register dst, Register src) { Alu(2, opcode, dst, src); } \
|
|
void op##l(Register dst, const Address& src) { Alu(4, opcode, dst, src); } \
|
|
void op##w(Register dst, const Address& src) { Alu(2, opcode, dst, src); } \
|
|
void op##l(const Address& dst, Register src) { Alu(4, opcode2, dst, src); } \
|
|
void op##w(const Address& dst, Register src) { Alu(2, opcode2, dst, src); } \
|
|
void op##l(Register dst, const Immediate& imm) { \
|
|
Alu(modrm_opcode, dst, imm); \
|
|
} \
|
|
void op##l(const Address& dst, const Immediate& imm) { \
|
|
Alu(modrm_opcode, dst, imm); \
|
|
}
|
|
|
|
ALU_OPS(DECLARE_ALU);
|
|
|
|
#undef DECLARE_ALU
|
|
#undef ALU_OPS
|
|
|
|
void cdq();
|
|
|
|
void idivl(Register reg);
|
|
|
|
void divl(Register reg);
|
|
|
|
void imull(Register dst, Register src);
|
|
void imull(Register reg, const Immediate& imm);
|
|
void imull(Register reg, const Address& address);
|
|
|
|
void imull(Register reg);
|
|
void imull(const Address& address);
|
|
|
|
void mull(Register reg);
|
|
void mull(const Address& address);
|
|
|
|
void incl(Register reg);
|
|
void incl(const Address& address);
|
|
|
|
void decl(Register reg);
|
|
void decl(const Address& address);
|
|
|
|
void shll(Register reg, const Immediate& imm);
|
|
void shll(Register operand, Register shifter);
|
|
void shll(const Address& operand, Register shifter);
|
|
void shrl(Register reg, const Immediate& imm);
|
|
void shrl(Register operand, Register shifter);
|
|
void sarl(Register reg, const Immediate& imm);
|
|
void sarl(Register operand, Register shifter);
|
|
void sarl(const Address& address, Register shifter);
|
|
void shldl(Register dst, Register src, Register shifter);
|
|
void shldl(Register dst, Register src, const Immediate& imm);
|
|
void shldl(const Address& operand, Register src, Register shifter);
|
|
void shrdl(Register dst, Register src, Register shifter);
|
|
void shrdl(Register dst, Register src, const Immediate& imm);
|
|
void shrdl(const Address& dst, Register src, Register shifter);
|
|
|
|
void negl(Register reg);
|
|
void notl(Register reg);
|
|
|
|
void bsfl(Register dst, Register src);
|
|
void bsrl(Register dst, Register src);
|
|
void popcntl(Register dst, Register src);
|
|
void lzcntl(Register dst, Register src);
|
|
|
|
void bt(Register base, Register offset);
|
|
void bt(Register base, int bit);
|
|
|
|
void enter(const Immediate& imm);
|
|
void leave();
|
|
|
|
void ret();
|
|
void ret(const Immediate& imm);
|
|
|
|
// 'size' indicates size in bytes and must be in the range 1..8.
|
|
void nop(int size = 1);
|
|
void int3();
|
|
void hlt();
|
|
|
|
void j(Condition condition, Label* label, JumpDistance distance = kFarJump);
|
|
void j(Condition condition, const ExternalLabel* label);
|
|
|
|
void jmp(Register reg);
|
|
void jmp(const Address& address);
|
|
void jmp(Label* label, JumpDistance distance = kFarJump);
|
|
void jmp(const ExternalLabel* label);
|
|
|
|
void lock();
|
|
void cmpxchgl(const Address& address, Register reg);
|
|
|
|
void cld();
|
|
void std();
|
|
|
|
void cpuid();
|
|
|
|
/*
|
|
* Macros for High-level operations and implemented on all architectures.
|
|
*/
|
|
|
|
void Ret() { ret(); }
|
|
|
|
// Sets the return address to [value] as if there was a call.
|
|
// On IA32 pushes [value].
|
|
void SetReturnAddress(Register value) { PushRegister(value); }
|
|
|
|
void PushValueAtOffset(Register base, int32_t offset) {
|
|
pushl(Address(base, offset));
|
|
}
|
|
|
|
void CompareRegisters(Register a, Register b);
|
|
void CompareObjectRegisters(Register a, Register b) {
|
|
CompareRegisters(a, b);
|
|
}
|
|
void BranchIf(Condition condition,
|
|
Label* label,
|
|
JumpDistance distance = kFarJump) {
|
|
j(condition, label, distance);
|
|
}
|
|
void BranchIfZero(Register src,
|
|
Label* label,
|
|
JumpDistance distance = kFarJump) {
|
|
cmpl(src, Immediate(0));
|
|
j(ZERO, label, distance);
|
|
}
|
|
void BranchIfBit(Register rn,
|
|
intptr_t bit_number,
|
|
Condition condition,
|
|
Label* label,
|
|
JumpDistance distance = kFarJump) {
|
|
testl(rn, Immediate(1 << bit_number));
|
|
j(condition, label, distance);
|
|
}
|
|
|
|
// Arch-specific Load to choose the right operation for [sz].
|
|
void Load(Register dst,
|
|
const Address& address,
|
|
OperandSize sz = kFourBytes) override;
|
|
void LoadIndexedPayload(Register dst,
|
|
Register base,
|
|
int32_t payload_offset,
|
|
Register index,
|
|
ScaleFactor scale,
|
|
OperandSize sz = kFourBytes) override {
|
|
Load(dst, FieldAddress(base, index, scale, payload_offset), sz);
|
|
}
|
|
void Store(Register src,
|
|
const Address& address,
|
|
OperandSize sz = kFourBytes) override;
|
|
void Store(const Object& value, const Address& address);
|
|
void StoreZero(const Address& address, Register temp = kNoRegister) {
|
|
movl(address, Immediate(0));
|
|
}
|
|
void LoadFromStack(Register dst, intptr_t depth);
|
|
void StoreToStack(Register src, intptr_t depth);
|
|
void CompareToStack(Register src, intptr_t depth);
|
|
void LoadMemoryValue(Register dst, Register base, int32_t offset) {
|
|
movl(dst, Address(base, offset));
|
|
}
|
|
void StoreMemoryValue(Register src, Register base, int32_t offset) {
|
|
movl(Address(base, offset), src);
|
|
}
|
|
|
|
void LoadUnboxedDouble(FpuRegister dst, Register base, int32_t offset) {
|
|
movsd(dst, Address(base, offset));
|
|
}
|
|
void StoreUnboxedDouble(FpuRegister src, Register base, int32_t offset) {
|
|
movsd(Address(base, offset), src);
|
|
}
|
|
void MoveUnboxedDouble(FpuRegister dst, FpuRegister src) {
|
|
if (src != dst) {
|
|
movaps(dst, src);
|
|
}
|
|
}
|
|
|
|
void LoadUnboxedSimd128(FpuRegister dst, Register base, int32_t offset) {
|
|
movups(dst, Address(base, offset));
|
|
}
|
|
void StoreUnboxedSimd128(FpuRegister dst, Register base, int32_t offset) {
|
|
movups(Address(base, offset), dst);
|
|
}
|
|
void MoveUnboxedSimd128(FpuRegister dst, FpuRegister src) {
|
|
if (src != dst) {
|
|
movaps(dst, src);
|
|
}
|
|
}
|
|
|
|
void LoadAcquire(Register dst,
|
|
const Address& address,
|
|
OperandSize size = kFourBytes) override {
|
|
// On intel loads have load-acquire behavior (i.e. loads are not re-ordered
|
|
// with other loads).
|
|
Load(dst, address, size);
|
|
if (FLAG_target_thread_sanitizer) {
|
|
FATAL("No support for TSAN on IA32.");
|
|
}
|
|
}
|
|
void StoreRelease(Register src,
|
|
const Address& address,
|
|
OperandSize size = kFourBytes) override {
|
|
// On intel stores have store-release behavior (i.e. stores are not
|
|
// re-ordered with other stores).
|
|
Store(src, address, size);
|
|
if (FLAG_target_thread_sanitizer) {
|
|
FATAL("No support for TSAN on IA32.");
|
|
}
|
|
}
|
|
|
|
void CompareWithMemoryValue(Register value,
|
|
Address address,
|
|
OperandSize size = kFourBytes) override {
|
|
ASSERT_EQUAL(size, kFourBytes);
|
|
cmpl(value, address);
|
|
}
|
|
|
|
void ExtendValue(Register to, Register from, OperandSize sz) override;
|
|
void PushRegister(Register r);
|
|
void PopRegister(Register r);
|
|
|
|
void PushRegisterPair(Register r0, Register r1) {
|
|
PushRegister(r1);
|
|
PushRegister(r0);
|
|
}
|
|
void PopRegisterPair(Register r0, Register r1) {
|
|
PopRegister(r0);
|
|
PopRegister(r1);
|
|
}
|
|
|
|
void PushRegistersInOrder(std::initializer_list<Register> regs);
|
|
|
|
void AddImmediate(Register reg, const Immediate& imm);
|
|
void AddImmediate(Register reg, int32_t value) {
|
|
AddImmediate(reg, Immediate(value));
|
|
}
|
|
void AddImmediate(Register dest, Register src, int32_t value);
|
|
void AddRegisters(Register dest, Register src) { addl(dest, src); }
|
|
void AddScaled(Register dest,
|
|
Register base,
|
|
Register index,
|
|
ScaleFactor scale,
|
|
int32_t disp) override {
|
|
if (base == kNoRegister) {
|
|
leal(dest, Address(index, scale, disp));
|
|
} else {
|
|
leal(dest, Address(base, index, scale, disp));
|
|
}
|
|
}
|
|
void SubImmediate(Register reg, const Immediate& imm);
|
|
void SubRegisters(Register dest, Register src) { subl(dest, src); }
|
|
void MulImmediate(Register reg,
|
|
int32_t imm,
|
|
OperandSize width = kFourBytes) override {
|
|
ASSERT(width == kFourBytes);
|
|
if (Utils::IsPowerOfTwo(imm)) {
|
|
const intptr_t shift = Utils::ShiftForPowerOfTwo(imm);
|
|
shll(reg, Immediate(shift));
|
|
} else {
|
|
imull(reg, Immediate(imm));
|
|
}
|
|
}
|
|
void AndImmediate(Register reg,
|
|
int32_t value,
|
|
OperandSize sz = kFourBytes) override {
|
|
AndImmediate(reg, reg, value, sz);
|
|
}
|
|
void AndImmediate(Register dst,
|
|
Register src,
|
|
int32_t value,
|
|
OperandSize sz = kFourBytes) override;
|
|
void AndRegisters(Register dst,
|
|
Register src1,
|
|
Register src2 = kNoRegister) override;
|
|
void OrImmediate(Register dst, int32_t value) { orl(dst, Immediate(value)); }
|
|
void LslImmediate(Register dst,
|
|
Register src,
|
|
int32_t shift,
|
|
OperandSize sz = kFourBytes) override {
|
|
ASSERT((shift >= 0) && (shift < OperandSizeInBits(sz)));
|
|
ExtendValue(dst, src, sz);
|
|
if (shift != 0) {
|
|
shll(dst, Immediate(shift));
|
|
}
|
|
}
|
|
void LslImmediate(Register reg,
|
|
int32_t shift,
|
|
OperandSize sz = kFourBytes) override {
|
|
LslImmediate(reg, reg, shift, sz);
|
|
}
|
|
void LslRegister(Register dst, Register shift) override {
|
|
ASSERT_EQUAL(shift, ECX); // IA32 does not have a TMP.
|
|
shll(dst, shift);
|
|
}
|
|
void LsrImmediate(Register dst, int32_t shift) override {
|
|
shrl(dst, Immediate(shift));
|
|
}
|
|
|
|
void CompareImmediate(Register reg,
|
|
int32_t immediate,
|
|
OperandSize width = kFourBytes) override {
|
|
ASSERT_EQUAL(width, kFourBytes);
|
|
cmpl(reg, Immediate(immediate));
|
|
}
|
|
|
|
void LoadImmediate(Register reg, int32_t immediate) override {
|
|
if (immediate == 0) {
|
|
xorl(reg, reg);
|
|
} else {
|
|
movl(reg, Immediate(immediate));
|
|
}
|
|
}
|
|
|
|
void LoadImmediate(Register reg, Immediate immediate) {
|
|
LoadImmediate(reg, immediate.value());
|
|
}
|
|
|
|
void LoadSImmediate(XmmRegister dst, float value);
|
|
void LoadDImmediate(XmmRegister dst, double value);
|
|
void LoadQImmediate(XmmRegister dst, simd128_value_t value);
|
|
|
|
void Drop(intptr_t stack_elements);
|
|
|
|
void LoadIsolate(Register dst);
|
|
void LoadIsolateGroup(Register dst);
|
|
|
|
void LoadUniqueObject(Register dst, const Object& object) {
|
|
LoadObject(dst, object, /*movable_referent=*/true);
|
|
}
|
|
|
|
void LoadObject(Register dst,
|
|
const Object& object,
|
|
bool movable_referent = false);
|
|
|
|
// If 'object' is a large Smi, xor it with a per-assembler cookie value to
|
|
// prevent user-controlled immediates from appearing in the code stream.
|
|
void LoadObjectSafely(Register dst, const Object& object);
|
|
|
|
void PushObject(const Object& object);
|
|
void CompareObject(Register reg, const Object& object);
|
|
|
|
void InitializeHeader(Register tags, Register object) {
|
|
movl(FieldAddress(object, target::Object::tags_offset()), tags);
|
|
// No fence: all stores are ordered on ia32.
|
|
}
|
|
void InitializeHeader(Immediate tags, Register object) {
|
|
movl(FieldAddress(object, target::Object::tags_offset()), tags);
|
|
// No fence: all stores are ordered on ia32.
|
|
}
|
|
|
|
void StoreObjectIntoObjectNoBarrier(
|
|
Register object,
|
|
const Address& dest,
|
|
const Object& value,
|
|
MemoryOrder memory_order = kRelaxedNonAtomic,
|
|
OperandSize size = kFourBytes) override;
|
|
|
|
void StoreBarrier(Register object,
|
|
Register value,
|
|
CanBeSmi can_be_smi,
|
|
Register scratch) override;
|
|
void ArrayStoreBarrier(Register object,
|
|
Register slot,
|
|
Register value,
|
|
CanBeSmi can_be_smi,
|
|
Register scratch) override;
|
|
void VerifyStoreNeedsNoWriteBarrier(Register object, Register value) override;
|
|
|
|
// Stores a non-tagged value into a heap object.
|
|
void StoreInternalPointer(Register object,
|
|
const Address& dest,
|
|
Register value);
|
|
|
|
// Stores a Smi value into a heap object field that always contains a Smi.
|
|
void StoreIntoSmiField(const Address& dest, Register value);
|
|
void ZeroInitSmiField(const Address& dest);
|
|
// Increments a Smi field. Leaves flags in same state as an 'addl'.
|
|
void IncrementSmiField(const Address& dest, int32_t increment);
|
|
|
|
void DoubleNegate(XmmRegister d);
|
|
void FloatNegate(XmmRegister f);
|
|
|
|
void DoubleAbs(XmmRegister reg);
|
|
|
|
void LockCmpxchgl(const Address& address, Register reg) {
|
|
lock();
|
|
cmpxchgl(address, reg);
|
|
}
|
|
|
|
void EnterFrame(intptr_t frame_space);
|
|
void LeaveFrame();
|
|
void ReserveAlignedFrameSpace(intptr_t frame_space);
|
|
|
|
void MonomorphicCheckedEntryJIT();
|
|
void MonomorphicCheckedEntryAOT();
|
|
void BranchOnMonomorphicCheckedEntryJIT(Label* label);
|
|
|
|
void CombineHashes(Register dst, Register other) override;
|
|
void FinalizeHashForSize(intptr_t bit_size,
|
|
Register dst,
|
|
Register scratch = kNoRegister) override;
|
|
|
|
// In debug mode, this generates code to check that:
|
|
// FP + kExitLinkSlotFromEntryFp == SP
|
|
// or triggers breakpoint otherwise.
|
|
//
|
|
// Clobbers EAX.
|
|
void EmitEntryFrameVerification();
|
|
|
|
// Transitions safepoint and Thread state between generated and native code.
|
|
// Updates top-exit-frame info, VM tag and execution-state. Leaves/enters a
|
|
// safepoint.
|
|
//
|
|
// Require a temporary register 'tmp'.
|
|
// Clobber all non-CPU registers (e.g. XMM registers and the "FPU stack").
|
|
// However XMM0 is saved for convenience.
|
|
void TransitionGeneratedToNative(Register destination_address,
|
|
Register new_exit_frame,
|
|
Register new_exit_through_ffi,
|
|
bool enter_safepoint);
|
|
void TransitionNativeToGenerated(Register scratch,
|
|
bool exit_safepoint,
|
|
bool set_tag = true);
|
|
void EnterFullSafepoint(Register scratch);
|
|
void ExitFullSafepoint(Register scratch);
|
|
|
|
// For non-leaf runtime calls. For leaf runtime calls, use LeafRuntimeScope,
|
|
void CallRuntime(const RuntimeEntry& entry, intptr_t argument_count);
|
|
|
|
void Call(const Code& code,
|
|
bool movable_target = false,
|
|
CodeEntryKind entry_kind = CodeEntryKind::kNormal);
|
|
// Will not clobber any registers and can therefore be called with 5 live
|
|
// registers.
|
|
void CallVmStub(const Code& code);
|
|
|
|
void Call(Address target) { call(target); }
|
|
|
|
void CallCFunction(Address target) { Call(target); }
|
|
|
|
void CallCFunction(Register target) { call(target); }
|
|
|
|
void Jmp(const Code& code);
|
|
void J(Condition condition, const Code& code);
|
|
|
|
void RangeCheck(Register value,
|
|
Register temp,
|
|
intptr_t low,
|
|
intptr_t high,
|
|
RangeCheckCondition condition,
|
|
Label* target) override;
|
|
|
|
/*
|
|
* Loading and comparing classes of objects.
|
|
*/
|
|
void LoadClassId(Register result, Register object);
|
|
|
|
void LoadClassById(Register result, Register class_id);
|
|
|
|
void CompareClassId(Register object, intptr_t class_id, Register scratch);
|
|
|
|
void LoadClassIdMayBeSmi(Register result, Register object);
|
|
void LoadTaggedClassIdMayBeSmi(Register result, Register object);
|
|
void EnsureHasClassIdInDEBUG(intptr_t cid,
|
|
Register src,
|
|
Register scratch,
|
|
bool can_be_null = false) override;
|
|
|
|
void SmiUntagOrCheckClass(Register object,
|
|
intptr_t class_id,
|
|
Register scratch,
|
|
Label* is_smi);
|
|
|
|
static bool AddressCanHoldConstantIndex(const Object& constant,
|
|
bool is_external,
|
|
intptr_t cid,
|
|
intptr_t index_scale);
|
|
|
|
static Address ElementAddressForIntIndex(bool is_external,
|
|
intptr_t cid,
|
|
intptr_t index_scale,
|
|
Register array,
|
|
intptr_t index,
|
|
intptr_t extra_disp = 0);
|
|
|
|
static Address ElementAddressForRegIndex(bool is_external,
|
|
intptr_t cid,
|
|
intptr_t index_scale,
|
|
bool index_unboxed,
|
|
Register array,
|
|
Register index,
|
|
intptr_t extra_disp = 0);
|
|
|
|
void LoadStaticFieldAddress(Register address,
|
|
Register field,
|
|
Register scratch,
|
|
bool is_shared) {
|
|
LoadFieldFromOffset(scratch, field,
|
|
target::Field::host_offset_or_field_id_offset());
|
|
const intptr_t field_table_offset =
|
|
is_shared ? compiler::target::Thread::shared_field_table_values_offset()
|
|
: compiler::target::Thread::field_table_values_offset();
|
|
LoadMemoryValue(address, THR, static_cast<int32_t>(field_table_offset));
|
|
static_assert(kSmiTagShift == 1, "adjust scale factor");
|
|
leal(address, Address(address, scratch, TIMES_HALF_WORD_SIZE, 0));
|
|
}
|
|
|
|
void LoadFieldAddressForRegOffset(Register address,
|
|
Register instance,
|
|
Register offset_in_words_as_smi) override {
|
|
static_assert(kSmiTagShift == 1, "adjust scale factor");
|
|
leal(address, FieldAddress(instance, offset_in_words_as_smi, TIMES_2, 0));
|
|
}
|
|
|
|
void LoadFieldAddressForOffset(Register address,
|
|
Register instance,
|
|
int32_t offset) override {
|
|
leal(address, FieldAddress(instance, offset));
|
|
}
|
|
|
|
static Address VMTagAddress() {
|
|
return Address(THR, target::Thread::vm_tag_offset());
|
|
}
|
|
|
|
/*
|
|
* Misc. functionality
|
|
*/
|
|
void SmiTag(Register reg) override { addl(reg, reg); }
|
|
|
|
void SmiUntag(Register reg) { sarl(reg, Immediate(kSmiTagSize)); }
|
|
|
|
// Truncates upper bits.
|
|
void LoadInt32FromBoxOrSmi(Register result, Register value) override {
|
|
if (result != value) {
|
|
MoveRegister(result, value);
|
|
value = result;
|
|
}
|
|
ASSERT(value == result);
|
|
compiler::Label done;
|
|
SmiUntag(result); // Leaves CF after SmiUntag.
|
|
j(NOT_CARRY, &done, compiler::Assembler::kNearJump);
|
|
// Undo untagging by multiplying value by 2.
|
|
// [reg + reg + disp8] has a shorter encoding than [reg*2 + disp32]
|
|
COMPILE_ASSERT(kSmiTagShift == 1);
|
|
movl(result, compiler::Address(result, result, TIMES_1,
|
|
target::Mint::value_offset()));
|
|
Bind(&done);
|
|
}
|
|
|
|
void BranchIfNotSmi(Register reg,
|
|
Label* label,
|
|
JumpDistance distance = kFarJump) {
|
|
testl(reg, Immediate(kSmiTagMask));
|
|
j(NOT_ZERO, label, distance);
|
|
}
|
|
|
|
void BranchIfSmi(Register reg,
|
|
Label* label,
|
|
JumpDistance distance = kFarJump) override {
|
|
testl(reg, Immediate(kSmiTagMask));
|
|
j(ZERO, label, distance);
|
|
}
|
|
|
|
void ArithmeticShiftRightImmediate(Register dst,
|
|
Register src,
|
|
int32_t shift,
|
|
OperandSize sz = kFourBytes) override {
|
|
ASSERT(IsSignedOperand(sz));
|
|
ASSERT((shift >= 0) && (shift < OperandSizeInBits(sz)));
|
|
ExtendValue(dst, src, sz);
|
|
if (shift != 0) {
|
|
sarl(dst, Immediate(shift));
|
|
}
|
|
}
|
|
void ArithmeticShiftRightImmediate(Register reg,
|
|
int32_t shift,
|
|
OperandSize sz = kFourBytes) override {
|
|
ArithmeticShiftRightImmediate(reg, reg, shift, sz);
|
|
}
|
|
void CompareWords(Register reg1,
|
|
Register reg2,
|
|
intptr_t offset,
|
|
Register count,
|
|
Register temp,
|
|
Label* equals) override;
|
|
|
|
void Align(intptr_t alignment, intptr_t offset);
|
|
void Bind(Label* label) override;
|
|
void Jump(Label* label, JumpDistance distance = kFarJump) {
|
|
jmp(label, distance);
|
|
}
|
|
// Unconditional jump to a given address in register.
|
|
void Jump(Register target) { jmp(target); }
|
|
|
|
// Moves one word from the memory at [from] to the memory at [to].
|
|
// Needs a temporary register.
|
|
void MoveMemoryToMemory(Address to, Address from, Register tmp);
|
|
|
|
// Set up a Dart frame on entry with a frame pointer and PC information to
|
|
// enable easy access to the RawInstruction object of code corresponding
|
|
// to this frame.
|
|
// The dart frame layout is as follows:
|
|
// ....
|
|
// ret PC
|
|
// saved EBP <=== EBP
|
|
// pc (used to derive the RawInstruction Object of the dart code)
|
|
// locals space <=== ESP
|
|
// .....
|
|
// This code sets this up with the sequence:
|
|
// pushl ebp
|
|
// movl ebp, esp
|
|
// call L
|
|
// L: <code to adjust saved pc if there is any intrinsification code>
|
|
// .....
|
|
void EnterDartFrame(intptr_t frame_size);
|
|
void LeaveDartFrame();
|
|
|
|
// Set up a Dart frame for a function compiled for on-stack replacement.
|
|
// The frame layout is a normal Dart frame, but the frame is partially set
|
|
// up on entry (it is the frame of the unoptimized code).
|
|
void EnterOsrFrame(intptr_t extra_size);
|
|
|
|
// Set up a stub frame so that the stack traversal code can easily identify
|
|
// a stub frame.
|
|
// The stub frame layout is as follows:
|
|
// ....
|
|
// ret PC
|
|
// saved EBP
|
|
// 0 (used to indicate frame is a stub frame)
|
|
// .....
|
|
// This code sets this up with the sequence:
|
|
// pushl ebp
|
|
// movl ebp, esp
|
|
// pushl immediate(0)
|
|
// .....
|
|
void EnterStubFrame();
|
|
void LeaveStubFrame();
|
|
static constexpr intptr_t kEnterStubFramePushedWords = 2;
|
|
|
|
// Set up a frame for calling a C function.
|
|
// Automatically save the pinned registers in Dart which are not callee-
|
|
// saved in the native calling convention.
|
|
// Use together with CallCFunction.
|
|
void EnterCFrame(intptr_t frame_space);
|
|
void LeaveCFrame();
|
|
|
|
// Instruction pattern from entrypoint is used in dart frame prologs
|
|
// to set up the frame and save a PC which can be used to figure out the
|
|
// RawInstruction object corresponding to the code running in the frame.
|
|
// entrypoint:
|
|
// pushl ebp (size is 1 byte)
|
|
// movl ebp, esp (size is 2 bytes)
|
|
// call L (size is 5 bytes)
|
|
// L:
|
|
static constexpr intptr_t kEntryPointToPcMarkerOffset = 8;
|
|
static intptr_t EntryPointToPcMarkerOffset() {
|
|
return kEntryPointToPcMarkerOffset;
|
|
}
|
|
|
|
// If allocation tracing for |cid| is enabled, will jump to |trace| label,
|
|
// which will allocate in the runtime where tracing occurs.
|
|
void MaybeTraceAllocation(intptr_t cid,
|
|
Label* trace,
|
|
Register temp_reg,
|
|
JumpDistance distance = JumpDistance::kFarJump);
|
|
|
|
void TryAllocateObject(intptr_t cid,
|
|
intptr_t instance_size,
|
|
Label* failure,
|
|
JumpDistance distance,
|
|
Register instance_reg,
|
|
Register temp_reg) override;
|
|
|
|
void TryAllocateArray(intptr_t cid,
|
|
intptr_t instance_size,
|
|
Label* failure,
|
|
JumpDistance distance,
|
|
Register instance,
|
|
Register end_address,
|
|
Register temp);
|
|
|
|
void CheckAllocationCanary(Register top) {
|
|
#if defined(DEBUG)
|
|
Label okay;
|
|
cmpl(Address(top, 0), Immediate(kAllocationCanary));
|
|
j(EQUAL, &okay, Assembler::kNearJump);
|
|
Stop("Allocation canary");
|
|
Bind(&okay);
|
|
#endif
|
|
}
|
|
void WriteAllocationCanary(Register top) {
|
|
#if defined(DEBUG)
|
|
movl(Address(top, 0), Immediate(kAllocationCanary));
|
|
#endif
|
|
}
|
|
|
|
// Copy [size] bytes from [src] address to [dst] address.
|
|
// [size] should be a multiple of word size.
|
|
// Clobbers [src], [dst], [size] and [temp] registers.
|
|
// IA32 requires fixed registers for memory copying:
|
|
// [src] = ESI, [dst] = EDI, [size] = ECX.
|
|
void CopyMemoryWords(Register src,
|
|
Register dst,
|
|
Register size,
|
|
Register temp = kNoRegister);
|
|
|
|
// Debugging and bringup support.
|
|
void Breakpoint() override { int3(); }
|
|
|
|
// Check if the given value is an integer value that can be directly
|
|
// embedded into the code without additional XORing with jit_cookie.
|
|
// We consider 16-bit integers, powers of two and corresponding masks
|
|
// as safe values that can be embedded into the code object.
|
|
static bool IsSafeSmi(const Object& object) {
|
|
if (!target::IsSmi(object)) {
|
|
return false;
|
|
}
|
|
int64_t value;
|
|
if (HasIntegerValue(object, &value)) {
|
|
return Utils::IsInt(16, value) || Utils::IsPowerOfTwo(value) ||
|
|
Utils::IsPowerOfTwo(value + 1);
|
|
}
|
|
return false;
|
|
}
|
|
static bool IsSafe(const Object& object) {
|
|
return !target::IsSmi(object) || IsSafeSmi(object);
|
|
}
|
|
|
|
Object& GetSelfHandle() const { return code_; }
|
|
|
|
void PushCodeObject();
|
|
|
|
private:
|
|
void Alu(int bytes, uint8_t opcode, Register dst, Register src);
|
|
void Alu(uint8_t modrm_opcode, Register dst, const Immediate& imm);
|
|
void Alu(int bytes, uint8_t opcode, Register dst, const Address& src);
|
|
void Alu(int bytes, uint8_t opcode, const Address& dst, Register src);
|
|
void Alu(uint8_t modrm_opcode, const Address& dst, const Immediate& imm);
|
|
|
|
inline void EmitUint8(uint8_t value);
|
|
inline void EmitInt32(int32_t value);
|
|
inline void EmitRegisterOperand(int rm, int reg);
|
|
inline void EmitXmmRegisterOperand(int rm, XmmRegister reg);
|
|
inline void EmitFixup(AssemblerFixup* fixup);
|
|
inline void EmitOperandSizeOverride();
|
|
|
|
void EmitOperand(int rm, const Operand& operand);
|
|
void EmitImmediate(const Immediate& imm);
|
|
void EmitComplex(int rm, const Operand& operand, const Immediate& immediate);
|
|
void EmitLabel(Label* label, intptr_t instruction_size);
|
|
void EmitLabelLink(Label* label);
|
|
void EmitNearLabelLink(Label* label);
|
|
|
|
void EmitGenericShift(int rm, Register reg, const Immediate& imm);
|
|
void EmitGenericShift(int rm, const Operand& operand, Register shifter);
|
|
|
|
int32_t jit_cookie();
|
|
|
|
int32_t jit_cookie_;
|
|
Object& code_;
|
|
|
|
DISALLOW_ALLOCATION();
|
|
DISALLOW_COPY_AND_ASSIGN(Assembler);
|
|
};
|
|
|
|
inline void Assembler::EmitUint8(uint8_t value) {
|
|
buffer_.Emit<uint8_t>(value);
|
|
}
|
|
|
|
inline void Assembler::EmitInt32(int32_t value) {
|
|
buffer_.Emit<int32_t>(value);
|
|
}
|
|
|
|
inline void Assembler::EmitRegisterOperand(int rm, int reg) {
|
|
ASSERT(rm >= 0 && rm < 8);
|
|
buffer_.Emit<uint8_t>(0xC0 + (rm << 3) + reg);
|
|
}
|
|
|
|
inline void Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) {
|
|
EmitRegisterOperand(rm, static_cast<Register>(reg));
|
|
}
|
|
|
|
inline void Assembler::EmitFixup(AssemblerFixup* fixup) {
|
|
buffer_.EmitFixup(fixup);
|
|
}
|
|
|
|
inline void Assembler::EmitOperandSizeOverride() {
|
|
EmitUint8(0x66);
|
|
}
|
|
|
|
} // namespace compiler
|
|
} // namespace dart
|
|
|
|
#endif // RUNTIME_VM_COMPILER_ASSEMBLER_ASSEMBLER_IA32_H_
|