Tess Strickland
b23584eaa0
For non-x86 architectures, these forms directly translate to a
single instruction when possible. On x86 architectures,
XImmediate(dst, src, imm) where X is in {Lsl, ArithmeticShiftRight, And}
can be translated to:
MoveRegister(dst, src);
XImmediate(dst, imm);
in the general case since MoveRegister(dst, src) is a no-op if dst and
src are the same.
Also add versions of these assembler macros that take an OperandSize
and handle 32-bit OperandSizes appropriately on 64-bit architectures.
Ensure the implementation for LslImmediate and
ArithmeticShiftRightImmediate emits no instructions if shift == 0,
dst == src, and OperandSizeInBits(sz) == kBitsPerWord on all
architectures.
-----
Other changes:
Fix ConstantExpression::EmitMoveToLocation on ARM64 to match
other architectures, which allow any word-sized or less unboxed
integer representation.
Fill out ExtendValue on RISCV for previously unimplemented
OperandSizes, using the Zba and Zbb extensions when possible.
-----
TEST=vm/cc/Assembler_AndImmediate vm/cc/Assembler_LslImmediate
vm/cc/Assembler_ArithmeticShiftRightImmediate
Separated out of https://dart-review.googlesource.com/c/sdk/+/378706
for easier debugging/reviewing.
Change-Id: I721f1334784f7011a958ea8af29f0e56c620726c
Cq-Include-Trybots: luci.dart.try:vm-aot-linux-release-simarm_x64-try,vm-aot-linux-debug-x64-try,vm-aot-mac-release-arm64-try,vm-aot-mac-product-arm64-try,vm-aot-linux-product-x64-try,vm-aot-dwarf-linux-product-x64-try,vm-aot-linux-debug-simarm_x64-try,vm-linux-debug-x64-try,vm-mac-debug-arm64-try,vm-mac-release-arm64-try,vm-linux-debug-ia32-try,vm-aot-android-release-arm64c-try,vm-ffi-android-debug-arm64c-try,vm-aot-linux-debug-x64c-try,vm-linux-debug-x64c-try,vm-ffi-qemu-linux-release-arm-try,vm-ffi-qemu-linux-release-riscv64-try
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/386180
Reviewed-by: Alexander Markov <alexmarkov@google.com>
Commit-Queue: Tess Strickland <sstrickl@google.com>
530 lines
24 KiB
C++
530 lines
24 KiB
C++
// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
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// for details. All rights reserved. Use of this source code is governed by a
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// BSD-style license that can be found in the LICENSE file.
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#include <functional>
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#include "vm/compiler/assembler/assembler.h"
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#include "vm/compiler/assembler/assembler_test.h"
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#include "vm/globals.h"
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#include "vm/hash.h"
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#include "vm/os.h"
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#include "vm/random.h"
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#include "vm/simulator.h"
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#include "vm/unit_test.h"
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#include "vm/virtual_memory.h"
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namespace dart {
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namespace compiler {
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ASSEMBLER_TEST_EXTERN(StoreIntoObject);
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} // namespace compiler
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ASSEMBLER_TEST_RUN(StoreIntoObject, test) {
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#define TEST_CODE(value, growable_array, thread) \
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test->Invoke<void, ObjectPtr, ObjectPtr, Thread*>(value, growable_array, \
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thread)
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const Array& old_array = Array::Handle(Array::New(3, Heap::kOld));
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const Array& new_array = Array::Handle(Array::New(3, Heap::kNew));
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const GrowableObjectArray& grow_old_array = GrowableObjectArray::Handle(
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GrowableObjectArray::New(old_array, Heap::kOld));
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const GrowableObjectArray& grow_new_array = GrowableObjectArray::Handle(
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GrowableObjectArray::New(old_array, Heap::kNew));
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Smi& smi = Smi::Handle();
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Thread* thread = Thread::Current();
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EXPECT(old_array.ptr() == grow_old_array.data());
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EXPECT(!thread->StoreBufferContains(grow_old_array.ptr()));
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EXPECT(old_array.ptr() == grow_new_array.data());
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EXPECT(!thread->StoreBufferContains(grow_new_array.ptr()));
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// Store Smis into the old object.
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for (int i = -128; i < 128; i++) {
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smi = Smi::New(i);
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TEST_CODE(smi.ptr(), grow_old_array.ptr(), thread);
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EXPECT(static_cast<CompressedObjectPtr>(smi.ptr()) ==
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static_cast<CompressedObjectPtr>(grow_old_array.data()));
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EXPECT(!thread->StoreBufferContains(grow_old_array.ptr()));
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}
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// Store an old object into the old object.
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TEST_CODE(old_array.ptr(), grow_old_array.ptr(), thread);
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EXPECT(old_array.ptr() == grow_old_array.data());
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EXPECT(!thread->StoreBufferContains(grow_old_array.ptr()));
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// Store a new object into the old object.
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TEST_CODE(new_array.ptr(), grow_old_array.ptr(), thread);
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EXPECT(new_array.ptr() == grow_old_array.data());
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EXPECT(thread->StoreBufferContains(grow_old_array.ptr()));
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// Store a new object into the new object.
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TEST_CODE(new_array.ptr(), grow_new_array.ptr(), thread);
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EXPECT(new_array.ptr() == grow_new_array.data());
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EXPECT(!thread->StoreBufferContains(grow_new_array.ptr()));
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// Store an old object into the new object.
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TEST_CODE(old_array.ptr(), grow_new_array.ptr(), thread);
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EXPECT(old_array.ptr() == grow_new_array.data());
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EXPECT(!thread->StoreBufferContains(grow_new_array.ptr()));
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}
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namespace compiler {
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#define __ assembler->
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ASSEMBLER_TEST_GENERATE(InstantiateTypeArgumentsHashKeys, assembler) {
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#if defined(TARGET_ARCH_IA32)
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const Register kArg1Reg = EAX;
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const Register kArg2Reg = ECX;
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__ movl(kArg1Reg, Address(ESP, 2 * target::kWordSize));
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__ movl(kArg2Reg, Address(ESP, 1 * target::kWordSize));
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#else
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const Register kArg1Reg = CallingConventions::ArgumentRegisters[0];
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const Register kArg2Reg = CallingConventions::ArgumentRegisters[1];
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#endif
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__ CombineHashes(kArg1Reg, kArg2Reg);
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__ FinalizeHash(kArg1Reg, kArg2Reg);
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__ MoveRegister(CallingConventions::kReturnReg, kArg1Reg);
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__ Ret();
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}
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#undef __
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} // namespace compiler
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ASSEMBLER_TEST_RUN(InstantiateTypeArgumentsHashKeys, test) {
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typedef uint32_t (*HashKeysCode)(uword hash, uword other) DART_UNUSED;
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auto hash_test = [&](const Expect& expect, uword hash1, uword hash2) {
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const uint32_t expected = FinalizeHash(CombineHashes(hash1, hash2));
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const uint32_t got = EXECUTE_TEST_CODE_UWORD_UWORD_UINT32(
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HashKeysCode, test->entry(), hash1, hash2);
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if (got == expected) return;
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TextBuffer buffer(128);
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buffer.Printf("For hash1 = %" Pu " and hash2 = %" Pu
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": expected result %u, got result %u",
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hash1, hash2, expected, got);
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expect.Fail("%s", buffer.buffer());
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};
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#define HASH_TEST(hash1, hash2) \
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hash_test(Expect(__FILE__, __LINE__), hash1, hash2)
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const intptr_t kNumRandomTests = 500;
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Random random;
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// First, fixed and random 32 bit tests for all architectures.
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HASH_TEST(1, 1);
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HASH_TEST(10, 20);
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HASH_TEST(20, 10);
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HASH_TEST(kMaxUint16, kMaxUint32 - kMaxUint16);
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HASH_TEST(kMaxUint32 - kMaxUint16, kMaxUint16);
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for (intptr_t i = 0; i < kNumRandomTests; i++) {
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const uword hash1 = random.NextUInt32();
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const uword hash2 = random.NextUInt32();
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HASH_TEST(hash1, hash2);
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}
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#if defined(TARGET_ARCH_IS_64_BIT)
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// Now 64-bit tests on 64-bit architectures.
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HASH_TEST(kMaxUint16, kMaxUint64 - kMaxUint16);
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HASH_TEST(kMaxUint64 - kMaxUint16, kMaxUint16);
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for (intptr_t i = 0; i < kNumRandomTests; i++) {
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const uword hash1 = random.NextUInt64();
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const uword hash2 = random.NextUInt64();
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HASH_TEST(hash1, hash2);
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}
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#endif
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#undef HASH_TEST
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}
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#define __ assembler->
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#if defined(TARGET_ARCH_IA32)
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const Register kArg1Reg = EAX;
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const Register kArg2Reg = ECX;
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#else
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const Register kArg1Reg = CallingConventions::ArgumentRegisters[0];
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const Register kArg2Reg = CallingConventions::ArgumentRegisters[1];
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#endif
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#define LOAD_FROM_BOX_TEST(SIZE, TYPE, VALUE, SAME_REGISTER) \
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ASSEMBLER_TEST_GENERATE(Load##SIZE##FromBoxOrSmi##VALUE##SAME_REGISTER, \
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assembler) { \
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const bool same_register = SAME_REGISTER; \
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\
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const Register src = kArg1Reg; \
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const Register dst = same_register ? src : kArg2Reg; \
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const TYPE value = VALUE; \
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\
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EnterTestFrame(assembler); \
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\
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__ LoadObject(src, Integer::ZoneHandle(Integer::New(value, Heap::kOld))); \
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__ Load##SIZE##FromBoxOrSmi(dst, src); \
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__ MoveRegister(CallingConventions::kReturnReg, dst); \
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\
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LeaveTestFrame(assembler); \
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\
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__ Ret(); \
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} \
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\
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ASSEMBLER_TEST_RUN(Load##SIZE##FromBoxOrSmi##VALUE##SAME_REGISTER, test) { \
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const int64_t res = test->InvokeWithCodeAndThread<int64_t>(); \
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EXPECT_EQ(static_cast<TYPE>(VALUE), static_cast<TYPE>(res)); \
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}
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0, true)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0, false)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 1, true)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 1, false)
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#if defined(TARGET_ARCH_IS_32_BIT)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0x7FFFFFFF, true)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0x7FFFFFFF, false)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0x80000000, true)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0x80000000, false)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0xFFFFFFFF, true)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0xFFFFFFFF, false)
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#else
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0x7FFFFFFFFFFFFFFF, true)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0x7FFFFFFFFFFFFFFF, false)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0x8000000000000000, true)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0x8000000000000000, false)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0xFFFFFFFFFFFFFFFF, true)
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LOAD_FROM_BOX_TEST(Word, intptr_t, 0xFFFFFFFFFFFFFFFF, false)
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#endif
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LOAD_FROM_BOX_TEST(Int32, int32_t, 0, true)
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LOAD_FROM_BOX_TEST(Int32, int32_t, 0, false)
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LOAD_FROM_BOX_TEST(Int32, int32_t, 1, true)
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LOAD_FROM_BOX_TEST(Int32, int32_t, 1, false)
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LOAD_FROM_BOX_TEST(Int32, int32_t, 0x7FFFFFFF, true)
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LOAD_FROM_BOX_TEST(Int32, int32_t, 0x7FFFFFFF, false)
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LOAD_FROM_BOX_TEST(Int32, int32_t, 0x80000000, true)
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LOAD_FROM_BOX_TEST(Int32, int32_t, 0x80000000, false)
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LOAD_FROM_BOX_TEST(Int32, int32_t, 0xFFFFFFFF, true)
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LOAD_FROM_BOX_TEST(Int32, int32_t, 0xFFFFFFFF, false)
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#if !defined(TARGET_ARCH_IS_32_BIT)
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LOAD_FROM_BOX_TEST(Int64, int64_t, 0, true)
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LOAD_FROM_BOX_TEST(Int64, int64_t, 0, false)
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LOAD_FROM_BOX_TEST(Int64, int64_t, 1, true)
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LOAD_FROM_BOX_TEST(Int64, int64_t, 1, false)
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LOAD_FROM_BOX_TEST(Int64, int64_t, 0x7FFFFFFFFFFFFFFF, true)
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LOAD_FROM_BOX_TEST(Int64, int64_t, 0x7FFFFFFFFFFFFFFF, false)
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LOAD_FROM_BOX_TEST(Int64, int64_t, 0x8000000000000000, true)
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LOAD_FROM_BOX_TEST(Int64, int64_t, 0x8000000000000000, false)
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LOAD_FROM_BOX_TEST(Int64, int64_t, 0xFFFFFFFFFFFFFFFF, true)
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LOAD_FROM_BOX_TEST(Int64, int64_t, 0xFFFFFFFFFFFFFFFF, false)
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#endif
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#if defined(TARGET_ARCH_ARM)
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ISOLATE_UNIT_TEST_CASE(Assembler_Regress54621) {
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auto zone = thread->zone();
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const classid_t cid = kTypedDataInt32ArrayCid;
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const intptr_t index_scale = 1;
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const intptr_t kMaxAllowedOffsetForExternal = (2 << 11) - 1;
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auto& smi = Smi::Handle(zone, Smi::New(kMaxAllowedOffsetForExternal));
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bool needs_base;
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EXPECT(compiler::Assembler::AddressCanHoldConstantIndex(
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smi, /*is_load=*/true,
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/*is_external=*/true, cid, index_scale, &needs_base));
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EXPECT(!needs_base);
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EXPECT(compiler::Assembler::AddressCanHoldConstantIndex(
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smi, /*is_load=*/true,
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/*is_external=*/false, cid, index_scale, &needs_base));
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EXPECT(needs_base);
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// Double-checking we're on a boundary of what's allowed.
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smi = Smi::New(kMaxAllowedOffsetForExternal + 1);
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EXPECT(!compiler::Assembler::AddressCanHoldConstantIndex(
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smi, /*is_load=*/true,
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/*is_external=*/false, cid, index_scale));
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EXPECT(!compiler::Assembler::AddressCanHoldConstantIndex(
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smi, /*is_load=*/true,
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/*is_external=*/true, cid, index_scale));
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}
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#endif
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namespace compiler {
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intptr_t RegRegImmTests::ExtendValue(intptr_t value, OperandSize sz) {
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switch (sz) {
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#if defined(TARGET_ARCH_IS_64_BIT)
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case kEightBytes:
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return value; // We only simulate 64-bit architectures on 64-bit.
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#endif
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case kFourBytes:
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return static_cast<int32_t>(value);
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case kUnsignedFourBytes:
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return static_cast<uint32_t>(value);
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default:
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break;
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}
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UNREACHABLE();
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return value;
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}
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intptr_t RegRegImmTests::ZeroExtendValue(intptr_t value, OperandSize sz) {
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if (!Assembler::NeedsSignExtension(sz)) return ExtendValue(value, sz);
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switch (sz) {
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case kFourBytes:
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return ExtendValue(value, kUnsignedFourBytes);
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default:
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break;
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}
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UNREACHABLE();
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return value;
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}
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intptr_t RegRegImmTests::SignExtendValue(intptr_t value, OperandSize sz) {
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if (Assembler::IsSignedOperand(sz)) return ExtendValue(value, sz);
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switch (sz) {
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case kUnsignedFourBytes:
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return ExtendValue(value, kFourBytes);
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default:
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break;
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}
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UNREACHABLE();
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return value;
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}
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void CheckRegRegImmOperation(
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Expect& expect,
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AssemblerTest* test,
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intptr_t rhs,
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OperandSize sz,
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const std::function<intptr_t(intptr_t, intptr_t, OperandSize)>& f) {
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RELEASE_ASSERT(Assembler::OperandSizeInBits(sz) <= target::kBitsPerWord);
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for (size_t i = 0; i < ARRAY_SIZE(kRegRegImmInputs); ++i) {
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auto const input = kRegRegImmInputs[i];
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intptr_t expected = f(input, rhs, sz);
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intptr_t got = test->Invoke<intptr_t, intptr_t>(input);
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#if defined(TARGET_ARCH_IS_32_BIT)
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// In case the test is running on a 64-bit simulator, use static casts to
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// uint32_t (which has the benefit of only printing the lower 32 bits
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// for failures).
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expected = static_cast<uint32_t>(expected);
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got = static_cast<uint32_t>(got);
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#endif
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if (expected != got) {
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expect.Fail("For input %#" Px ": expected %#" Px ", got %#" Px "\n",
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input, expected, got);
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}
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}
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if (expect.failed()) {
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OS::PrintErr("Generated assembly:\n%s\n", test->RelativeDisassembly());
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}
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}
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#if defined(TARGET_ARCH_IA32)
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const Register RegRegImmTests::kInputReg = kNoRegister;
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#else
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const Register RegRegImmTests::kInputReg =
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CallingConventions::ArgumentRegisters[0];
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#endif
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const Register RegRegImmTests::kReturnReg = CallingConventions::kReturnReg;
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#if TARGET_ARCH_IS_32_BIT
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#define FOR_EACH_RHS_AND_SIZE(V) \
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V(0, kFourBytes) \
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V(0, kUnsignedFourBytes) \
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V(1, kFourBytes) \
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V(1, kUnsignedFourBytes) \
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V(0x2E, kFourBytes) \
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V(0x2E, kUnsignedFourBytes) \
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V(kMaxUint8, kFourBytes) \
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V(kMaxUint8, kUnsignedFourBytes) \
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V(0x2E4F, kFourBytes) \
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V(0x2E4F, kUnsignedFourBytes) \
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V(kMaxUint16, kFourBytes) \
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V(kMaxUint16, kUnsignedFourBytes) \
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V(0x2E4F5B3C, kFourBytes) \
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V(0x2E4F5B3C, kUnsignedFourBytes) \
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V(kMaxUint32, kFourBytes) \
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V(kMaxUint32, kUnsignedFourBytes)
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#else
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#define FOR_EACH_RHS_AND_SIZE(V) \
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V(0, kFourBytes) \
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V(0, kUnsignedFourBytes) \
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V(0, kEightBytes) \
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V(1, kFourBytes) \
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V(1, kUnsignedFourBytes) \
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V(1, kEightBytes) \
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V(0x2E, kFourBytes) \
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V(0x2E, kUnsignedFourBytes) \
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V(0x2E, kEightBytes) \
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V(kMaxUint8, kFourBytes) \
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V(kMaxUint8, kUnsignedFourBytes) \
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V(kMaxUint8, kEightBytes) \
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V(0x2E4F, kFourBytes) \
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V(0x2E4F, kUnsignedFourBytes) \
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V(0x2E4F, kEightBytes) \
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V(kMaxUint16, kFourBytes) \
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V(kMaxUint16, kUnsignedFourBytes) \
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V(kMaxUint16, kEightBytes) \
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V(0x2E4F5B3C, kFourBytes) \
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V(0x2E4F5B3C, kUnsignedFourBytes) \
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V(0x2E4F5B3C, kEightBytes) \
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V(kMaxUint32, kFourBytes) \
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V(kMaxUint32, kUnsignedFourBytes) \
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V(kMaxUint32, kEightBytes) \
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V(0x2E4F5B3C9D8716A0, kEightBytes) \
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V(kMaxUint64, kFourBytes) \
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V(kMaxUint64, kUnsignedFourBytes) \
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V(kMaxUint64, kEightBytes)
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#endif
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#if defined(TARGET_ARCH_IA32)
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#define AND_ASSEMBLER_TEST_GENERATE(rhs, sz) \
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ASSEMBLER_TEST_GENERATE(AndImmediate_X_##rhs##_##sz, assembler) { \
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__ movl(RegRegImmTests::kReturnReg, Address(ESP, 4)); \
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__ AndImmediate(RegRegImmTests::kReturnReg, RegRegImmTests::kReturnReg, \
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rhs, sz); \
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__ Ret(); \
|
|
}
|
|
#else
|
|
#define AND_ASSEMBLER_TEST_GENERATE(rhs, sz) \
|
|
ASSEMBLER_TEST_GENERATE(AndImmediate_X_##rhs##_##sz, assembler) { \
|
|
__ AndImmediate(RegRegImmTests::kReturnReg, RegRegImmTests::kInputReg, \
|
|
rhs, sz); \
|
|
__ Ret(); \
|
|
}
|
|
#endif
|
|
|
|
intptr_t RegRegImmTests::And(intptr_t value, intptr_t rhs, OperandSize sz) {
|
|
// On all architectures, the result is zero-extended for non-word-sized sz.
|
|
return ZeroExtendValue(value & rhs, sz);
|
|
}
|
|
|
|
#define AND_ASSEMBLER_TEST_RUN(rhs, sz) \
|
|
ASSEMBLER_TEST_RUN(AndImmediate_X_##rhs##_##sz, test) { \
|
|
dart::Expect expect(__FILE__, __LINE__); \
|
|
CheckRegRegImmOperation(expect, test, rhs, sz, RegRegImmTests::And); \
|
|
}
|
|
|
|
FOR_EACH_RHS_AND_SIZE(AND_ASSEMBLER_TEST_GENERATE)
|
|
FOR_EACH_RHS_AND_SIZE(AND_ASSEMBLER_TEST_RUN)
|
|
|
|
#undef AND_ASSEMBLER_TEST_RUN
|
|
#undef AND_ASSEMBLER_TEST_GENERATE
|
|
#undef FOR_EACH_RHS_AND_SIZE
|
|
|
|
#if TARGET_ARCH_IS_32_BIT
|
|
#define FOR_EACH_SHIFT_AND_SIGNED_SIZE(V) \
|
|
V(0, kFourBytes) \
|
|
V(1, kFourBytes) \
|
|
V(7, kFourBytes) \
|
|
V(15, kFourBytes) \
|
|
V(16, kFourBytes) \
|
|
V(25, kFourBytes) \
|
|
V(31, kFourBytes)
|
|
#else
|
|
#define FOR_EACH_SHIFT_AND_SIGNED_SIZE(V) \
|
|
V(0, kFourBytes) \
|
|
V(0, kEightBytes) \
|
|
V(1, kFourBytes) \
|
|
V(1, kEightBytes) \
|
|
V(7, kFourBytes) \
|
|
V(7, kEightBytes) \
|
|
V(15, kFourBytes) \
|
|
V(15, kEightBytes) \
|
|
V(16, kFourBytes) \
|
|
V(16, kEightBytes) \
|
|
V(25, kFourBytes) \
|
|
V(25, kEightBytes) \
|
|
V(31, kFourBytes) \
|
|
V(31, kEightBytes) \
|
|
V(52, kEightBytes) \
|
|
V(63, kEightBytes)
|
|
#endif
|
|
|
|
#if TARGET_ARCH_IS_32_BIT
|
|
#define FOR_EACH_SHIFT_AND_UNSIGNED_SIZE(V) \
|
|
V(0, kUnsignedFourBytes) \
|
|
V(1, kUnsignedFourBytes) \
|
|
V(7, kUnsignedFourBytes) \
|
|
V(15, kUnsignedFourBytes) \
|
|
V(16, kUnsignedFourBytes) \
|
|
V(25, kUnsignedFourBytes) \
|
|
V(31, kUnsignedFourBytes)
|
|
#else
|
|
#define FOR_EACH_SHIFT_AND_UNSIGNED_SIZE(V) \
|
|
V(0, kUnsignedFourBytes) \
|
|
V(1, kUnsignedFourBytes) \
|
|
V(7, kUnsignedFourBytes) \
|
|
V(15, kUnsignedFourBytes) \
|
|
V(16, kUnsignedFourBytes) \
|
|
V(25, kUnsignedFourBytes) \
|
|
V(31, kUnsignedFourBytes)
|
|
#endif
|
|
|
|
#if defined(TARGET_ARCH_IA32)
|
|
#define LSL_ASSEMBLER_TEST_GENERATE(shift, sz) \
|
|
ASSEMBLER_TEST_GENERATE(LslImmediate_X_##shift##_##sz, assembler) { \
|
|
__ movl(RegRegImmTests::kReturnReg, Address(ESP, 4)); \
|
|
__ LslImmediate(RegRegImmTests::kReturnReg, RegRegImmTests::kReturnReg, \
|
|
shift, sz); \
|
|
__ Ret(); \
|
|
}
|
|
#else
|
|
#define LSL_ASSEMBLER_TEST_GENERATE(shift, sz) \
|
|
ASSEMBLER_TEST_GENERATE(LslImmediate_X_##shift##_##sz, assembler) { \
|
|
__ LslImmediate(RegRegImmTests::kReturnReg, RegRegImmTests::kInputReg, \
|
|
shift, sz); \
|
|
__ Ret(); \
|
|
}
|
|
#endif
|
|
|
|
#define LSL_ASSEMBLER_TEST_RUN(shift, sz) \
|
|
ASSEMBLER_TEST_RUN(LslImmediate_X_##shift##_##sz, test) { \
|
|
dart::Expect expect(__FILE__, __LINE__); \
|
|
CheckRegRegImmOperation(expect, test, shift, sz, RegRegImmTests::Lsl); \
|
|
}
|
|
|
|
FOR_EACH_SHIFT_AND_SIGNED_SIZE(LSL_ASSEMBLER_TEST_GENERATE)
|
|
FOR_EACH_SHIFT_AND_SIGNED_SIZE(LSL_ASSEMBLER_TEST_RUN)
|
|
FOR_EACH_SHIFT_AND_UNSIGNED_SIZE(LSL_ASSEMBLER_TEST_GENERATE)
|
|
FOR_EACH_SHIFT_AND_UNSIGNED_SIZE(LSL_ASSEMBLER_TEST_RUN)
|
|
|
|
#undef LSL_ASSEMBLER_TEST_RUN
|
|
#undef LSL_ASSEMBLER_TEST_GENERATE
|
|
|
|
#if defined(TARGET_ARCH_IA32)
|
|
#define ASR_ASSEMBLER_TEST_GENERATE(shift, sz) \
|
|
ASSEMBLER_TEST_GENERATE(ArithmeticShiftRightImmediate_X_##shift##_##sz, \
|
|
assembler) { \
|
|
if (Assembler::IsSignedOperand(sz)) { \
|
|
__ movl(RegRegImmTests::kReturnReg, Address(ESP, 4)); \
|
|
__ ArithmeticShiftRightImmediate(RegRegImmTests::kReturnReg, \
|
|
RegRegImmTests::kReturnReg, shift, sz); \
|
|
} \
|
|
__ Ret(); \
|
|
}
|
|
#else
|
|
#define ASR_ASSEMBLER_TEST_GENERATE(shift, sz) \
|
|
ASSEMBLER_TEST_GENERATE(ArithmeticShiftRightImmediate_X_##shift##_##sz, \
|
|
assembler) { \
|
|
__ ArithmeticShiftRightImmediate(RegRegImmTests::kReturnReg, \
|
|
RegRegImmTests::kInputReg, shift, sz); \
|
|
__ Ret(); \
|
|
}
|
|
#endif
|
|
|
|
#define ASR_ASSEMBLER_TEST_RUN(shift, sz) \
|
|
ASSEMBLER_TEST_RUN(ArithmeticShiftRightImmediate_X_##shift##_##sz, test) { \
|
|
dart::Expect expect(__FILE__, __LINE__); \
|
|
CheckRegRegImmOperation(expect, test, shift, sz, RegRegImmTests::Asr); \
|
|
}
|
|
|
|
FOR_EACH_SHIFT_AND_SIGNED_SIZE(ASR_ASSEMBLER_TEST_GENERATE)
|
|
FOR_EACH_SHIFT_AND_SIGNED_SIZE(ASR_ASSEMBLER_TEST_RUN)
|
|
|
|
#undef ASR_ASSEMBLER_TEST_RUN
|
|
#undef ASR_ASSEMBLER_TEST_GENERATE
|
|
#undef FOR_EACH_SHIFT_AND_UNSIGNED_SIZE
|
|
#undef FOR_EACH_SHIFT_AND_SIGNED_SIZE
|
|
|
|
} // namespace compiler
|
|
|
|
} // namespace dart
|