depend on the current rounding mode (fixes issue 25900).
Add support for TRUNC.W in assembler, disassembler, and simulator.
Fix disassembler to understand CVT.S.
Remove unused instructions.
Update co19 status file.
R=rmacnak@google.com
Review URL: https://codereview.chromium.org/1765623002 .
Add neg-instruction to the MIPS backend and use it instead of mul with -1.
Fixes the test that requires that identical(nan, -nan) == false.
TEST=language/nan_identical_test
R=zra@google.com
Review URL: https://codereview.chromium.org/1425143003 .
a svc instruction (or hlt instruction on arm64).
The instructions svc and hlt are used in conjunction with a simulator only.
At least, gdb now stops on armv5te when hitting a stop message (no prompt).
Add support for printing stop message in disassembly on mips and arm64.
Clean up various bkpt codes on arm (now similar to arm64 and mips).
R=zra@google.com
Review URL: https://codereview.chromium.org//1097413004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@45363 260f80e4-7a28-3924-810f-c04153c831b5
This change adds a flag --mips-far-branches, which when set causes
relative branches to be converted to absolute branches by determining
the PC, adding the branch offset to it, and using the jr or jalr
instruction to jump if the branch test passes.
This procedure clobbers the assembler temporary TMP, so TMP can no
longer be used in a branch test or in the branch delay slot of a
relative branch. Because TMP can't be used in a branch test, a
new temporary is introduced CMPRES2. This change replaces TMP with
CMPRES1 or another register where TMP can no longer be used.
Tests that were failing due to a too-far relative have the
--mips-far-branches flag set.
R=regis@google.com
Review URL: https://codereview.chromium.org//20369003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25543 260f80e4-7a28-3924-810f-c04153c831b5
- Exposes double precision rather than single precision floating point registers
to architecture generic code. This entails a mechanical change in the assembler
to floating point instructions.
- Adds slti, sltiu instructions for comparison with small immediates, and uses
them in the Branch(Un)Signed* macros.
- Fixes a bug in the intermediate language comparison/branching instructions
caused by using subu for comparison. Now it uses two slt instructions.
- Fixes register use bugs in intermediate language.
- More uses of NULLREG instead of loading Object::null()
R=regis@google.com
Review URL: https://codereview.chromium.org//16022011
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23190 260f80e4-7a28-3924-810f-c04153c831b5
This change backs out an earlier change to the disassemblers that
made them return false if an instruction couldn't be decoded.
This was used in the simulator debuggers for arm and mips to avoid
executing an instruction that couldn't be decoded.
Instead, now when an unknown instruction is encountered in the simulator,
if the simulator is running interactively, we drop into
the debugger, and otherwise die. We detect that a simulator is
running interactively by setting a flag if we enter the debugger
for a user set break point.
Review URL: https://codereview.chromium.org//12903006
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20394 260f80e4-7a28-3924-810f-c04153c831b5
Also includes changes to keep it from aborting unexpectedly.
Among other things, I changed the Disassembler::Disassemble to return false
when the underlying decoder can't decode an instruction. Then,
the MIPS SimulatorDebugger will refuse to step or cont on an instruction
that the Disassembler can't decode.
Review URL: https://codereview.chromium.org//12431016
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19958 260f80e4-7a28-3924-810f-c04153c831b5
Ryan Macnak