depend on the current rounding mode (fixes issue 25900).
Add support for TRUNC.W in assembler, disassembler, and simulator.
Fix disassembler to understand CVT.S.
Remove unused instructions.
Update co19 status file.
R=rmacnak@google.com
Review URL: https://codereview.chromium.org/1765623002 .
Add neg-instruction to the MIPS backend and use it instead of mul with -1.
Fixes the test that requires that identical(nan, -nan) == false.
TEST=language/nan_identical_test
R=zra@google.com
Review URL: https://codereview.chromium.org/1425143003 .
Instead of calling code object directly, call indirectly and
pass the code object in a register. The object pool is then loaded from
the code object. This is another preparation step for making generated code
relocatable.
All non-ia32 platforms:
No entry patching.
ARM:
PC marker (now code object) moves to the same place as on x64 (below saved PP, above saved FP).
R9 is now used as PP, R10 as CODE_REG.
BUG=
R=rmacnak@google.com
Review URL: https://codereview.chromium.org//1192103004 .
Add THR register that caches the current thread in generated code.
Shuffle some registers around as needed to free one up.
Note: Assembler::LoadIsolate now always loads the *current* isolate whenever the code is executed, rather than the isolate in which the code was compiled (no existing code was affected by this slight change in semantics).
Rewrite some ia32 stubs to use one less register, and for some ia32 bigint intrinsics, explicitly save THR (like CTX in the past, see r44699).
Next steps:
- pass current thread rather than isolate in NativeArguments
- ditto for exception handler jump
- migrate fields vm_tag, top_exit_frame_info, etc. to thread
R=srdjan@google.com
Review URL: https://codereview.chromium.org//1156593002
In addition to tracking input and output ranges in the IC-stubs with a Smi fastpath (SmiAdd and SmiSub, currently) this CL also introduces two IC stubs that have no fast-path by still track ranges and update the range feedback.
We are able to distinguish between the following ranges (encoding of the lattice is shown in the parens):
- u-smi (0000)
- smi (0001)
- uint31 (0010)
- int32 (0011)
- uint32 (0100)
- int64 (1xxx) and (x1x1)
BUG=
R=fschneider@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//735543003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42370 260f80e4-7a28-3924-810f-c04153c831b5
This change rewrites the code from the ARM assembler for parsing /proc/cpuinfo on Linux and Android, and collects it into a CpuInfo class that can be used for other architectures as well. This code is in cpuinfo_*.cc. /proc/cpuinfo equivalents are used for Mac and Windows. CpuInfo is used by the VM service to report on the hardware dart is running on. In the future CpuInfo can also be used here to provide more information.
R=iposva@google.com, johnmccutchan@google.com
Review URL: https://codereview.chromium.org//120723003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32468 260f80e4-7a28-3924-810f-c04153c831b5
This change adds a flag --mips-far-branches, which when set causes
relative branches to be converted to absolute branches by determining
the PC, adding the branch offset to it, and using the jr or jalr
instruction to jump if the branch test passes.
This procedure clobbers the assembler temporary TMP, so TMP can no
longer be used in a branch test or in the branch delay slot of a
relative branch. Because TMP can't be used in a branch test, a
new temporary is introduced CMPRES2. This change replaces TMP with
CMPRES1 or another register where TMP can no longer be used.
Tests that were failing due to a too-far relative have the
--mips-far-branches flag set.
R=regis@google.com
Review URL: https://codereview.chromium.org//20369003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25543 260f80e4-7a28-3924-810f-c04153c831b5
- Exposes double precision rather than single precision floating point registers
to architecture generic code. This entails a mechanical change in the assembler
to floating point instructions.
- Adds slti, sltiu instructions for comparison with small immediates, and uses
them in the Branch(Un)Signed* macros.
- Fixes a bug in the intermediate language comparison/branching instructions
caused by using subu for comparison. Now it uses two slt instructions.
- Fixes register use bugs in intermediate language.
- More uses of NULLREG instead of loading Object::null()
R=regis@google.com
Review URL: https://codereview.chromium.org//16022011
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23190 260f80e4-7a28-3924-810f-c04153c831b5
Florian Schneider