Commit Graph

12 Commits

Author SHA1 Message Date
Ryan Macnak 04ba20aa98 [vm] Support RISC-V.
Implements a backend targeting RV32GC and RV64GC, based on Linux standardizing around GC. The assembler is written to make it easy to disable usage of C, but because the sizes of some instruction sequences are compile-time constants, an additional build configuration would need to be defined to make use of it.

The assembler and disassembler cover every RV32/64GC instruction. The simulator covers all instructions except accessing CSRs and the floating point state accessible through such, include accrued exceptions and dynamic rounding mode.

Quirks:
  - RISC-V is a compare-and-branch architecture, but some existing "architecture-independent" parts of the Dart compiler assume a condition code architecture. To avoid rewriting these parts, we use a peephole in the assembler to map to compare-and-branch. See Assembler::BranchIf. Luckily nothing depended on taking multiple branches on the same condition code set.
  - There are no hardware overflow checks, so we must use Hacker's Delight style software checks. Often these are very cheap: if the sign of one operand is known, a single branch is needed.
  - The ranges of RISC-V branches and jumps are such that we use 3 levels of generation for forward branches, instead of the 2 levels of near and far branches used on ARM[64]. Nearly all code is handled by the first two levels with 20-bits of range, with enormous regex matchers triggering the third level that uses aupic+jalr to get 32-bits of range.
  - For PC-relative calls in AOT, we always generate auipc+jalr pairs with 32-bits of range, so we never generate trampolines.
  - Only a subset of registers are available in some compressed instructions, so we assign the most popular uses to these registers. In particular, THR, TMP[2], CODE and PP. This has the effect of assigning CODE and PP to volatile registers in the C calling convention, whereas they are assigned preserved registers on the other architectures. As on ARM64, PP is untagged; this is so short indices can be accessed with a compressed instruction.
  - There are no push or pop instructions, so combining pushes and pops is preferred so we can update SP once.
  - The C calling convention has a strongly aligned stack, but unlike on ARM64 we don't need to use an alternate stack pointer. The author ensured language was added to the RISC-V psABI making the OS responsible for realigning the stack pointer for signal handlers, allowing Dart to leave the stack pointer misaligned from the C calling convention's point of view until a foreign call.
  - We don't bother with the link register tracking done on ARM[64]. Instead we make use of an alternate link register to avoid inline spilling in the write barrier.

Unimplemented:
 - non-trivial FFI cases
 - Compressed pointers - No intention to implement.
 - Unboxed SIMD - We might make use of the V extension registers when the V extension is ratified.
 - BigInt intrinsics

TEST=existing tests for IL level, new tests for assembler/disassembler/simulator
Bug: https://github.com/dart-lang/sdk/issues/38587
Bug: https://github.com/dart-lang/sdk/issues/48164
Change-Id: I991d1df4be5bf55efec5371b767b332d37dfa3e0
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/217289
Reviewed-by: Alexander Markov <alexmarkov@google.com>
Reviewed-by: Daco Harkes <dacoharkes@google.com>
Reviewed-by: Slava Egorov <vegorov@google.com>
Commit-Queue: Ryan Macnak <rmacnak@google.com>
2022-01-20 00:57:57 +00:00
Samir Jindel c885bdde1d [vm] DBC is obsolete. Remove dead code.
Change-Id: Ica33af158cca53c8e951e4b2582de83660e8a60d
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/121851
Commit-Queue: Samir Jindel <sjindel@google.com>
Reviewed-by: Martin Kustermann <kustermann@google.com>
2019-10-27 18:18:29 +00:00
Zachary Anderson 6cd8a79078 VM: Re-format to use at most one newline between functions
R=asiva@google.com

Review-Url: https://codereview.chromium.org/2974233002 .
2017-07-13 08:08:37 -07:00
Zachary Anderson ac16656161 Remove MIPS support
R=asiva@google.com

Review-Url: https://codereview.chromium.org/2858623002 .
2017-06-22 08:49:22 -07:00
Ben Konyi f2fd150ea0 Added new type of unit test, RAW_UNIT_TEST_CASE, which is used for tests that can be flaky if run while the VM is alive. Tests created using the RAW_UNIT_TEST_CASE macro will run after the VM has shutdown to avoid having any worker threads contaminating the test results.
BUG=
R=johnmccutchan@google.com

Review-Url: https://codereview.chromium.org/2666133002 .
2017-01-31 15:16:38 -08:00
Zachary Anderson a1bcf051d8 clang-format runtime/vm
R=johnmccutchan@google.com

Review URL: https://codereview.chromium.org/2481873005 .
2016-11-08 13:54:47 -08:00
Vyacheslav Egorov ee0f608ce4 Dart Byte Code interpreter.
This version is Clang/GCC only and does not support Windows because it uses computed goto's.

Only unoptimized mode is supported.

Architecture is described in constants_dbc.h and stack_frame_dbc.h.

R=fschneider@google.com, zra@google.com

Review URL: https://codereview.chromium.org/1858283002 .
2016-04-18 23:02:01 +02:00
zra@google.com 2fe51715e5 Begins work on ARM64, first assembler test.
Most new code is in constants_arm64.h and
{assembler,disassembler,simulator}_arm64.{h,cc}

The rest of the CL just #def's out tests, modifies status files,
and adds UNIMPLEMENTED functions, etc.

R=regis@google.com

Review URL: https://codereview.chromium.org//221133002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@34654 260f80e4-7a28-3924-810f-c04153c831b5
2014-04-02 17:39:32 +00:00
iposva@google.com c3c942407b Fix dartbug.com/10415:
- Append 'on "$os_$arch"' to the version string on the VM.

Review URL: https://codereview.chromium.org//14593004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22452 260f80e4-7a28-3924-810f-c04153c831b5
2013-05-07 07:59:03 +00:00
regis@google.com be9555b2e1 Mofify vm code base so that it can be built for --arch=simmips.
Review URL: https://codereview.chromium.org//12018023

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@17321 260f80e4-7a28-3924-810f-c04153c831b5
2013-01-18 21:46:58 +00:00
sgjesse@google.com bf67f24098 Move assert.h/assert.cc from runtime/vm to runtime/platform
The purpose of this change is twofold:

1. Source in the bin directory can now use the same assertions as
   source in the vm directory. The ASSERT macro used by the code
   in runtime/bin was just defined to use assert from the standard
   C library.
2. Moving other implementation parts from runtime/vm to
   runtime/platform (e.g. classes Monitor and Mutex) for sharing
   between runtime/bin and runtime/vm will be easier as these
   implementations rely on these assertion macros.

Created two gypi files for the platform directory. One for the
headers and one for the source. The source one is only included
when building the VM library and will be present in libdart.a
when the dart executable is linked.

All the code for asserts is still in the dart namespace.

Also re-arranged the order of includes to be alphabetically in
the files touched.

R=ager@google.com, iposva@google.com

BUG=
TEST=

Review URL: http://codereview.chromium.org//9189003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@3335 260f80e4-7a28-3924-810f-c04153c831b5
2012-01-16 12:28:10 +00:00
dgrove@google.com 4c0f559d23 Initial checkin.
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@15 260f80e4-7a28-3924-810f-c04153c831b5
2011-10-05 05:20:07 +00:00