Add neg-instruction to the MIPS backend and use it instead of mul with -1.
Fixes the test that requires that identical(nan, -nan) == false.
TEST=language/nan_identical_test
R=zra@google.com
Review URL: https://codereview.chromium.org/1425143003 .
On ia32 this is int3(). This also makes precompiled instruction snapshots
deterministic (to be precise the empty space due to alignment), and not depending
on the address of the null object at snapshot creation time.
BUG=
R=rmacnak@google.com
Review URL: https://codereview.chromium.org//1367973002 .
Instead of calling code object directly, call indirectly and
pass the code object in a register. The object pool is then loaded from
the code object. This is another preparation step for making generated code
relocatable.
All non-ia32 platforms:
No entry patching.
ARM:
PC marker (now code object) moves to the same place as on x64 (below saved PP, above saved FP).
R9 is now used as PP, R10 as CODE_REG.
BUG=
R=rmacnak@google.com
Review URL: https://codereview.chromium.org//1192103004 .
Remove unused branch/call macro instructions from the assembler.
Setup a frame and pool pointer when invoking leaf runtime functions (in the
deoptimzation stub and store-buffer update stub).
BUG=
R=rmacnak@google.com
Review URL: https://codereview.chromium.org//1314883002 .
This makes the code in the code generator independent from how stubs
are actually called (i.e. directly embedding the target address, or
indirectly by loading the target address from the code object).
BUG=
R=rmacnak@google.com
Review URL: https://codereview.chromium.org//1270803003 .
This allows to make the last explicitly named stubs shared between isolates.
When sharing code stubs, we can't do patching at their entry anymore.
Therefore, I had to remove patching support of the array allocation stub.
Is this a functionality we want to keep?
The change is mostly performance-neutral because optimized code has an inlined fast
path for array allocation and only uses the stub for the slow-case.
The only isolate-specific stubs left are object allocation stubs which are
associated with their Class are per-isolate.
Since this CL removes any isolate-specific stubs from StubCode, it becomes AllStatic.
BUG=
R=koda@google.com
Review URL: https://codereview.chromium.org//1247783002 .
Make context allocation stub shared between isolates.
The fast-path used in optimized code still has isolate-specific
addresses inlined for performance reasons.
Common functions are moved into class_table.h/.cc.
This is a preparation for adding an isolate-independent version of the
allocation code and allocation tracking code.
BUG=
R=johnmccutchan@google.com
Review URL: https://codereview.chromium.org//1241863002 .
- Track whether class allocation should be traced in existing ClassHeapStats structure.
- Emit compare and branch at top of ::TryAllocate
These changes appear to be performance neutral.
An alternative approach is to deoptimize all code that inlined allocations for a specific class. I do not think this is a good approach because we will spoil the water- allocations that aren't occurring in the (optimized steady state) running program will appear in the allocation profile. This will make the data much less actionable bordering on misleading. The approach used in this CL will guarantee the allocation profile aligns with the actual running program.
R=regis@google.com, srdjan@google.com
Review URL: https://codereview.chromium.org//1213013002 .
Also, set up a stub frame with object pool loaded in all stubs on those
platforms. This is a preparation step to making code relocatable.
ia32 is not affected because there is no object pool.
BUG=
R=srdjan@google.com
Review URL: https://codereview.chromium.org//1189573004.
This adds meta-information to object pool entries to allow storing
untagged immediates or code addresses (ExternalLabel) directly.
This eliminates the need to generate extra code to preserve the LSB
when storing immediates as smis (x64, arm64).
BUG=
Review URL: https://codereview.chromium.org//1175523002.
Instead of using RawObject* as keys, use Object*. Using handles eliminates any assumption
about the underlying GC implementation (e.g. requiring that old objects don't move).
Remove special handling of null_object by making HashMap more generic and
allowing the trait to specify the value used to indicate an empty element.
The goal is to use one unified, efficient implementation of the constant
pool on all architectures that require one (x64, arm64, mips).
R=vegorov@google.com, zra@google.com
Review URL: https://codereview.chromium.org//848703002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42901 260f80e4-7a28-3924-810f-c04153c831b5
In addition to tracking input and output ranges in the IC-stubs with a Smi fastpath (SmiAdd and SmiSub, currently) this CL also introduces two IC stubs that have no fast-path by still track ranges and update the range feedback.
We are able to distinguish between the following ranges (encoding of the lattice is shown in the parens):
- u-smi (0000)
- smi (0001)
- uint31 (0010)
- int32 (0011)
- uint32 (0100)
- int64 (1xxx) and (x1x1)
BUG=
R=fschneider@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//735543003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42370 260f80e4-7a28-3924-810f-c04153c831b5
Since Register is an enum type, it is automatically
coerced to integer types when passed as a parameter to
functions expecting an integer argument. This change
expands the use of Immediate and Operand wrappers
for Assembler instructions and macros to avoid this
automatic coercion.
I've also added dummy constructors to Address and
FieldAddress classes to address the same problem,
but in a way that does not increase verbosity,
since Address and FieldAddress are much more
prevalent in the code.
A cleaner solution would involve making Register
no longer coercable to integer types, but this
would likely require many changes to the Assemblers.
R=regis@google.com
Review URL: https://codereview.chromium.org//593363003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40905 260f80e4-7a28-3924-810f-c04153c831b5
First steps towards general pretenuring support.
* Generalize Heap::Top/EndAddress.
* Add testing flag to exercise new code paths.
* Also update the slow-case runtime calls, to ensure a fresh block will be allocated in old.
Next steps are general invalidation of the generated code and adding a policy that doesn't blow up the store buffers), and freelist allocation.
Review URL: https://codereview.chromium.org//578443003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40530 260f80e4-7a28-3924-810f-c04153c831b5
Introduce base classes for binary and unary integer operations and move all shared logic (e.g. canonicalization) into these classes.
Start removing special cases dispatch from instructions patterns - it goes into Canonicalization pass.
Start removing duplication between instruction patterns where meaningful and possible.
Cleanup the notion of truncation in the operations: is_truncating implies !can_overflow, not the other way around.
BUG=
R=johnmccutchan@google.com, srdjan@google.com
Review URL: https://codereview.chromium.org//564843002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40375 260f80e4-7a28-3924-810f-c04153c831b5
Previous implementation changed input representation depending on the propagated type of the value which violated assumptions made by SelectRepresentations phase.
Instead of using tagged/mint input require unboxed Int32/Uint32 input and insert explicit truncating unboxing when building StoreIndexed operation in the optimizer. This also leads to strictly better code and opens possibilities for further optimizations.
Implement Int32/Uint32 representation support on all platforms. This includes boxing, unboxing and unboxed converter operations.
Merge BoxInt32/BoxUint32 and UnboxInt32/UnboxUint32 instruction sequences to minimize duplication.
Improve instruction sequences by utilizing CARRY flag set by smi untagging where possible (ARM, ia32, x86).
Enable all tests that were disabled by r40078, r40079.
BUG=http://dartbug.com/20875R=fschneider@google.com, johnmccutchan@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//552303005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40143 260f80e4-7a28-3924-810f-c04153c831b5
1. Deopts on division when neither vfp nor idiv are present.
In a subsequent CL, I can add a leaf runtime call for this.
2. Uses a different PC read offset in STR and STM instructions.
On ARMv5 and earlier, the PC read offset is 8 except in STR
and STM instructions, where it is implementation defined. On
lego mindstorm it is 12. This requires changing
kEntryPointToPcMarkerOffset to be a function.
3. Uses a dummy struct to compute the size of a compressed
pc descriptor to avoid alignment issues. sizeof(PcDescriptorRec)
is 16 on ia32 and arm. Subtracting sizeof(int16_t) gives 14,
which creates alignment problems on ARM, i.e. poor performance on
ARMv6 and later, and wrong results on ARMv5 and earlier.
R=regis@google.com
Review URL: https://codereview.chromium.org//467103005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@39250 260f80e4-7a28-3924-810f-c04153c831b5
This change generate inline code for context allocation and makes
the stores to initialize the parent pointer and the context variables
explicit in the optimized flow graph. This allows dead store elimination
to eliminate those stores.
Before, we only had inlined context allocation for ia32.
Furthermore:
* Added an assertion that the exit label of slow-path code
is bound when emitting deferred code. This used to cause random crashes
if forgotten.
* Fixed a bug in allocation stats on ARM.
BUG=dartbug.com/17238
R=srdjan@google.com
Review URL: https://codereview.chromium.org//346823003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@39202 260f80e4-7a28-3924-810f-c04153c831b5
On these architectures it's preferable to load Scavenger address into the register and then access top/end fields through this register instead of loading addresses of those fields as immediates --- which takes either two instructions or a memory load through a pool pointer.
Cleanup boxing slow-paths in the optimizing compiler. We had tons of duplicated code that was essentially doing the same thing.
BUG=
R=johnmccutchan@google.com, regis@google.com
Review URL: https://codereview.chromium.org//410333003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38539 260f80e4-7a28-3924-810f-c04153c831b5
Change executable pages to be read/execute but not writable by default.
All pages are made temporarily writable just before a full GC, because both
the mark and sweep phases write to the pages. When allocating in a page and
when patching code, the pages are made temporarily writable.
The order of allocation of Code and Instructions objects is changed so that
a GC will not occur after Instructions is allocated. (A full GC would
render the Instructions unwritable.) A scoped object is used to make memory
protection simpler.
Original CL: https://codereview.chromium.org/106593002/
I added a cc test that is expected to crash.
R=srdjan@google.com
Review URL: https://codereview.chromium.org//136563002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32493 260f80e4-7a28-3924-810f-c04153c831b5
This change rewrites the code from the ARM assembler for parsing /proc/cpuinfo on Linux and Android, and collects it into a CpuInfo class that can be used for other architectures as well. This code is in cpuinfo_*.cc. /proc/cpuinfo equivalents are used for Mac and Windows. CpuInfo is used by the VM service to report on the hardware dart is running on. In the future CpuInfo can also be used here to provide more information.
R=iposva@google.com, johnmccutchan@google.com
Review URL: https://codereview.chromium.org//120723003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32468 260f80e4-7a28-3924-810f-c04153c831b5
Florian Schneider