Add THR register that caches the current thread in generated code.
Shuffle some registers around as needed to free one up.
Note: Assembler::LoadIsolate now always loads the *current* isolate whenever the code is executed, rather than the isolate in which the code was compiled (no existing code was affected by this slight change in semantics).
Rewrite some ia32 stubs to use one less register, and for some ia32 bigint intrinsics, explicitly save THR (like CTX in the past, see r44699).
Next steps:
- pass current thread rather than isolate in NativeArguments
- ditto for exception handler jump
- migrate fields vm_tag, top_exit_frame_info, etc. to thread
R=srdjan@google.com
Review URL: https://codereview.chromium.org//1156593002
This CL:
- Adds SupportsHardwareDivision() to FlowGraphCompiler.
In FlowGraphOptimizer, if SupportsHardwareDivision()
is false, Smi and Mint division operations are not
inlined.
- Reduces the supported addressing modes for ldrd, strd.
For ARMv6 and up, the address only needs to be 4-byte
aligned, for ARMv5TE and below the address must be
8-byte aligned. So, on ARMv5TE, we can split these
each into two instructions, which is easier to do if
the addressing modes are restricted to base + offset,
which is all we were using anyway.
- Uses the smull instruction on ARMv5TE and ARMv6. I don't
remember why it was disabled, and the docs say
it is supported. Verified working on ARMv5TE hardware.
- Fixes a bug in OSR frame entry caused by the
difference between the PC read offset in store vs.
other instructions.
- Fixes assembler tests that have a float return for
targets without vfp.
R=regis@google.com
Review URL: https://codereview.chromium.org//1043943002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@44788 260f80e4-7a28-3924-810f-c04153c831b5
In addition to tracking input and output ranges in the IC-stubs with a Smi fastpath (SmiAdd and SmiSub, currently) this CL also introduces two IC stubs that have no fast-path by still track ranges and update the range feedback.
We are able to distinguish between the following ranges (encoding of the lattice is shown in the parens):
- u-smi (0000)
- smi (0001)
- uint31 (0010)
- int32 (0011)
- uint32 (0100)
- int64 (1xxx) and (x1x1)
BUG=
R=fschneider@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//735543003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42370 260f80e4-7a28-3924-810f-c04153c831b5
Since Register is an enum type, it is automatically
coerced to integer types when passed as a parameter to
functions expecting an integer argument. This change
expands the use of Immediate and Operand wrappers
for Assembler instructions and macros to avoid this
automatic coercion.
I've also added dummy constructors to Address and
FieldAddress classes to address the same problem,
but in a way that does not increase verbosity,
since Address and FieldAddress are much more
prevalent in the code.
A cleaner solution would involve making Register
no longer coercable to integer types, but this
would likely require many changes to the Assemblers.
R=regis@google.com
Review URL: https://codereview.chromium.org//593363003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40905 260f80e4-7a28-3924-810f-c04153c831b5
Changes:
* Register allocator now allocates GPRs for kUnboxedMint.
* Register allocator supports for SameAsFirstInput for register pairs.
* Register allocator properly handles register pairs in environment uses and materialization uses.
* BoxInteger updated on IA32/ARM.
* UnboxInteger updated on IA32/ARM.
* BinaryMintOp updated on IA32/ARM.
* ShiftMintOp updated on IA32/ARM.
* UnaryMintOp updated on IA32/ARM.
* RelationalOp updated on IA32/ARM.
* EqualityCompare updated on IA32/ARM.
* LoadIndexed and StoreIndexed updated on IA32/ARM.
* New Deopt instructions added.
* Update live_registers when an instruction has a fixed register input and a call on the slow path.
* Improve printing of register pairs in flow graph.
* Do not assume live registers in slow paths contain tagged values.
* LiveRange pairs for kUnboxedMint definitions marked as kUntagged representation (reduces stack usage).
* Live register spilling on ARM uses same register order as stack map encoding.
* Spill slots containing tagged and untagged are segregated.
* Print stack maps when printing live ranges with safe points.
* Print allocated spill slot when printing live ranges.
Status:
* IA32 completed. All tests are passing.
* ARM completed. All tests passing.
R=fschneider@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//252333002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@36468 260f80e4-7a28-3924-810f-c04153c831b5
mls, mla, umull, smull, etc. are not implemented on
all ARMv6's. This change works around them. For
mls and mla, we just use two instructions. smull
was used to check for overflow in mul, so we have
to do that manually. For umlal in the Random
intrinsic, we just fall through for now, though in
principal it wouldn't be hard to emulate.
R=regis@google.com
Review URL: https://codereview.chromium.org//255273003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@35550 260f80e4-7a28-3924-810f-c04153c831b5
This change rewrites the code from the ARM assembler for parsing /proc/cpuinfo on Linux and Android, and collects it into a CpuInfo class that can be used for other architectures as well. This code is in cpuinfo_*.cc. /proc/cpuinfo equivalents are used for Mac and Windows. CpuInfo is used by the VM service to report on the hardware dart is running on. In the future CpuInfo can also be used here to provide more information.
R=iposva@google.com, johnmccutchan@google.com
Review URL: https://codereview.chromium.org//120723003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32468 260f80e4-7a28-3924-810f-c04153c831b5
Ryan Macnak