i.e. #ifndef VM_WHATEVER -> #ifndef RUNTIME_VM_WHATEVER
This lets us remove a hack from the PRESUBMIT.py script that existed
for reasons that are no longer valid, and sets us up to add some
presubmit checks for the GN build.
R=asiva@google.com, rmacnak@google.com
Review URL: https://codereview.chromium.org/2450713004 .
The catch entry block has all locals in fixed locations
(Rj) where j = kNumberOfRegisters - i for parameter i.
This means we reserve a range of DBC registers at the top-end of the frame.
Those registers are blocked for general allocation to avoid any overlap
with the rest of the registers that are allocated from the bottom.
Each optimized frame with a try-catch will be kNumberOfRegisters wide.
BUG=
R=vegorov@google.com
Review URL: https://codereview.chromium.org/2388093003 .
Most of the infrastructure is fixed to work with DBC stack layout:
- register allocator allocates DBC registers with the limitation that we allocate only 20 registers and bail out if anything needs spilling (there is no use implementing spilling on DBC because registers are memory locations themselves). We should be able to bump number of CPU registers on DBC up to 256 but this requires major surgery in some parts - so I postponed this;
- lazy deoptimization is implemented, eager deoptimization is not - because we don't emit any code that actually requires it. it's a minor change to support it once we have a target;
- stack scanning respects stack maps built by registers allocator;
We bailout from all unsupported instructions.
R=zra@google.com
Review URL: https://codereview.chromium.org/1992963002 .
This change makes CTX available by not caching the current
context while in Dart code. Instead the current context
is held in a local variable (:saved_current_context_var) and
is passed as argument in CTX at calls.
This also simplifies a lot of code in the debugger: As a result,
Isolate::top_context is not needed anymore since the current context
can always be extracted from a Dart frame.
R=vegorov@google.com
Review URL: https://codereview.chromium.org//678763004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@41422 260f80e4-7a28-3924-810f-c04153c831b5
We were violating sorting at instructions that use the same value as both fixed register input and an unallocated one producing a list that contained use at P, followed by a use at P-1.
This would later cause a problem when we split live-range at P-1 and spill [..., P-1) prefix.
Use at P-1 would be attributed to unspilled part of the range leading to completely incorrect parallel move at P-1: [rx <- S+X, ry <- rx], where rx - is the aforementioned fixed register and ry is a register selected for an unallocated use of the value.
R=srdjan@google.com
BUG=
Review URL: https://codereview.chromium.org//601103004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40681 260f80e4-7a28-3924-810f-c04153c831b5
The way it was implemented did not always work for phis for live ranges extending past the loop, because the hint itself stayed uncoverted until after register allocation inside the loop was completed.
For the loop like this:
f() {
var x = 1.0, y = 2.0;
for (var i = 0; i < 100; i++) x += y;
return x;
}
That used to generate:
loop:
cmp ecx,0xc8
jnl ->exit
mov xmm3, xmm2
addsd xmm3, xmm1
mov xmm2, xmm3
add ecx,0x2
jmp ->loop
With this change we generate:
loop:
cmp ecx,0xc8
jnl ->exit
addsd xmm2,xmm1
add ecx,0x2
jmp ->loop
R=fschneider@google.com
BUG=
Review URL: https://codereview.chromium.org//556453006
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40024 260f80e4-7a28-3924-810f-c04153c831b5
This avoids treating spill slot associated with the definition live during GC as
it will only be filled in after definition's code is fully executed.
Additionally this makes output register dead for GC inside the definiton itself
which is something we used to guarantee manually by removing it from the
live_registers set before calling on the slow path.
BUG=
R=fschneider@google.com
Review URL: https://codereview.chromium.org//375693004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@38059 260f80e4-7a28-3924-810f-c04153c831b5
Changes:
* Register allocator now allocates GPRs for kUnboxedMint.
* Register allocator supports for SameAsFirstInput for register pairs.
* Register allocator properly handles register pairs in environment uses and materialization uses.
* BoxInteger updated on IA32/ARM.
* UnboxInteger updated on IA32/ARM.
* BinaryMintOp updated on IA32/ARM.
* ShiftMintOp updated on IA32/ARM.
* UnaryMintOp updated on IA32/ARM.
* RelationalOp updated on IA32/ARM.
* EqualityCompare updated on IA32/ARM.
* LoadIndexed and StoreIndexed updated on IA32/ARM.
* New Deopt instructions added.
* Update live_registers when an instruction has a fixed register input and a call on the slow path.
* Improve printing of register pairs in flow graph.
* Do not assume live registers in slow paths contain tagged values.
* LiveRange pairs for kUnboxedMint definitions marked as kUntagged representation (reduces stack usage).
* Live register spilling on ARM uses same register order as stack map encoding.
* Spill slots containing tagged and untagged are segregated.
* Print stack maps when printing live ranges with safe points.
* Print allocated spill slot when printing live ranges.
Status:
* IA32 completed. All tests are passing.
* ARM completed. All tests passing.
R=fschneider@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//252333002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@36468 260f80e4-7a28-3924-810f-c04153c831b5
- Adds a PairLocation type (Location is still a single word but now has two tags one for constants and one for pairs).
- New representations: kPairOfTagged & kPairOfUnboxedDouble.
- Register allocator uses second SSA index for Definitions that use two registers.
- Fix LiveRange shape for kWritableRegister inputs.
- Updated MergedMathInstr that returns a kPairOfTagged or kPairOfUnboxedDouble (depending on the merged math kind).
- A new instruction (ExtractNthOutput) for extracting a single register from an instruction that has a output register pair.
Open issues that need to be addressed in a follow up CL:
- Adjust PhiInstr and handling of PhiInstr in the register allocator to work with output pairs (once unboxed mints are in GPRs).
R=fschneider@google.com, srdjan@google.com
Review URL: https://codereview.chromium.org//215363004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@34833 260f80e4-7a28-3924-810f-c04153c831b5
This is a first step towards fully optimizing try-catch-finally.
At a catch entry, all local variables and parameters are
expected at a fixed stack location. There is a list of
initial definitions at the catch entry block, similar to
the initial definitions at graph entry.
Inside every try-block there is a special prologue code before each
call (instruction that may throw) inside the try-block. This prologue
is similar to a parallel move instruction: It moves all locals+parameters
to the locations expected by the catch-entry block. The stack frame
is extended with the corresponding number of fixed slots right below
the normal spill slots.
Every function containing try-catch has additional compiler-
generated local variables to pass the context, the exception and
the stack trace.
Variable liveness analysis is adapted to treat locals inside try{} blocks
specially: Every call has an implicit LoadLocal of every local variable.
This CL uses a safe approximiation of liveness which can be optimized further.
Current restrictions which are planned for future CLs:
* No inlining inside try-blocks.
* No inlining of functions containing try-catch.
* No try-finally yet.
R=kmillikin@google.com
Review URL: https://codereview.chromium.org//14682020
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22615 260f80e4-7a28-3924-810f-c04153c831b5
AllocationSinking pass discovers non-escaping allocations that have no input uses other than uses in the stores into its own fields.
Every environment use of such allocation is replaced by a state snapshot (MaterializeObject instruction) that describes the state of each initialized field in the object. State snapshots are computed through an additional round of load-forwarding.
Once snapshots are computed allocations are removed from the graph.
MaterializeObject instructions are not compiled into native code but produce deoptimization instructions instead that describe how object should be materialized at deoptimization.
Deoptimization instructions now follow the following format:
[mat obj #1]...[mat obj #N][ret addr][... mat arguments ...][... real frames ...]
- the prefix describes each object to materialize on deopt via kMaterializeObject instruction;
- actual values that are needed for materialization are emited as a part of bottom-most stack frame. This is done to simplify implementation: they need to be discoverable by a GC during materialization phase. At the end of deoptimization they will be removed from the stack;
- normal stack slots can refer to materialized objects via kMaterializedObjectRef instruction.
Additionally this change contains fixes in load-forwarding that are needed to guarantee that all artificial LoadField instructions inserted during AllocationSinking are correctly replaced with actual values.
Limitations of the current implementation:
- can't eliminate allocations that flow into phis but otherwise don't actually escape;
- can't sink allocations out of loops;
- allocation with type arguments are not handled.
R=regis@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//14935005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22485 260f80e4-7a28-3924-810f-c04153c831b5
Remove representation from location. Presence of representation in location encoding was violating the invariant that unequal locations must be disjoint (where equality for locations is defined in terms of bitwise equality of their encoding). This could lead ParallelMoveResolver to treat XMM1 containing unboxed double as unequal location to XMM1 containing unboxed mint, which is obviously incorrect.
For similar reason eliminate kFloat32x4StackSlot and kUint32x4StackSlot distinction is eliminated and both are replaced with kQuadStackSlot. Register allocator now guarantees that no kQuadStackSlot occupies the same space as any other kDoubleStackSlot. This also shrinks optimized stack when only doubles are used (but might lead to a higher stack utilization when a mixture of doubles and quads is used).
Implement allocation of scratch Cpu and Xmm registers for ParallelMoveResolver. This also allows to remove push(eax)/pop(eax) pairs when resolving memory-memory cycles on ia32.
BUG=dart:9710
Review URL: https://codereview.chromium.org//13801014
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21148 260f80e4-7a28-3924-810f-c04153c831b5
This CL removes optimized access for scalarlist, and only the new TypedData classes
are optimized. I changed the runtime libraries core and math to use typedData
instead of scalarlist (Uint16List is used in StringBuffer, Uint32List by Math.random).
Instead of using LoadIndexed for internal and external arrays,
split external loads into a load of the backing store and a load
of the element.
v3 <- LoadIndexed(v1, index)
becomes
v2 <- LoadUntagged(v1, ExternalTypedData::data_offset)
v3 <- LoadIndexed(v2, index);
For this I introduce two new representations in the IL:
kUntagged (for values that hold a untagged pointer) and
kNoRepresentation (for instructions accept any input
representation)
Deoptimization does not need to know about kUntagged
since these values can never occur in the environment.
Also with this change:
* fix COMPILE_ASSERT and use it in one place.
* Cleanup IL printer output of deopt ids.
Review URL: https://codereview.chromium.org//12871010
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20198 260f80e4-7a28-3924-810f-c04153c831b5
Previously we removed dead phis late, in the register allocator. This
change removes them as soon as they are discovered to be dead and packs the
phi array to squeeze out NULLs. This speeds iteration but doesn't save
space because the phi array is zone-allocated.
The PhiIterator is used everywhere to iterate phis except a few places that
need to know the phi index (e.g., SSA construction, phi elimination).
R=vegorov@google.com
Review URL: https://codereview.chromium.org//12340108
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19206 260f80e4-7a28-3924-810f-c04153c831b5
This CL adds AND, OR, XOR and == operations on unboxed 64-bit integers
(aka. mints).
Unboxed mints are stored in xmm registers. Each xmm register location
has an additional bit to keep track of its value representation.
Unboxed mints are materialized on the heap on deoptmization in the same way as
unboxed doubles.
The SSE instructions used are available on all CPUs that support SSE 4.1.
Review URL: https://codereview.chromium.org//10968059
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@13112 260f80e4-7a28-3924-810f-c04153c831b5
Add a stack bitmap to the location summaries for calls that are GC
safepoints. The bitmap covers the spill slots. The register
allocator collects these bitmaps into a list and then marks live
pointer values during register allocation. When emitting code for a
call, a heap-allocated stackmap is built.
BUG=
Review URL: https://chromiumcodereview.appspot.com//10831261
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@10618 260f80e4-7a28-3924-810f-c04153c831b5
Bugs fixed in register allocator:
- incorrect assertions in SplitAt;
- allocation finger should not cache positions that are owned by a sibling after split;
- UpdateFreeUntil should allow evicting live range with vreg 0;
- values expected in fixed locations should not cause an interference at the instruction itself, they can be evicted if need arises;
Bug fixed in deoptimization:
- parallel move resolver uses push/pop to free a scratch register for memory to memory moves, when using it for deoptimization we need to ensure that those push/pops do not interfere with actual moves;
R=srdjan@google.com
BUG=
Review URL: https://chromiumcodereview.appspot.com//10824165
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@10287 260f80e4-7a28-3924-810f-c04153c831b5
Zachary Anderson