This CL:
- Adds SupportsHardwareDivision() to FlowGraphCompiler.
In FlowGraphOptimizer, if SupportsHardwareDivision()
is false, Smi and Mint division operations are not
inlined.
- Reduces the supported addressing modes for ldrd, strd.
For ARMv6 and up, the address only needs to be 4-byte
aligned, for ARMv5TE and below the address must be
8-byte aligned. So, on ARMv5TE, we can split these
each into two instructions, which is easier to do if
the addressing modes are restricted to base + offset,
which is all we were using anyway.
- Uses the smull instruction on ARMv5TE and ARMv6. I don't
remember why it was disabled, and the docs say
it is supported. Verified working on ARMv5TE hardware.
- Fixes a bug in OSR frame entry caused by the
difference between the PC read offset in store vs.
other instructions.
- Fixes assembler tests that have a float return for
targets without vfp.
R=regis@google.com
Review URL: https://codereview.chromium.org//1043943002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@44788 260f80e4-7a28-3924-810f-c04153c831b5
Refactor all remaning cases where the current zone is used through new(Isolate*) and remove this interface.
Removing this interface is needed to move towards multiple threads per isolate, and also makes the caller more aware of the scope of the zone used, reducing the risk of use-after-free.
Make the current thread and the stack zone created around native/runtime entries directly available in their body, saving an indirection (and optimized away if unused).
R=iposva@google.com
Review URL: https://codereview.chromium.org//982873004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@44541 260f80e4-7a28-3924-810f-c04153c831b5