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48 Commits

Author SHA1 Message Date
Ryan Macnak e3f791b00e Fix ARM and MIPS builds for gcc 4.9.2. 
R=zra@google.com

Review URL: https://codereview.chromium.org/2489953003 .
 2016-11-10 11:13:13 -08:00
Zachary Anderson a1bcf051d8 clang-format runtime/vm 
R=johnmccutchan@google.com

Review URL: https://codereview.chromium.org/2481873005 .
 2016-11-08 13:54:47 -08:00
Ryan Macnak 26245de7a5 Support unaligned integer loads on ARM and MIPS. 
Fixes SDK build with SIMARM/SIMARM64/SIMMIPS.

R=johnmccutchan@google.com

Review URL: https://codereview.chromium.org/2452453002 .
 2016-10-31 17:41:53 -07:00
Florian Schneider ab4490e5bf VM: Remove collection of unused range feedback. 
We can always put it back if the optimizer makes use of it.
It's a lot of extra code that is unused. Therefore, remove it for now.

BUG=
R=vegorov@google.com

Review URL: https://codereview.chromium.org/2132933003 .
 2016-07-11 06:46:50 -07:00
Regis Crelier cb0f9e98ea Fix typo in newly introduced mips assembly tests. 
R=rmacnak@google.com

Review URL: https://codereview.chromium.org/1767133002 .
 2016-03-07 11:34:46 -08:00
Regis Crelier 6219753e18 Use TRUNC.W instead of CVT.W on mips to convert from double to int as to not 
depend on the current rounding mode (fixes issue 25900).
Add support for TRUNC.W in assembler, disassembler, and simulator.
Fix disassembler to understand CVT.S.
Remove unused instructions.
Update co19 status file.

R=rmacnak@google.com

Review URL: https://codereview.chromium.org/1765623002 .
 2016-03-03 17:05:09 -08:00
Ryan Macnak cb210e3997 Enable concurrent sweep on MIPS and ARM64. 
Compare ARM from commit f78517a5ba.

Closes #25651.

R=zra@google.com

Review URL: https://codereview.chromium.org/1722013002 .
 2016-02-29 09:23:25 -08:00
Florian Schneider 64261cbb9d VM: Improve and fix double negation on MIPS. 
Add neg-instruction to the MIPS backend and use it instead of mul with -1.

Fixes the test that requires that identical(nan, -nan) == false.

TEST=language/nan_identical_test
R=zra@google.com

Review URL: https://codereview.chromium.org/1425143003 .
 2015-10-29 22:34:46 +01:00
Florian Schneider bac82e2592 VM: New calling convention for generated code. 
Instead of calling code object directly, call indirectly and
pass the code object in a register. The object pool is then loaded from
the code object. This is another preparation step for making generated code
relocatable.

All non-ia32 platforms:
No entry patching.

ARM:
PC marker (now code object) moves to the same place as on x64 (below saved PP, above saved FP).
R9 is now used as PP, R10 as CODE_REG.

BUG=
R=koda@google.com, rmacnak@google.com

Committed: https://github.com/dart-lang/sdk/commit/1d343e5a7b75168fb6c9f86b64c55173cdbdc9b2

Review URL: https://codereview.chromium.org//1192103004 .
 2015-09-19 13:21:09 +02:00
Florian Schneider 7af7a2db87 Revert "VM: New calling convention for generated code." 
This reverts commit 1d343e5a7b.

Because of Windows test failures.

BUG=
TBR=whesse@google.com

Review URL: https://codereview.chromium.org//1343373003 .
 2015-09-16 13:46:05 +02:00
Florian Schneider 1d343e5a7b VM: New calling convention for generated code. 
Instead of calling code object directly, call indirectly and
pass the code object in a register. The object pool is then loaded from
the code object. This is another preparation step for making generated code
relocatable.

All non-ia32 platforms:
No entry patching.

ARM:
PC marker (now code object) moves to the same place as on x64 (below saved PP, above saved FP).
R9 is now used as PP, R10 as CODE_REG.

BUG=
R=rmacnak@google.com

Review URL: https://codereview.chromium.org//1192103004 .
 2015-09-16 13:05:58 +02:00
Florian Schneider 28c5ba6bdc VM: Simplify assembler test by removing unused parameter. 
No need to pass a Context into assembler tests.

BUG=
R=srdjan@google.com

Review URL: https://codereview.chromium.org//1272223002 .
 2015-08-06 10:24:14 +02:00
Daniel Andersson fd890f4097 Cache current thread in a reserved register and use it in LoadIsolate 
Add THR register that caches the current thread in generated code.
Shuffle some registers around as needed to free one up.

Note: Assembler::LoadIsolate now always loads the *current* isolate whenever the code is executed, rather than the isolate in which the code was compiled (no existing code was affected by this slight change in semantics).

Rewrite some ia32 stubs to use one less register, and for some ia32 bigint intrinsics, explicitly save THR (like CTX in the past, see r44699).

Next steps:
- pass current thread rather than isolate in NativeArguments
- ditto for exception handler jump
- migrate fields vm_tag, top_exit_frame_info, etc. to thread

R=srdjan@google.com

Review URL: https://codereview.chromium.org//1156593002
 2015-05-26 13:46:12 -07:00
zra@google.com d077e38107 Fix MIPS assembler test. 
R=regis@google.com

Review URL: https://codereview.chromium.org//791953003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42746 260f80e4-7a28-3924-810f-c04153c831b5
 2015-01-09 17:59:11 +00:00
vegorov@google.com aa48bd4759 Range feedback for arithmetic operations. 
In addition to tracking input and output ranges in the IC-stubs with a Smi fastpath (SmiAdd and SmiSub, currently) this CL also introduces two IC stubs that have no fast-path by still track ranges and update the range feedback.

We are able to distinguish between the following ranges (encoding of the lattice is shown in the parens):

- u-smi  (0000)
- smi    (0001)
- uint31 (0010)
- int32  (0011)
- uint32 (0100)
- int64  (1xxx) and (x1x1)

BUG=
R=fschneider@google.com, srdjan@google.com, zra@google.com

Review URL: https://codereview.chromium.org//735543003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42370 260f80e4-7a28-3924-810f-c04153c831b5
 2014-12-15 18:48:15 +00:00
regis@google.com d353b001a5 Fix SLTIU instruction in MIPS assembler, disassembler, and simulator. 
Add regression assembler test.

R=zra@google.com

Review URL: https://codereview.chromium.org//802023002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42362 260f80e4-7a28-3924-810f-c04153c831b5
 2014-12-15 16:46:04 +00:00
regis@google.com 6fd6dd93d4 Fix build (gcc is happy, this must be clang complaining). 
Review URL: https://codereview.chromium.org//721513002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@41678 260f80e4-7a28-3924-810f-c04153c831b5
 2014-11-11 23:05:34 +00:00
regis@google.com eea98ee4df Fix unsigned multiplication in MIPS simulator (add assembler regression test). 
Fix breakpoint handling in MIPS simulator.
Fix potential overflow in Bigint_sqrAdd intrinsic on ARM.

R=zra@google.com

Review URL: https://codereview.chromium.org//713993002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@41674 260f80e4-7a28-3924-810f-c04153c831b5
 2014-11-11 22:28:58 +00:00
rmacnak@google.com d72161731e Satisfy new -Wunused-local-typedefs in gcc 4.8 in the simulators. 
R=zra@google.com

Review URL: https://codereview.chromium.org//356233003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@37823 260f80e4-7a28-3924-810f-c04153c831b5
 2014-06-30 17:02:58 +00:00
zra@google.com 3eba8b8f77 Avoids MIPS32r2 instructions on MIPS32. 
Adds necessary feature detection to tell the difference.

R=regis@google.com

Review URL: https://codereview.chromium.org//211363007

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@34391 260f80e4-7a28-3924-810f-c04153c831b5
 2014-03-25 21:30:51 +00:00
zra@google.com fd366da1cf Updates refactoring of CPU feature detection 
with fix that uses cpuid for Intel/Linux.

R=asiva@google.com

Review URL: https://codereview.chromium.org//136303012

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32980 260f80e4-7a28-3924-810f-c04153c831b5
 2014-02-24 19:28:30 +00:00
zra@google.com 3693beeb6b Reverts refactoring of CPU feature detection for 
assertion failure in Dartium.

R=asiva@google.com

Review URL: https://codereview.chromium.org//142663004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32560 260f80e4-7a28-3924-810f-c04153c831b5
 2014-02-11 16:05:43 +00:00
zra@google.com 6f2096face Refactors some CPU feature detection into new class CpuInfo, and uses new information in VM service. 
This change rewrites the code from the ARM assembler for parsing /proc/cpuinfo on Linux and Android, and collects it into a CpuInfo class that can be used for other architectures as well. This code is in cpuinfo_*.cc. /proc/cpuinfo equivalents are used for Mac and Windows. CpuInfo is used by the VM service to report on the hardware dart is running on. In the future CpuInfo can also be used here to provide more information.

R=iposva@google.com, johnmccutchan@google.com

Review URL: https://codereview.chromium.org//120723003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@32468 260f80e4-7a28-3924-810f-c04153c831b5
 2014-02-08 22:27:27 +00:00
zra@google.com 3fd0e585d3 Fixes bug in far branches on MIPS. 
Also increases test coverage of far branches on
ARM and MIPS.

R=regis@google.com

Review URL: https://codereview.chromium.org//107293008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@31024 260f80e4-7a28-3924-810f-c04153c831b5
 2013-12-10 16:43:06 +00:00
zra@google.com dad3270d95 Implements far branch targets for MIPS. 
This change adds a flag --mips-far-branches, which when set causes
relative branches to be converted to absolute branches by determining
the PC, adding the branch offset to it, and using the jr or jalr
instruction to jump if the branch test passes.

This procedure clobbers the assembler temporary TMP, so TMP can no
longer be used in a branch test or in the branch delay slot of a
relative branch. Because TMP can't be used in a branch test, a
new temporary is introduced CMPRES2. This change replaces TMP with
CMPRES1 or another register where TMP can no longer be used.

Tests that were failing due to a too-far relative have the
--mips-far-branches flag set.

R=regis@google.com

Review URL: https://codereview.chromium.org//20369003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25543 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-26 23:30:32 +00:00
zra@google.com 8edda78ccc Enables more tests for SIMMIPS. 
. Fixes register allocation bugs
. Implements float <-> double conversion in assembler and simulator.
. Fixes floating point argument passing for simarm and simmips,
  and floating point return for simarm, and adjusts tests to match.

R=regis@google.com

Review URL: https://codereview.chromium.org//17502002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24365 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-24 20:16:16 +00:00
zra@google.com 488b20bd7e Fixes buggy FPU tests for MIPS hardware. 
R=regis@google.com

Review URL: https://codereview.chromium.org//15874005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24152 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-18 16:47:43 +00:00
zra@google.com e846af4128 Implements intrinsics for MIPS. 
Also, adds the MADD, MADDU, MTLO, MTHI instructions
to the MIPS simulator, assembler, and disassembler.

R=regis@google.com

Review URL: https://codereview.chromium.org//16272004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23489 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-31 21:03:41 +00:00
zra@google.com 354b204cf0 Enables optimization on MIPS 
- Exposes double precision rather than single precision floating point registers
  to architecture generic code. This entails a mechanical change in the assembler
  to floating point instructions.
- Adds slti, sltiu instructions for comparison with small immediates, and uses
  them in the Branch(Un)Signed* macros.
- Fixes a bug in the intermediate language comparison/branching instructions
  caused by using subu for comparison. Now it uses two slt instructions.
- Fixes register use bugs in intermediate language.
- More uses of NULLREG instead of loading Object::null()

R=regis@google.com

Review URL: https://codereview.chromium.org//16022011

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23190 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-24 23:45:41 +00:00
zra@google.com b350781cad Impelemnts some FPU arithmetic function for the MIPS simulator, assembler, disassembler. 
R=regis@google.com

Review URL: https://codereview.chromium.org//15038008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22818 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-16 21:18:04 +00:00
zra@google.com 18268541b0 Implements int to double conversion instructions for MIPS simulator, assembler, disassembler. 
R=regis@google.com

Review URL: https://codereview.chromium.org//15144004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22763 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-15 23:51:17 +00:00
zra@google.com 144def4ee3 Implements FPU compare and branching for MIPS simulator, assembler, disassembler. 
R=regis@google.com

Review URL: https://codereview.chromium.org//14672037

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22752 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-15 18:37:47 +00:00
zra@google.com 3c10f6b796 On MIPS, keeps Object::null() in a register. 
On MIPS, we have a lot of registers, and we don't use very many of them.
This change removes the second temporary register TMP2, and instead
dedicates a register to holding Object::null(), which is used frequently
for comparisons, etc..

Also, uses branch delay slot when leaving a dart frame and returning.

R=regis@google.com

Review URL: https://codereview.chromium.org//14854010

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22331 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-02 17:53:34 +00:00
zra@google.com 64d10ad4e4 Implements write barrier on MIPS. 
Review URL: https://codereview.chromium.org//13925024

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21532 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-16 00:25:03 +00:00
zra@google.com e8f86c5d3a Adds support for UseDartApi vm test on MIPS. 
Also, adds:
- xori instruction,
- SubuDetectOverflow (like AdduDetectOverflow).
Review URL: https://codereview.chromium.org//13884017

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21396 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-12 22:20:32 +00:00
zra@google.com 1349cb1fea Adds some floating point instructions to MIPS simulator, assembler, disassembler. 
Review URL: https://codereview.chromium.org//14206002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21376 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-12 17:25:38 +00:00
zra@google.com cae56d75ed Introduces a second temporary register for MIPS assembler macros. 
- Also, adds macros for comparisons followed by branches, and uses them.
Review URL: https://codereview.chromium.org//13483018

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21118 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-08 22:04:27 +00:00
zra@google.com d5be052e40 Adds macros to the MIPS assembler for detecting overflow. 
Review URL: https://codereview.chromium.org//13722022

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21085 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-08 16:51:12 +00:00
zra@google.com fd72ee418a Implements optional parameter handling in MIPS vm. 
- Deocdes ic data and argument descriptor.
- Removes SUB instruction from assembler and disassembler.
Review URL: https://codereview.chromium.org//13474009

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20895 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-03 21:43:52 +00:00
zra@google.com 007c830756 Adds branch instructions and labels to the MIPS simulator, assembler, disassembler. 
Review URL: https://codereview.chromium.org//12634030

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20419 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-22 21:37:10 +00:00
zra@google.com 2bdc772122 Adds MIPS SPECIAL instructions to simulator, assembler, debugger. 
Review URL: https://codereview.chromium.org//12837009

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20321 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-21 15:50:31 +00:00
zra@google.com ad8004569d Adds MIPS instructions to simulator, assembler, disassembler 
ins - bitfield insert
ext - bitfield extract
l{b,bu,h,hu,w} - load byte, unsigned byte, etc.
s{b,h,w} - store byte, halfword, word
Review URL: https://codereview.chromium.org//12519007

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19819 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-11 20:50:50 +00:00
zra@google.com 6699610946 Adds a few MIPS arithmetic instructions to the simulator, assembler, disassembler 
Review URL: https://codereview.chromium.org//12545024

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19730 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-08 21:47:03 +00:00
iposva@google.com 0308a45996 - Allow the use of branch delay slots. 
Review URL: https://codereview.chromium.org//12623002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19669 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-08 07:25:19 +00:00
iposva@google.com f507e542de - Add a skeleton MIPS assembler, disassembler and simulator. 
- Remove unused fields and methods from ARM simulator.
- Remove unused 5th parameter from Simulator::Call.
Review URL: https://codereview.chromium.org//12541003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19606 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-07 11:04:27 +00:00
regis@google.com 8c44be4313 Add support for object pool that will be used on ARM and MIPS architectures. 
Modify code patching infrastructure to accept code object, which is necessary to
get to the object pool containing patchable target addresses.
Modify assembler test infrastructure to provide associated code object.
Review URL: https://codereview.chromium.org//12260026

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18604 260f80e4-7a28-3924-810f-c04153c831b5
 2013-02-15 23:55:31 +00:00
regis@google.com 5675b85979 Generate first ARM assembler test and execute (simulate) it. 
RFC: First draft showing how generated ARM code accesses GC'ed objects and
accesses patched call targets.
Review URL: https://codereview.chromium.org//12224024

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18200 260f80e4-7a28-3924-810f-c04153c831b5
 2013-02-07 00:55:47 +00:00
regis@google.com 0bf36986ec Add test skeletons for arm and mips. 
Review URL: https://codereview.chromium.org//11929037

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@17330 260f80e4-7a28-3924-810f-c04153c831b5
 2013-01-18 23:46:48 +00:00