i.e. #ifndef VM_WHATEVER -> #ifndef RUNTIME_VM_WHATEVER
This lets us remove a hack from the PRESUBMIT.py script that existed
for reasons that are no longer valid, and sets us up to add some
presubmit checks for the GN build.
R=asiva@google.com, rmacnak@google.com
Review URL: https://codereview.chromium.org/2450713004 .
The call sequence is very similar to a classic IC call, except the guarded class and the target are loaded indirectly from the constant pool instead of as immediates. In the monomorphic case, we call directly to the expected target with a class check in the callee. In the unlinked, polymorphic and megamorphic cases, we call a stub; these case are now call-through instead of call-and-return.
Every code, except stubs involved in switchable calls, includes the class check sequence at the beginning. So we now distinguish between a checked and an unchecked entry point. Generated code except the switchable call continues to use the unchecked entry point.
PC offsets are calculated relative to the beginning of the instruction stream, rather than either entry point.
BUG=
R=fschneider@google.com
Review URL: https://codereview.chromium.org/2226893002 .
1. Make CheckArrayBoundInstr also check the index for smi. This allows easy replacement
of the deoptimizing checks with the slow-path checks in the precompiler.
2. Add GenericCheckBoundInstr which has a slow-path attached for
handling check failures.
BUG=
R=vegorov@google.com
Review URL: https://codereview.chromium.org/2149023002 .
Independently patchable entries are not required for debugging because breakpoints are only added to unoptimized code, nor for deopt because deopt patches the instruction stream and not the object pool.
Future work: Reduce the static call table from (pc offset, function, code) triples to (pc offset, function or allocation stub) pairs.
precompiled dart2js arm 20747140 -> 20674954 (-0.34%)
R=fschneider@google.com
Review URL: https://codereview.chromium.org/1713853003 .
On ia32 this is int3(). This also makes precompiled instruction snapshots
deterministic (to be precise the empty space due to alignment), and not depending
on the address of the null object at snapshot creation time.
BUG=
R=rmacnak@google.com
Review URL: https://codereview.chromium.org//1367973002 .
Instead of calling code object directly, call indirectly and
pass the code object in a register. The object pool is then loaded from
the code object. This is another preparation step for making generated code
relocatable.
All non-ia32 platforms:
No entry patching.
ARM:
PC marker (now code object) moves to the same place as on x64 (below saved PP, above saved FP).
R9 is now used as PP, R10 as CODE_REG.
BUG=
R=rmacnak@google.com
Review URL: https://codereview.chromium.org//1192103004 .
Remove unused branch/call macro instructions from the assembler.
Setup a frame and pool pointer when invoking leaf runtime functions (in the
deoptimzation stub and store-buffer update stub).
BUG=
R=rmacnak@google.com
Review URL: https://codereview.chromium.org//1314883002 .
This makes the code in the code generator independent from how stubs
are actually called (i.e. directly embedding the target address, or
indirectly by loading the target address from the code object).
BUG=
R=rmacnak@google.com
Review URL: https://codereview.chromium.org//1270803003 .
This allows to make the last explicitly named stubs shared between isolates.
When sharing code stubs, we can't do patching at their entry anymore.
Therefore, I had to remove patching support of the array allocation stub.
Is this a functionality we want to keep?
The change is mostly performance-neutral because optimized code has an inlined fast
path for array allocation and only uses the stub for the slow-case.
The only isolate-specific stubs left are object allocation stubs which are
associated with their Class are per-isolate.
Since this CL removes any isolate-specific stubs from StubCode, it becomes AllStatic.
BUG=
R=koda@google.com
Review URL: https://codereview.chromium.org//1247783002 .
Make context allocation stub shared between isolates.
The fast-path used in optimized code still has isolate-specific
addresses inlined for performance reasons.
Common functions are moved into class_table.h/.cc.
This is a preparation for adding an isolate-independent version of the
allocation code and allocation tracking code.
BUG=
R=johnmccutchan@google.com
Review URL: https://codereview.chromium.org//1241863002 .
- Track whether class allocation should be traced in existing ClassHeapStats structure.
- Emit compare and branch at top of ::TryAllocate
These changes appear to be performance neutral.
An alternative approach is to deoptimize all code that inlined allocations for a specific class. I do not think this is a good approach because we will spoil the water- allocations that aren't occurring in the (optimized steady state) running program will appear in the allocation profile. This will make the data much less actionable bordering on misleading. The approach used in this CL will guarantee the allocation profile aligns with the actual running program.
R=regis@google.com, srdjan@google.com
Review URL: https://codereview.chromium.org//1213013002 .
Also, set up a stub frame with object pool loaded in all stubs on those
platforms. This is a preparation step to making code relocatable.
ia32 is not affected because there is no object pool.
BUG=
R=srdjan@google.com
Review URL: https://codereview.chromium.org//1189573004.
This adds meta-information to object pool entries to allow storing
untagged immediates or code addresses (ExternalLabel) directly.
This eliminates the need to generate extra code to preserve the LSB
when storing immediates as smis (x64, arm64).
BUG=
Review URL: https://codereview.chromium.org//1175523002.
a svc instruction (or hlt instruction on arm64).
The instructions svc and hlt are used in conjunction with a simulator only.
At least, gdb now stops on armv5te when hitting a stop message (no prompt).
Add support for printing stop message in disassembly on mips and arm64.
Clean up various bkpt codes on arm (now similar to arm64 and mips).
R=zra@google.com
Review URL: https://codereview.chromium.org//1097413004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@45363 260f80e4-7a28-3924-810f-c04153c831b5
This CL:
- Adds SupportsHardwareDivision() to FlowGraphCompiler.
In FlowGraphOptimizer, if SupportsHardwareDivision()
is false, Smi and Mint division operations are not
inlined.
- Reduces the supported addressing modes for ldrd, strd.
For ARMv6 and up, the address only needs to be 4-byte
aligned, for ARMv5TE and below the address must be
8-byte aligned. So, on ARMv5TE, we can split these
each into two instructions, which is easier to do if
the addressing modes are restricted to base + offset,
which is all we were using anyway.
- Uses the smull instruction on ARMv5TE and ARMv6. I don't
remember why it was disabled, and the docs say
it is supported. Verified working on ARMv5TE hardware.
- Fixes a bug in OSR frame entry caused by the
difference between the PC read offset in store vs.
other instructions.
- Fixes assembler tests that have a float return for
targets without vfp.
R=regis@google.com
Review URL: https://codereview.chromium.org//1043943002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@44788 260f80e4-7a28-3924-810f-c04153c831b5
Instead of using RawObject* as keys, use Object*. Using handles eliminates any assumption
about the underlying GC implementation (e.g. requiring that old objects don't move).
Remove special handling of null_object by making HashMap more generic and
allowing the trait to specify the value used to indicate an empty element.
The goal is to use one unified, efficient implementation of the constant
pool on all architectures that require one (x64, arm64, mips).
R=vegorov@google.com, zra@google.com
Review URL: https://codereview.chromium.org//848703002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42901 260f80e4-7a28-3924-810f-c04153c831b5
In addition to tracking input and output ranges in the IC-stubs with a Smi fastpath (SmiAdd and SmiSub, currently) this CL also introduces two IC stubs that have no fast-path by still track ranges and update the range feedback.
We are able to distinguish between the following ranges (encoding of the lattice is shown in the parens):
- u-smi (0000)
- smi (0001)
- uint31 (0010)
- int32 (0011)
- uint32 (0100)
- int64 (1xxx) and (x1x1)
BUG=
R=fschneider@google.com, srdjan@google.com, zra@google.com
Review URL: https://codereview.chromium.org//735543003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@42370 260f80e4-7a28-3924-810f-c04153c831b5
Zachary Anderson