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57 Commits

Author SHA1 Message Date
zra@google.com 3fd0e585d3 Fixes bug in far branches on MIPS. 
Also increases test coverage of far branches on
ARM and MIPS.

R=regis@google.com

Review URL: https://codereview.chromium.org//107293008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@31024 260f80e4-7a28-3924-810f-c04153c831b5
 2013-12-10 16:43:06 +00:00
asiva@google.com c0ddb83c3b ARM and MIPS changes which correspond to the initial change submitted in 
https://codereview.chromium.org/63093003/

R=regis@google.com, zra@google.com

Review URL: https://codereview.chromium.org//62953014

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@30124 260f80e4-7a28-3924-810f-c04153c831b5
 2013-11-08 19:40:07 +00:00
fschneider@google.com aa789a7b27 Merge (x & y) == 0 pattern to emit a single test instruction. 
This is based on a previous uncommitted CL by vegorov@
(https://codereview.chromium.org/14251023/).

It is rebased and fixes a bug in the MIPS implementation: BranchOnCondition
requires the comparison result in fixed registers CMPRES1/CMPRES2.

Remove register alias TMP1 (=TMP) and CMPRES (=CMPRES1). It is confusing to
have them around and easy to forget that they are actually the same.

R=srdjan@google.com, zra@google.com

Review URL: https://codereview.chromium.org//59613005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@29966 260f80e4-7a28-3924-810f-c04153c831b5
 2013-11-06 12:13:29 +00:00
zra@google.com ca82c461a0 Impelments IfThenElse instruction for ARM and MIPS. 
R=fschneider@google.com

Review URL: https://codereview.chromium.org//58003003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@29933 260f80e4-7a28-3924-810f-c04153c831b5
 2013-11-05 20:45:25 +00:00
kmillikin@google.com de1519525c Reapply "Do not directly load smi constants larger than a 16 bit..." 
Reapply "Do not directly load smi constants larger than a 16 bit payload on
ia32" with a bugfix.  The predicate Assembler::IsSafeSmi incorrectly
returned true for non-smis on non-ia32 platforms.

Original summary: Instead of emitting a large smi constant directly as an
immediate, xor the smi with a random 32-bit cookie at compile time, emit
code to move that into a register and then to xor the register with the
cookie.

Original codereview: https://codereview.chromium.org/48743002/

R=fschneider@google.com

Review URL: https://codereview.chromium.org//51333006

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@29533 260f80e4-7a28-3924-810f-c04153c831b5
 2013-10-30 11:38:39 +00:00
whesse@google.com 0729948569 Revert "Do not directly load smi constants larger than a 16 bit payload on ia32." 
There is an assertion failure on debug VM tests.

BUG=
R=fschneider@google.com

Review URL: https://codereview.chromium.org//46873004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@29458 260f80e4-7a28-3924-810f-c04153c831b5
 2013-10-29 16:49:42 +00:00
kmillikin@google.com adf6560e82 Do not directly load smi constants larger than a 16 bit payload on ia32. 
Instead of emitting a large smi constant directly as an immediate, xor the
smi with a random 32-bit cookie at compile time, emit code to move that into
a register and then to xor the register with the cookie.

1. In unoptimized code constants are always loaded into a register in
   ConstantInstr::EmitNativeCode.  Change it to load safely.

2. In optimized code constants loaded into a register for use by an
   instruction are loaded by ParallelMoveResolver::EmitMove.  Change it to
   load safely.

3. In optimized code some instructions allow constants as inputs.  These are
   reflected with an input location of Location::RegisterOrConstant (or
   similar) or else Location::Constant.  For the former allocate a register
   if the constant is unsafe, and for the latter check for safety before
   allowing the constant input.

BUG=https://code.google.com/p/dart/issues/detail?id=1742
R=iposva@google.com, srdjan@google.com

Review URL: https://codereview.chromium.org//48743002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@29439 260f80e4-7a28-3924-810f-c04153c831b5
 2013-10-29 12:19:12 +00:00
srdjan@google.com 3a8252f90d Cleanups: int -> intptr_t for "array" lengths, memory sizes. 
R=asiva@google.com

Review URL: https://codereview.chromium.org//26294002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@28324 260f80e4-7a28-3924-810f-c04153c831b5
 2013-10-07 20:19:37 +00:00
zra@google.com e65e9e1564 Better handling of zero in compare and branch for MIPS. 
R=regis@google.com

Review URL: https://codereview.chromium.org//23537030

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@27362 260f80e4-7a28-3924-810f-c04153c831b5
 2013-09-10 23:46:09 +00:00
regis@google.com 8171570100 Fix the previously ineffective assert checking the number of arguments passed to 
a runtime entry in the VM.

R=asiva@google.com

Review URL: https://codereview.chromium.org//23672011

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@26826 260f80e4-7a28-3924-810f-c04153c831b5
 2013-08-28 23:07:14 +00:00
zra@google.com fa2ad38a31 Enables per-function far-branches for ARM and MIPS. 
R=regis@google.com, srdjan@google.com

Review URL: https://codereview.chromium.org//21363003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25723 260f80e4-7a28-3924-810f-c04153c831b5
 2013-08-01 20:51:46 +00:00
zra@google.com 42217dc159 Implements far-branches on ARM. 
R=regis@google.com

Review URL: https://codereview.chromium.org//21159002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25617 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-30 15:33:36 +00:00
zra@google.com dad3270d95 Implements far branch targets for MIPS. 
This change adds a flag --mips-far-branches, which when set causes
relative branches to be converted to absolute branches by determining
the PC, adding the branch offset to it, and using the jr or jalr
instruction to jump if the branch test passes.

This procedure clobbers the assembler temporary TMP, so TMP can no
longer be used in a branch test or in the branch delay slot of a
relative branch. Because TMP can't be used in a branch test, a
new temporary is introduced CMPRES2. This change replaces TMP with
CMPRES1 or another register where TMP can no longer be used.

Tests that were failing due to a too-far relative have the
--mips-far-branches flag set.

R=regis@google.com

Review URL: https://codereview.chromium.org//20369003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25543 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-26 23:30:32 +00:00
zra@google.com 351aaec2c3 Replaces Location::ToStackSlotAddress() with Location::ToStackSlotOffset() 
This way, Location no longer mentions the architecture specific Address class.

R=regis@google.com

Review URL: https://codereview.chromium.org//19464002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25122 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-17 20:54:34 +00:00
zra@google.com 20dcf8afaa Implements OSR for arm and mips. 
R=regis@google.com

Review URL: https://codereview.chromium.org//19017007

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24896 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-10 23:45:18 +00:00
zra@google.com 76f872967c Optimize functions containing try-catch on MIPS. 
R=regis@google.com

Review URL: https://codereview.chromium.org//18243002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24616 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-28 23:48:13 +00:00
zra@google.com 60392c70fd Implements external array access for mips. 
R=regis@google.com

Review URL: https://codereview.chromium.org//17907005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24524 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-27 16:42:39 +00:00
regis@google.com 5ffa56b798 Fix and simplify invocation of noSuchMethod on all platforms after the wrong 
number (or bad name) of arguments is passed.
The frame of the wrong method (the one invoked with the wrong number or name of
arguments) is not left on the stack and therefore not visible in the stack trace
anymore, which is much cleaner, especially since the leftover frame was not
fully initialized.
This change was already done on ARM.

R=zra@google.com

Review URL: https://codereview.chromium.org//17857008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24485 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-26 19:58:49 +00:00
zra@google.com 5bf5a92064 Fixes bugs in arm and mips intrinsifier. 
R=regis@google.com

Review URL: https://codereview.chromium.org//17634003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24427 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-25 18:58:47 +00:00
zra@google.com 8edda78ccc Enables more tests for SIMMIPS. 
. Fixes register allocation bugs
. Implements float <-> double conversion in assembler and simulator.
. Fixes floating point argument passing for simarm and simmips,
  and floating point return for simarm, and adjusts tests to match.

R=regis@google.com

Review URL: https://codereview.chromium.org//17502002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24365 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-24 20:16:16 +00:00
zra@google.com 4a99fabecb Enables language tests for SIMMIPS. 
R=regis@google.com

Review URL: https://codereview.chromium.org//17131002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24098 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-17 15:58:31 +00:00
zra@google.com c004b84376 Enables more VM tests for SIMMIPS. 
Implements:
- Megamorphic instance calls
- Left-shift
- Equality
- and various bug-fixes.

R=regis@google.com

Review URL: https://codereview.chromium.org//15934025

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23877 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-11 20:08:40 +00:00
zra@google.com e846af4128 Implements intrinsics for MIPS. 
Also, adds the MADD, MADDU, MTLO, MTHI instructions
to the MIPS simulator, assembler, and disassembler.

R=regis@google.com

Review URL: https://codereview.chromium.org//16272004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23489 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-31 21:03:41 +00:00
zra@google.com e6cf04a8bb Changes to run "Hello, world!" on MIPS hardware. 
R=regis@google.com

Review URL: https://codereview.chromium.org//16160013

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23484 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-31 18:41:41 +00:00
zra@google.com 354b204cf0 Enables optimization on MIPS 
- Exposes double precision rather than single precision floating point registers
  to architecture generic code. This entails a mechanical change in the assembler
  to floating point instructions.
- Adds slti, sltiu instructions for comparison with small immediates, and uses
  them in the Branch(Un)Signed* macros.
- Fixes a bug in the intermediate language comparison/branching instructions
  caused by using subu for comparison. Now it uses two slt instructions.
- Fixes register use bugs in intermediate language.
- More uses of NULLREG instead of loading Object::null()

R=regis@google.com

Review URL: https://codereview.chromium.org//16022011

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23190 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-24 23:45:41 +00:00
zra@google.com b350781cad Impelemnts some FPU arithmetic function for the MIPS simulator, assembler, disassembler. 
R=regis@google.com

Review URL: https://codereview.chromium.org//15038008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22818 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-16 21:18:04 +00:00
zra@google.com 18268541b0 Implements int to double conversion instructions for MIPS simulator, assembler, disassembler. 
R=regis@google.com

Review URL: https://codereview.chromium.org//15144004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22763 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-15 23:51:17 +00:00
zra@google.com 144def4ee3 Implements FPU compare and branching for MIPS simulator, assembler, disassembler. 
R=regis@google.com

Review URL: https://codereview.chromium.org//14672037

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22752 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-15 18:37:47 +00:00
regis@google.com 53347a3337 Remove stack_frame_<arch>.cc files. 
The architecture specific information is in stack_frame_<arch>.h files.

R=srdjan@google.com

Review URL: https://codereview.chromium.org//14925005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22470 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-07 18:06:21 +00:00
zra@google.com 3c10f6b796 On MIPS, keeps Object::null() in a register. 
On MIPS, we have a lot of registers, and we don't use very many of them.
This change removes the second temporary register TMP2, and instead
dedicates a register to holding Object::null(), which is used frequently
for comparisons, etc..

Also, uses branch delay slot when leaving a dart frame and returning.

R=regis@google.com

Review URL: https://codereview.chromium.org//14854010

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22331 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-02 17:53:34 +00:00
zra@google.com aa2dd0acf7 On MIPS, uses more branch delay slots. 
Also, tries to reorganize loops to look like what gcc produces.

R=regis@google.com

Review URL: https://codereview.chromium.org//14733002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22262 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-01 16:56:31 +00:00
zra@google.com 09f3f2537e Uses slt and sltu for signed vs. unsigned comparison by the MIPS assembler. 
Previously, the sequence subu/b{gt,le,...}z was used, which fails to
distinguish between signed and unsigned comparison.

R=regis@google.com

Review URL: https://codereview.chromium.org//14556002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22159 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-30 00:35:09 +00:00
zra@google.com 069456803e Implements features to run "Hello, world!" on simulated MIPS. 
Review URL: https://codereview.chromium.org//14246039

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21759 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-19 18:31:47 +00:00
zra@google.com 64d10ad4e4 Implements write barrier on MIPS. 
Review URL: https://codereview.chromium.org//13925024

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21532 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-16 00:25:03 +00:00
zra@google.com e8f86c5d3a Adds support for UseDartApi vm test on MIPS. 
Also, adds:
- xori instruction,
- SubuDetectOverflow (like AdduDetectOverflow).
Review URL: https://codereview.chromium.org//13884017

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21396 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-12 22:20:32 +00:00
zra@google.com 1349cb1fea Adds some floating point instructions to MIPS simulator, assembler, disassembler. 
Review URL: https://codereview.chromium.org//14206002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21376 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-12 17:25:38 +00:00
zra@google.com 2c5cea8d4e Supports FrameLookup vm test on MIPS 
As with the similar CL for ARM, also:
- Supports inline allocation of objects.
- Supports checking of inline cache and instance calls.
- Supports subtype test cache.
- Supports (some) equality checks.
- Supports for (some) conditional branches.
- Supports for pool pointer setup in stubs.
Review URL: https://codereview.chromium.org//14076005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21233 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-10 21:59:57 +00:00
zra@google.com cae56d75ed Introduces a second temporary register for MIPS assembler macros. 
- Also, adds macros for comparisons followed by branches, and uses them.
Review URL: https://codereview.chromium.org//13483018

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21118 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-08 22:04:27 +00:00
zra@google.com d5be052e40 Adds macros to the MIPS assembler for detecting overflow. 
Review URL: https://codereview.chromium.org//13722022

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21085 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-08 16:51:12 +00:00
zra@google.com 0cc80971fb Implements type checking in MIPS needed for FindCodeObject test. 
Review URL: https://codereview.chromium.org//13619008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20932 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-04 17:55:06 +00:00
zra@google.com fd72ee418a Implements optional parameter handling in MIPS vm. 
- Deocdes ic data and argument descriptor.
- Removes SUB instruction from assembler and disassembler.
Review URL: https://codereview.chromium.org//13474009

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20895 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-03 21:43:52 +00:00
zra@google.com 3e080d1b34 Adds native/leaf runtime call stub and redirection on MIPS. 
Review URL: https://codereview.chromium.org//13473010

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20813 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-02 20:24:55 +00:00
zra@google.com c4b55c1276 Third codegen test passing for simulated MIPS. 
Review URL: https://codereview.chromium.org//13407003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20794 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-02 16:40:14 +00:00
zra@google.com 35aeebcd8c First two codegen tests passing on SIMMIPS 
Review URL: https://codereview.chromium.org//13228002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20734 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-01 17:02:44 +00:00
zra@google.com 2125ee9a37 Simplifies MIPS LoadWordFromPoolOffset 
Review URL: https://codereview.chromium.org//13094015

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20539 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-26 20:27:31 +00:00
zra@google.com 463b651f78 Adds Stop to MIPS. Starts on MIPS call patcher. 
Review URL: https://codereview.chromium.org//12703028

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20527 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-26 17:50:43 +00:00
zra@google.com 007c830756 Adds branch instructions and labels to the MIPS simulator, assembler, disassembler. 
Review URL: https://codereview.chromium.org//12634030

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20419 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-22 21:37:10 +00:00
zra@google.com 2bdc772122 Adds MIPS SPECIAL instructions to simulator, assembler, debugger. 
Review URL: https://codereview.chromium.org//12837009

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20321 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-21 15:50:31 +00:00
zra@google.com 82367b380d Copies Simulator Debugger from ARM to MIPS. 
Also includes changes to keep it from aborting unexpectedly.
Among other things, I changed the Disassembler::Disassemble to return false
when the underlying decoder can't decode an instruction. Then,
the MIPS SimulatorDebugger will refuse to step or cont on an instruction
that the Disassembler can't decode.
Review URL: https://codereview.chromium.org//12431016

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19958 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-13 18:43:16 +00:00
zra@google.com ad8004569d Adds MIPS instructions to simulator, assembler, disassembler 
ins - bitfield insert
ext - bitfield extract
l{b,bu,h,hu,w} - load byte, unsigned byte, etc.
s{b,h,w} - store byte, halfword, word
Review URL: https://codereview.chromium.org//12519007

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19819 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-11 20:50:50 +00:00