srdjan@google.com
a8f549dbc3
Merge sin(a), cos(a) into one instruction. On IA32 use x87 fsincos operation, on x64 call runtime routine whihc merges sin/cos intos sincos.
...
TODO: Implement for ARM and MIPS.
R=fschneider@google.com
Review URL: https://codereview.chromium.org//92433002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@30827 260f80e4-7a28-3924-810f-c04153c831b5
2013-12-03 22:00:27 +00:00
iposva@google.com
070d3dedf7
- Add a per-isolate pseudo random number generator to the
...
VM internals. This PRNG is not used to generate random
numbers in Dart code.
- Use the PRNG to generate JIT cookies for large constants
if needed during assembly.
- Add the possibility to set an external entropy source
for the PRNG through the C API.
R=asiva@google.com
Review URL: https://codereview.chromium.org//59773007
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@29950 260f80e4-7a28-3924-810f-c04153c831b5
2013-11-06 00:59:46 +00:00
kmillikin@google.com
de1519525c
Reapply "Do not directly load smi constants larger than a 16 bit..."
...
Reapply "Do not directly load smi constants larger than a 16 bit payload on
ia32" with a bugfix. The predicate Assembler::IsSafeSmi incorrectly
returned true for non-smis on non-ia32 platforms.
Original summary: Instead of emitting a large smi constant directly as an
immediate, xor the smi with a random 32-bit cookie at compile time, emit
code to move that into a register and then to xor the register with the
cookie.
Original codereview: https://codereview.chromium.org/48743002/
R=fschneider@google.com
Review URL: https://codereview.chromium.org//51333006
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@29533 260f80e4-7a28-3924-810f-c04153c831b5
2013-10-30 11:38:39 +00:00
whesse@google.com
0729948569
Revert "Do not directly load smi constants larger than a 16 bit payload on ia32."
...
There is an assertion failure on debug VM tests.
BUG=
R=fschneider@google.com
Review URL: https://codereview.chromium.org//46873004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@29458 260f80e4-7a28-3924-810f-c04153c831b5
2013-10-29 16:49:42 +00:00
kmillikin@google.com
adf6560e82
Do not directly load smi constants larger than a 16 bit payload on ia32.
...
Instead of emitting a large smi constant directly as an immediate, xor the
smi with a random 32-bit cookie at compile time, emit code to move that into
a register and then to xor the register with the cookie.
1. In unoptimized code constants are always loaded into a register in
ConstantInstr::EmitNativeCode. Change it to load safely.
2. In optimized code constants loaded into a register for use by an
instruction are loaded by ParallelMoveResolver::EmitMove. Change it to
load safely.
3. In optimized code some instructions allow constants as inputs. These are
reflected with an input location of Location::RegisterOrConstant (or
similar) or else Location::Constant. For the former allocate a register
if the constant is unsafe, and for the latter check for safety before
allowing the constant input.
BUG=https://code.google.com/p/dart/issues/detail?id=1742
R=iposva@google.com , srdjan@google.com
Review URL: https://codereview.chromium.org//48743002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@29439 260f80e4-7a28-3924-810f-c04153c831b5
2013-10-29 12:19:12 +00:00
srdjan@google.com
3a8252f90d
Cleanups: int -> intptr_t for "array" lengths, memory sizes.
...
R=asiva@google.com
Review URL: https://codereview.chromium.org//26294002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@28324 260f80e4-7a28-3924-810f-c04153c831b5
2013-10-07 20:19:37 +00:00
sra@google.com
ce4b15c0e9
Esoteric bit operations.
...
- bit length
- truncate to signed fixed width integer
- truncate to unsigned fixed width integer
This change is motivated by a program that spends 20-30% of its time here:
// TODO(5828): Replace this with a bit-length method on int when available.
int n_bitLength = this.n.toRadixString(2).length;
See Also
https://code.google.com/p/dart/issues/detail?id=5828#c3
https://code.google.com/p/dart/issues/detail?id=6486#c2
https://code.google.com/p/dart/issues/detail?id=5798#c5
https://code.google.com/p/dart/issues/detail?id=12008
R=lrn@google.com , srdjan@google.com
Review URL: https://codereview.chromium.org//23645003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@27269 260f80e4-7a28-3924-810f-c04153c831b5
2013-09-06 22:22:26 +00:00
regis@google.com
8171570100
Fix the previously ineffective assert checking the number of arguments passed to
...
a runtime entry in the VM.
R=asiva@google.com
Review URL: https://codereview.chromium.org//23672011
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@26826 260f80e4-7a28-3924-810f-c04153c831b5
2013-08-28 23:07:14 +00:00
johnmccutchan@google.com
4ba3c7b2c9
Add packed add and subtract to IA32 and X64 assemblers
...
R=srdjan@google.com
Review URL: https://codereview.chromium.org//23129014
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@26325 260f80e4-7a28-3924-810f-c04153c831b5
2013-08-19 19:57:22 +00:00
zra@google.com
fa2ad38a31
Enables per-function far-branches for ARM and MIPS.
...
R=regis@google.com , srdjan@google.com
Review URL: https://codereview.chromium.org//21363003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25723 260f80e4-7a28-3924-810f-c04153c831b5
2013-08-01 20:51:46 +00:00
srdjan@google.com
66fb716dce
Implement some conditional moves instructions for ia32/x64. Use them in MinMax instruction implementation.
...
R=johnmccutchan@google.com
Review URL: https://codereview.chromium.org//21307004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25685 260f80e4-7a28-3924-810f-c04153c831b5
2013-07-31 22:57:33 +00:00
johnmccutchan@google.com
1b09112ce0
Add two argument SSE shuffle instructions
...
R=srdjan@google.com
Review URL: https://codereview.chromium.org//19940005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25301 260f80e4-7a28-3924-810f-c04153c831b5
2013-07-22 20:20:50 +00:00
zra@google.com
351aaec2c3
Replaces Location::ToStackSlotAddress() with Location::ToStackSlotOffset()
...
This way, Location no longer mentions the architecture specific Address class.
R=regis@google.com
Review URL: https://codereview.chromium.org//19464002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25122 260f80e4-7a28-3924-810f-c04153c831b5
2013-07-17 20:54:34 +00:00
kmillikin@google.com
3e78b2ad4a
Reapply "Initial implementation of on-stack replacement (OSR)."
...
This reapplies SVN r24024 with a bugfix.
After OSR compilation, restore the pre-OSR code (which might be already
optimized) rather than the unoptimized code (which might have its entry
patched). When the optimized code entry is patched it is only safe to call
it as a static call, not as an instance call.
R=fschneider@google.com
Review URL: https://codereview.chromium.org//17233003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24088 260f80e4-7a28-3924-810f-c04153c831b5
2013-06-17 11:05:15 +00:00
kmillikin@google.com
d6f3eccdf2
Revert "Initial implementation of on-stack replacement (OSR)."
...
This reverts commit 24024.
TBR=fschneider@google.com
Review URL: https://codereview.chromium.org//16888013
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24025 260f80e4-7a28-3924-810f-c04153c831b5
2013-06-14 10:30:53 +00:00
kmillikin@google.com
0b39927d30
Initial implementation of on-stack replacement (OSR).
...
Add profiling support to select OSR candidates and launch the compiler
for OSR, followed by entry to the function at the OSR entry point.
Implemented only on IA32 and X64. The initial implementation can be
improved in various ways --- specifically: tuning of profiling
parameters and incorporation of feedback about the actual values seen
at OSR entry.
R=fschneider@google.com
Review URL: https://codereview.chromium.org//16693006
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24024 260f80e4-7a28-3924-810f-c04153c831b5
2013-06-14 10:10:55 +00:00
srdjan@google.com
34ac0a0fa1
Use stack locations instead of register for binary Smi operations when possible.
...
R=fschneider@google.com
Review URL: https://codereview.chromium.org//16126003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23249 260f80e4-7a28-3924-810f-c04153c831b5
2013-05-28 10:44:02 +00:00
fschneider@google.com
8ad125f607
Optimize functions containing try-catch.
...
This is a first step towards fully optimizing try-catch-finally.
At a catch entry, all local variables and parameters are
expected at a fixed stack location. There is a list of
initial definitions at the catch entry block, similar to
the initial definitions at graph entry.
Inside every try-block there is a special prologue code before each
call (instruction that may throw) inside the try-block. This prologue
is similar to a parallel move instruction: It moves all locals+parameters
to the locations expected by the catch-entry block. The stack frame
is extended with the corresponding number of fixed slots right below
the normal spill slots.
Every function containing try-catch has additional compiler-
generated local variables to pass the context, the exception and
the stack trace.
Variable liveness analysis is adapted to treat locals inside try{} blocks
specially: Every call has an implicit LoadLocal of every local variable.
This CL uses a safe approximiation of liveness which can be optimized further.
Current restrictions which are planned for future CLs:
* No inlining inside try-blocks.
* No inlining of functions containing try-catch.
* No try-finally yet.
R=kmillikin@google.com
Review URL: https://codereview.chromium.org//14682020
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22615 260f80e4-7a28-3924-810f-c04153c831b5
2013-05-13 10:33:24 +00:00
regis@google.com
53347a3337
Remove stack_frame_<arch>.cc files.
...
The architecture specific information is in stack_frame_<arch>.h files.
R=srdjan@google.com
Review URL: https://codereview.chromium.org//14925005
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22470 260f80e4-7a28-3924-810f-c04153c831b5
2013-05-07 18:06:21 +00:00
iposva@google.com
6c4ac09cb9
- Remove heap tracing.
...
Review URL: https://codereview.chromium.org//14179015
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21844 260f80e4-7a28-3924-810f-c04153c831b5
2013-04-22 21:43:57 +00:00
srdjan@google.com
1ccf49ce9f
Use rep_movsb for copying one-byte strings in substring intrinsic.
...
Review URL: https://codereview.chromium.org//14122002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21293 260f80e4-7a28-3924-810f-c04153c831b5
2013-04-11 16:39:34 +00:00
vegorov@google.com
11edd87390
Convert diamond shaped control flow into a single conditional instruction.
...
Adds a IfConverter pass that right now recognizes two simple patterns cond ? 0 : 2^n and cond ? x : x+-1 that can be generated without branches on ia32 and x64 using setcc instruction.
R=fschneider@google.com
Review URL: https://codereview.chromium.org//14057004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21207 260f80e4-7a28-3924-810f-c04153c831b5
2013-04-10 15:09:46 +00:00
vegorov@google.com
0e9a59eb59
Use shorter write-barrier filtering sequence when value is known to be non-smi.
...
R=iposva@google.com
Review URL: https://codereview.chromium.org//12438032
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@20373 260f80e4-7a28-3924-810f-c04153c831b5
2013-03-22 11:28:13 +00:00
regis@google.com
1b274ff2cf
Remove the barely used macro assemblers after merging their contents to the base
...
assemblers.
Review URL: https://codereview.chromium.org//12398029
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19434 260f80e4-7a28-3924-810f-c04153c831b5
2013-03-05 00:04:32 +00:00
srdjan@google.com
1bc8991142
For Doubl erounding call C-function instead of attempting to inline it. Fixes issue 8760.
...
Review URL: https://codereview.chromium.org//12334080
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19013 260f80e4-7a28-3924-810f-c04153c831b5
2013-02-25 23:05:43 +00:00
regis@google.com
8c44be4313
Add support for object pool that will be used on ARM and MIPS architectures.
...
Modify code patching infrastructure to accept code object, which is necessary to
get to the object pool containing patchable target addresses.
Modify assembler test infrastructure to provide associated code object.
Review URL: https://codereview.chromium.org//12260026
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18604 260f80e4-7a28-3924-810f-c04153c831b5
2013-02-15 23:55:31 +00:00
fschneider@google.com
e2a0c8f7ca
Optimize stores to ExternalUint8Array and ExternalUint8ClampedArray in the optimizer.
...
This CL adds support for these two array types to the StoreIndexed instruction.
Review URL: https://codereview.chromium.org//12263010
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18517 260f80e4-7a28-3924-810f-c04153c831b5
2013-02-14 12:59:51 +00:00
johnmccutchan@google.com
9fb0984c9d
SSE Assembler + Linux build fixes
...
Review URL: https://codereview.chromium.org//12223115
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18493 260f80e4-7a28-3924-810f-c04153c831b5
2013-02-13 23:05:17 +00:00
johnmccutchan@google.com
dd140c2958
Revert SSE assembler changes
...
Review URL: https://codereview.chromium.org//12212151
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18410 260f80e4-7a28-3924-810f-c04153c831b5
2013-02-12 23:14:12 +00:00
johnmccutchan@google.com
06eb49d537
SSE Assembler and Disassembler support
...
Review URL: https://codereview.chromium.org//12207117
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18406 260f80e4-7a28-3924-810f-c04153c831b5
2013-02-12 22:43:48 +00:00
regis@google.com
912194a756
Fix vm code base so that it can be built for --arch=simarm (no snapshot yet).
...
Review URL: https://codereview.chromium.org//11956004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@17246 260f80e4-7a28-3924-810f-c04153c831b5
2013-01-18 00:34:20 +00:00
srdjan@google.com
40a7130741
Inline Doubles truncate and round.
...
Review URL: https://codereview.chromium.org//11573044
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@16983 260f80e4-7a28-3924-810f-c04153c831b5
2013-01-11 20:42:47 +00:00
fschneider@google.com
87a3a4b479
Support immediate and memory operands for PushArgumentInstr in optimized code.
...
If a value is a constant or stored on the stack this change avoids loading it into a
new register before pushing it.
Review URL: https://codereview.chromium.org//11791051
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@16806 260f80e4-7a28-3924-810f-c04153c831b5
2013-01-08 16:51:57 +00:00
cshapiro@google.com
49f6f9f36d
Merge the Merlin heap tracing to top-of-trunk.
...
Review URL: https://codereview.chromium.org//11428067
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@16199 260f80e4-7a28-3924-810f-c04153c831b5
2012-12-15 19:58:45 +00:00
vegorov@google.com
132bdc6bfb
Support VTune's JIT interface.
...
R=iposva@google.com
BUG=
Review URL: https://codereview.chromium.org//11412106
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@15517 260f80e4-7a28-3924-810f-c04153c831b5
2012-11-29 13:54:06 +00:00
fschneider@google.com
5399496ac4
Only require SSE2 at minimum hardware requirement.
...
BUG=dart:6010
Review URL: https://codereview.chromium.org//11416136
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@15253 260f80e4-7a28-3924-810f-c04153c831b5
2012-11-22 12:46:57 +00:00
fschneider@google.com
b38daebd36
Faster 64-bit left-shift for ia32.
...
This CL adds a fast left-shift that operates on unboxed mints.
(64-bit integers) to the ia32 optimizing compiler.
Review URL: https://codereview.chromium.org//11085004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@13408 260f80e4-7a28-3924-810f-c04153c831b5
2012-10-09 11:59:44 +00:00
fschneider@google.com
3efefbd582
Faster 64-bit right-shift for the ia32 compiler.
...
Review URL: https://codereview.chromium.org//11027060
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@13295 260f80e4-7a28-3924-810f-c04153c831b5
2012-10-05 14:42:00 +00:00
fschneider@google.com
f60ebcc5fb
Add fast 64-bit bitwise negation to the IA32 optimizing compiler.
...
Review URL: https://codereview.chromium.org//11043020
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@13221 260f80e4-7a28-3924-810f-c04153c831b5
2012-10-04 12:01:12 +00:00
fschneider@google.com
cb719805d8
Add fast 64-bit integer ADD and SUB to the optimizing compiler.
...
They operate on unboxed 64-bit integers stored in xmm registers.
I also fixed an issue with some SSE 4 specific assembler
tests where we hit an assert with an empty assembler buffer
when running with --no-use-sse41.
Review URL: https://codereview.chromium.org//11016028
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@13211 260f80e4-7a28-3924-810f-c04153c831b5
2012-10-04 08:50:28 +00:00
fschneider@google.com
6632f191c4
Support for unboxed 64-bit integer bitwise operations and equality on ia32.
...
This CL adds AND, OR, XOR and == operations on unboxed 64-bit integers
(aka. mints).
Unboxed mints are stored in xmm registers. Each xmm register location
has an additional bit to keep track of its value representation.
Unboxed mints are materialized on the heap on deoptmization in the same way as
unboxed doubles.
The SSE instructions used are available on all CPUs that support SSE 4.1.
Review URL: https://codereview.chromium.org//10968059
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@13112 260f80e4-7a28-3924-810f-c04153c831b5
2012-10-02 11:25:53 +00:00
fschneider@google.com
71767f5218
Add code for CPU feature detection and use it to detect SSE3 and SSE 4.1.
...
The Dart VM now requires at least SSE3 to build and run.
There is a new flag --use-sse41 (default:true) to disable the use of
SSE 4.1 features manually.
Review URL: https://codereview.chromium.org//10990028
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@12897 260f80e4-7a28-3924-810f-c04153c831b5
2012-09-26 09:08:21 +00:00
cshapiro@google.com
da14bf70a7
Add attributions so printf like functions can have their arguments checked.
...
This change also corrects some misuses of format strings and format
arguments that discovered by the compiler checks.
Review URL: https://chromiumcodereview.appspot.com//10869063
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@11912 260f80e4-7a28-3924-810f-c04153c831b5
2012-09-06 00:58:25 +00:00
vegorov@google.com
1911b2bc81
Make register allocator to disregard constant computation with no uses.
...
Inline constant values into environments, instead of creating a use of the constant definition.
Change BinarySmiOpComp code template to allow inline constant uses for the right hand side.
R=fschneider@google.com
BUG=
Review URL: https://chromiumcodereview.appspot.com//10916082
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@11798 260f80e4-7a28-3924-810f-c04153c831b5
2012-09-04 09:58:57 +00:00
vegorov@google.com
264c4f6d1a
Add support for XMM registers in SSA code generation pipeline.
...
Split BinaryDoubleOp into several instructions that manipulate unboxed doubles.
R=fschneider@google.com
BUG=
Review URL: https://chromiumcodereview.appspot.com//10875030
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@11313 260f80e4-7a28-3924-810f-c04153c831b5
2012-08-24 14:45:42 +00:00
vegorov@google.com
61dc368874
Fix kStoreBufferBlockProcessRuntimeEntry calling sequence.
...
Poping of volatile registers was performed without taking into account the fact that stack pointer could have been modified to ensure correct alignment _after_ volatile registers were pushed.
Enable --use-ssa on x64 again.
BUG=4221
Review URL: https://chromiumcodereview.appspot.com//10820053
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@10007 260f80e4-7a28-3924-810f-c04153c831b5
2012-07-30 10:38:48 +00:00
vegorov@google.com
1bd5a9b414
Skeleton of a linear scan register allocator.
...
BUG=
TEST=
Review URL: https://chromiumcodereview.appspot.com//10696151
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@9563 260f80e4-7a28-3924-810f-c04153c831b5
2012-07-11 18:52:17 +00:00
iposva@google.com
dd800b6870
- On store buffer block overflow call a VM leaf function to
...
add the entries into the store buffer.
- Add a way to preserve and restore caller saved registers.
- Clean up the implementation of the stub for Assembler::Stop.
Review URL: https://chromiumcodereview.appspot.com//10758008
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@9490 260f80e4-7a28-3924-810f-c04153c831b5
2012-07-09 22:58:27 +00:00
asiva@google.com
f05e3736d8
Fix issue 1968, replace usage of inline 'asm' constructs in 'stack alignment', 'jump to exception handler' and 'jump to error handler' code with calls to appropriate stubs.
...
Review URL: https://chromiumcodereview.appspot.com//10664004
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@9071 260f80e4-7a28-3924-810f-c04153c831b5
2012-06-25 17:35:20 +00:00
iposva@google.com
5e52657f33
- Implement the filtering store barrier on x64.
...
Review URL: https://chromiumcodereview.appspot.com//10581049
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@8953 260f80e4-7a28-3924-810f-c04153c831b5
2012-06-20 23:48:26 +00:00