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32 Commits

Author SHA1 Message Date
zra@google.com 3fd0e585d3 Fixes bug in far branches on MIPS. 
Also increases test coverage of far branches on
ARM and MIPS.

R=regis@google.com

Review URL: https://codereview.chromium.org//107293008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@31024 260f80e4-7a28-3924-810f-c04153c831b5
 2013-12-10 16:43:06 +00:00
zra@google.com a783459837 Preserves callee-saved FPU registers on ARM 
Preserves callee-saved FPU registers on ARM when
going from C++ to Dart code. Adds assertions to
the simulator to make sure this is being done
correctly.

R=regis@google.com

Review URL: https://codereview.chromium.org//23549013

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@27072 260f80e4-7a28-3924-810f-c04153c831b5
 2013-09-03 18:23:43 +00:00
zra@google.com 8f3e8783f8 Implements the two argument shuffle SIMD instruction for ARM. 
R=regis@google.com

Review URL: https://codereview.chromium.org//21004011

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25638 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-30 20:49:22 +00:00
zra@google.com af23dfc5b2 Increases the number of ARM floating-point registers. 
This is to be consistent with VFPv3_D32. Later, we'll detect
VFPv3_D16 at runtime.

R=regis@google.com

Review URL: https://codereview.chromium.org//19806005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25352 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-23 18:25:44 +00:00
zra@google.com dd9adc1a86 Adds more SIMD instructions for ARM. 
Adds the vnegqs, vabsqs, and vandq instructions.

Also reverts the increase in the number of floating point registers since it is causing crashes on hardware.

R=regis@google.com

Review URL: https://codereview.chromium.org//19493004

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25320 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-22 23:26:12 +00:00
zra@google.com 4b97f8c18c Adds reciprocal squre root SIMD instructions for ARM. 
R=regis@google.com

Review URL: https://codereview.chromium.org//19875002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25291 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-22 18:19:44 +00:00
zra@google.com a15bac1044 Adds ARM SIMD instructions. 
vminqs, maxqs, vrecpeqs (Reciprocal estimate), vrecpsqs (Reciprocal Newton-Raphson step).

R=regis@google.com

Review URL: https://codereview.chromium.org//19773017

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25245 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-19 21:32:03 +00:00
zra@google.com 18f6092d52 Implements ARM SIMD comparison instructions. 
R=regis@google.com

Review URL: https://codereview.chromium.org//19678020

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25189 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-18 22:56:45 +00:00
zra@google.com d886c10f6e Enables a SIMD test for ARM. 
Required adding the veorq, vmovq, and vdup instructions.

R=regis@google.com

Review URL: https://codereview.chromium.org//19776007

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25165 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-18 18:40:27 +00:00
zra@google.com 4731ad6b71 Adds the vtbl ARM SIMD instruction. 
It is needed for the Float32x4ShuffleInstr of the intermediate language.

R=regis@google.com

Review URL: https://codereview.chromium.org//19400003

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25073 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-16 21:18:26 +00:00
zra@google.com 3cebda38e6 Merges ARM load/store type enums into one enum. 
R=regis@google.com

Review URL: https://codereview.chromium.org//19256021

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25064 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-16 18:32:40 +00:00
zra@google.com 344b295eee Implements ARM SIMD multiplication and subtraction instructions. 
R=regis@google.com

Review URL: https://codereview.chromium.org//19290006

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@25052 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-16 16:13:56 +00:00
zra@google.com f219f81b14 Begins implementation of ARM neon instructions. 
Just adds the vadd instruction, but also changes the
arm assembler to expose the Q registers rather than the
D registers. Q0 = D1:D0 = S3:S2:S1:S0. This is similar
to how ia32 and x64 use only the xmm registers for
floating point.

R=regis@google.com

Review URL: https://codereview.chromium.org//18684008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24982 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-12 23:22:50 +00:00
zra@google.com 98fee55e2c Fixes ARM assembler test for hardware. 
R=regis@google.com

Review URL: https://codereview.chromium.org//18326012

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24639 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-01 18:37:10 +00:00
zra@google.com f86d2ec1b4 Adds support for integer division for ARM chips without the sdiv instruction. 
R=regis@google.com

Review URL: https://codereview.chromium.org//18331006

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24635 260f80e4-7a28-3924-810f-c04153c831b5
 2013-07-01 17:44:09 +00:00
zra@google.com 8edda78ccc Enables more tests for SIMMIPS. 
. Fixes register allocation bugs
. Implements float <-> double conversion in assembler and simulator.
. Fixes floating point argument passing for simarm and simmips,
  and floating point return for simarm, and adjusts tests to match.

R=regis@google.com

Review URL: https://codereview.chromium.org//17502002

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@24365 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-24 20:16:16 +00:00
zra@google.com 7718086a5f Fixes small ARM bugs, and updates status files. 
R=srdjan@google.com

Review URL: https://codereview.chromium.org//16054007

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23718 260f80e4-7a28-3924-810f-c04153c831b5
 2013-06-06 21:52:26 +00:00
regis@google.com 77417c2f49 Implement a few more features on ARM. 
The vm tests byte_array_test and byte_array_optimized_test still fail due to
an inlining bug on ARM.

R=zra@google.com

Review URL: https://codereview.chromium.org//15899010

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23370 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-29 23:12:20 +00:00
zra@google.com e5229295a0 Removes ARM mrc instruction. 
It is a privileged instruction and was only being used in tests
running on the simulator.

R=regis@google.com

Review URL: https://codereview.chromium.org//16194010

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23367 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-29 21:31:27 +00:00
zra@google.com 26fa41d1b1 Implements intrinsics for ARM. 
R=regis@google.com

Review URL: https://codereview.chromium.org//15822008

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@23311 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-28 22:55:51 +00:00
zra@google.com fabc87d633 Fixes for integer division on ARM hardware so that assembler tests pass. 
Now, all VM tests that pass on SIMARM, pass on ARM.

Also, more assertions in the ARM disassembler and simulator to
make sure that condition codes aren't used with bkpt.

R=regis@google.com

Review URL: https://codereview.chromium.org//14784011

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22471 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-07 18:21:18 +00:00
regis@google.com 76c8e61855 Fix ARM memory addressing mode 3 in assembler. 
Update assembler test.

R=zra@google.com

Review URL: https://codereview.chromium.org//14637013

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@22285 260f80e4-7a28-3924-810f-c04153c831b5
 2013-05-01 21:33:08 +00:00
regis@google.com ad6005e5c4 Support debugger API on ARM. 
Support smull ARM instruction in order to detect 32-bit multiplication overflow.
Enable debugger api tests on ARM.
Enable isolate tests on ARM.
Enable code descriptors tests on ARM.
Enable snapshot tests on ARM.
Enable heap tests on ARM.

Review URL: https://codereview.chromium.org//13983016

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21890 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-23 16:10:22 +00:00
regis@google.com b37703989f Implement write barrier on ARM. 
Enable StoreIntoObject and DartEntry vm tests.
Review URL: https://codereview.chromium.org//13638019

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@21083 260f80e4-7a28-3924-810f-c04153c831b5
 2013-04-08 16:44:39 +00:00
zra@google.com 31da7d6c55 Adds muls, sdiv, udiv instructions to ARM simulator, assembler, disassembler 
Review URL: https://codereview.chromium.org//12459005

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19511 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-05 19:53:43 +00:00
zra@google.com c9c0881ac7 Adds mrc instruction to arm simulator, assembler, disassembler. 
This instruction will be used to query an arm processor to
determine whether it supports the sdiv and udiv instructions.

Also adds a flag --sim_has_int_div to the arm simulator,
which changes the result of the mrc instruction so we can
test both ways.
Review URL: https://codereview.chromium.org//12378080

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19439 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-05 01:03:22 +00:00
zra@google.com 767b8ec8fc Adds vstm, vldm to ARM simulator, assembler, disassembler 
Review URL: https://codereview.chromium.org//12390039

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19404 260f80e4-7a28-3924-810f-c04153c831b5
 2013-03-04 17:45:38 +00:00
zra@google.com 0ce264e8fc Implements shifted offset register addressing mode for arm. 
Review URL: https://codereview.chromium.org//12321149

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@19102 260f80e4-7a28-3924-810f-c04153c831b5
 2013-02-27 00:35:57 +00:00
zra@google.com ddb1f60210 Adds ARM arm assembler tests. 
Review URL: https://codereview.chromium.org//12340006

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18844 260f80e4-7a28-3924-810f-c04153c831b5
 2013-02-21 18:36:34 +00:00
regis@google.com 8c44be4313 Add support for object pool that will be used on ARM and MIPS architectures. 
Modify code patching infrastructure to accept code object, which is necessary to
get to the object pool containing patchable target addresses.
Modify assembler test infrastructure to provide associated code object.
Review URL: https://codereview.chromium.org//12260026

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18604 260f80e4-7a28-3924-810f-c04153c831b5
 2013-02-15 23:55:31 +00:00
regis@google.com 5675b85979 Generate first ARM assembler test and execute (simulate) it. 
RFC: First draft showing how generated ARM code accesses GC'ed objects and
accesses patched call targets.
Review URL: https://codereview.chromium.org//12224024

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@18200 260f80e4-7a28-3924-810f-c04153c831b5
 2013-02-07 00:55:47 +00:00
regis@google.com 0bf36986ec Add test skeletons for arm and mips. 
Review URL: https://codereview.chromium.org//11929037

git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@17330 260f80e4-7a28-3924-810f-c04153c831b5
 2013-01-18 23:46:48 +00:00