Implements a backend targeting RV32GC and RV64GC, based on Linux standardizing around GC. The assembler is written to make it easy to disable usage of C, but because the sizes of some instruction sequences are compile-time constants, an additional build configuration would need to be defined to make use of it.
The assembler and disassembler cover every RV32/64GC instruction. The simulator covers all instructions except accessing CSRs and the floating point state accessible through such, include accrued exceptions and dynamic rounding mode.
Quirks:
- RISC-V is a compare-and-branch architecture, but some existing "architecture-independent" parts of the Dart compiler assume a condition code architecture. To avoid rewriting these parts, we use a peephole in the assembler to map to compare-and-branch. See Assembler::BranchIf. Luckily nothing depended on taking multiple branches on the same condition code set.
- There are no hardware overflow checks, so we must use Hacker's Delight style software checks. Often these are very cheap: if the sign of one operand is known, a single branch is needed.
- The ranges of RISC-V branches and jumps are such that we use 3 levels of generation for forward branches, instead of the 2 levels of near and far branches used on ARM[64]. Nearly all code is handled by the first two levels with 20-bits of range, with enormous regex matchers triggering the third level that uses aupic+jalr to get 32-bits of range.
- For PC-relative calls in AOT, we always generate auipc+jalr pairs with 32-bits of range, so we never generate trampolines.
- Only a subset of registers are available in some compressed instructions, so we assign the most popular uses to these registers. In particular, THR, TMP[2], CODE and PP. This has the effect of assigning CODE and PP to volatile registers in the C calling convention, whereas they are assigned preserved registers on the other architectures. As on ARM64, PP is untagged; this is so short indices can be accessed with a compressed instruction.
- There are no push or pop instructions, so combining pushes and pops is preferred so we can update SP once.
- The C calling convention has a strongly aligned stack, but unlike on ARM64 we don't need to use an alternate stack pointer. The author ensured language was added to the RISC-V psABI making the OS responsible for realigning the stack pointer for signal handlers, allowing Dart to leave the stack pointer misaligned from the C calling convention's point of view until a foreign call.
- We don't bother with the link register tracking done on ARM[64]. Instead we make use of an alternate link register to avoid inline spilling in the write barrier.
Unimplemented:
- non-trivial FFI cases
- Compressed pointers - No intention to implement.
- Unboxed SIMD - We might make use of the V extension registers when the V extension is ratified.
- BigInt intrinsics
TEST=existing tests for IL level, new tests for assembler/disassembler/simulator
Bug: https://github.com/dart-lang/sdk/issues/38587
Bug: https://github.com/dart-lang/sdk/issues/48164
Change-Id: I991d1df4be5bf55efec5371b767b332d37dfa3e0
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/217289
Reviewed-by: Alexander Markov <alexmarkov@google.com>
Reviewed-by: Daco Harkes <dacoharkes@google.com>
Reviewed-by: Slava Egorov <vegorov@google.com>
Commit-Queue: Ryan Macnak <rmacnak@google.com>
This relands https://dart-review.googlesource.com/c/sdk/+/205633
but without renaming TARGET_OS_IPHONE to DART_TARGET_OS_IPHONE.
It also changes uses of TARGET_OS_IOS to
DART_TARGET_OS_MACOS_IOS to be consistent with the rest of the
VM.
TargetConditionals.h for XCode 13 defines several
TARGET_OS_* preprocessor symbols that confuse the
Dart build. There is probably a more targeted fix
for this, but renaming the symbols that Dart uses
will also prevent this problem if more symbols
are added to the platform headers in the future.
See: https://github.com/dart-lang/sdk/issues/46499
TEST=It builds.
Change-Id: Ie775c19dd23cfdf5f65e5ebc6ee4ec3a561676fa
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/205860
Commit-Queue: Zach Anderson <zra@google.com>
Reviewed-by: Alexander Aprelev <aam@google.com>
TargetConditionals.h for XCode 13 defines several
TARGET_OS_* preprocessor symbols that confuse the
Dart build. There is probably a more targeted fix
for this, but renaming the symbols that Dart uses
will also prevent this problem if more symbols
are added to the platform headers in the future.
See: https://github.com/dart-lang/sdk/issues/46499
TEST=It builds.
Change-Id: I3b33a03b4a9a14b76d55fe12f8cdefec4b3c3664
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/205633
Commit-Queue: Zach Anderson <zra@google.com>
Reviewed-by: Siva Annamalai <asiva@google.com>
Android and Linux use R11 as the FP register in ARM code and R7 in Thumb code. We've been assuming all code in our process is ARM and reading R11 as FP. This made our stack walks fail if they started in Thumb code.
This issue does not arise on iOS, because its ABI uses R7 as the FP register for both ARM and Thumb code.
R=zra@google.com
Review-Url: https://codereview.chromium.org/2965823002 .
Like HOST_ARCH_*, HOST_OS_* describes the OS the VM is running on, which may be different from the OS the VM is generating code for during AOT compilation.
Currently we conflate the two when emitting AOT as assembly, and we get away with it because Flutter only uses assembly for targeting iOS and one can only target iOS from a Mac, but we expect to use assembly for Android as well so native tools can unwind Dart frames.
R=zra@google.com
Review-Url: https://codereview.chromium.org/2750843003 .
Kernel does not clear If-Then execution state bits when entering ARM signal handler which violates requirements imposed by ARM architecture reference. Some CPUs look at these bits even while in ARM mode which causes them
to skip some instructions in the prologue of the signal handler.
To work around the issue we insert enough NOPs in the prologue to ensure that no actual instructions are skipped and then branch to the actual signal handler.
For the kernel patch that fixes the issue see: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=6ecf830e5029598732e04067e325d946097519cb
This causes sporadic crashes with SIGILL on some testing devices (e.g. Nexus 7).
R=fschneider@google.com
BUG=
Review URL: https://codereview.chromium.org/1940883002 .
Profiler improvements:
- Track Functions in profile and build Function based trie
- Associate code objects with functions
- Created cpu_profile.dart library
- Major speed improvements for disassembly view
- Fix truncation of disassembly comments
- Ability to get code object ticks from disassembly view
- Inlining mini-map in disassembly view.
- Remove a bunch of unused data from profile service response
- In some cases a caller PC that is better than the PC marker is inserted into the stack trace
- Inlined functions are expanded
- Ability to clear profile
- New flag '--keep_code' which keeps deoptimized code around for use by the profiler.
General fixes:
- Fix caching in service library
- Remove pubspec.yaml before running pub get
R=asiva@google.com, rmacnak@google.com
Review URL: https://codereview.chromium.org//928833003
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@44067 260f80e4-7a28-3924-810f-c04153c831b5
On arm64, in Dart code, R18(SP) is the stack pointer.
In C++ code, R31(CSP) is the stack pointer.
The profiler must choose the right one when performing
its bounds checks.
This change also fixes a bug in the InvokeDartCode stub
on arm64 so that CSP is set to the Isolate's stack
limit immediately, rather than a bit later. When it was
set a bit later, if a profiler interrupt came in in the
interim, the stack would be smashed.
R=johnmccutchan@google.com
Review URL: https://codereview.chromium.org//583683002
git-svn-id: https://dart.googlecode.com/svn/branches/bleeding_edge/dart@40502 260f80e4-7a28-3924-810f-c04153c831b5
Ryan Macnak