skarg
104 lines
4.1 KiB
C
104 lines
4.1 KiB
C
// ----------------------------------------------------------------------------
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// ATMEL Microcontroller Software Support - ROUSSET -
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// ----------------------------------------------------------------------------
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// The software is delivered "AS IS" without warranty or condition of any
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// kind, either express, implied or statutory. This includes without
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// limitation any warranty or condition with respect to merchantability or
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// fitness for any particular purpose, or against the infringements of
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// intellectual property rights of others.
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// ----------------------------------------------------------------------------
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// File Name : Cstartup_SAM7.c
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// Object : Low level initializations written in C for IAR tools
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// 1.0 08/Sep/04 JPP : Creation
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// 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
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// ----------------------------------------------------------------------------
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// Include the board file description
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#include "AT91SAM7S256.h"
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#include "Board.h"
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// The following functions must be write in ARM mode this function called directly
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// by exception vector
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extern void AT91F_Spurious_handler(
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void);
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extern void AT91F_Default_IRQ_handler(
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void);
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extern void AT91F_Default_FIQ_handler(
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void);
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//*----------------------------------------------------------------------------
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//* \fn AT91F_LowLevelInit
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//* \brief This function performs very low level HW initialization
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//* this function can be use a Stack, depending the compilation
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//* optimization mode
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//*----------------------------------------------------------------------------
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void LowLevelInit(
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void)
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{
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int i;
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AT91PS_PMC pPMC = AT91C_BASE_PMC;
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//* Set Flash Wait sate
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// Single Cycle Access at Up to 30 MHz, or 40
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// if MCK = 48054841 I have 50 Cycle for 1 usecond ( flied MC_FMR->FMCN
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// result: AT91C_MC_FMR = 0x00320100 (MC Flash Mode Register)
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AT91C_BASE_MC->MC_FMR =
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(((AT91C_MC_FMCN) & (50 << 16)) | AT91C_MC_FWS_1FWS);
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//* Watchdog Disable
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// result: AT91C_WDTC_WDMR = 0x00008000 (Watchdog Mode Register)
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AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
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//* Set MCK at 48 054 841
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// 1 Enabling the Main Oscillator:
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// SCK = 1/32768 = 30.51 uSecond
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// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
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// result: AT91C_CKGR_MOR = 0x00000601 (Main Oscillator Register)
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pPMC->PMC_MOR = ((AT91C_CKGR_OSCOUNT & (0x06 << 8)) | AT91C_CKGR_MOSCEN);
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// Wait the startup time
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while (!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
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// PMC Clock Generator PLL Register setup
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//
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// The following settings are used: DIV = 14
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// MUL = 72
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// PLLCOUNT = 10
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//
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// Main Clock (MAINCK from crystal oscillator) = 18432000 hz (see AT91SAM7-EK schematic)
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// MAINCK / DIV = 18432000/14 = 1316571 hz
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// PLLCK = 1316571 * (MUL + 1) = 1316571 * (72 + 1) = 1316571 * 73 = 96109683 hz
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//
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// PLLCOUNT = number of slow clock cycles before the LOCK bit is set
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// in PMC_SR after CKGR_PLLR is written.
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//
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// PLLCOUNT = 10
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//
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// OUT = 0 (not used)
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// result: AT91C_CKGR_PLLR = 0x00000000480A0E (PLL Register)
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pPMC->PMC_PLLR =
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((AT91C_CKGR_DIV & 14) | (AT91C_CKGR_PLLCOUNT & (10 << 8)) |
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(AT91C_CKGR_MUL & (72 << 16)));
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// Wait the startup time (until PMC Status register LOCK bit is set)
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while (!(pPMC->PMC_SR & AT91C_PMC_LOCK));
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// PMC Master Clock (MCK) Register setup
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//
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// CSS = 3 (PLLCK clock selected)
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//
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// PRES = 1 (MCK = PLLCK / 2) = 96109683/2 = 48054841 hz
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//
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// Note: Master Clock MCK = 48054841 hz (this is the CPU clock speed)
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// result: AT91C_PMC_MCKR = 0x00000007 (Master Clock Register)
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pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2;
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// Set up the default interrupts handler vectors
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AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler;
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for (i = 1; i < 31; i++) {
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AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler;
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}
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AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler;
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}
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