skarg
251 lines
8.4 KiB
C
251 lines
8.4 KiB
C
/**************************************************************************
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*
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* Copyright (C) 2003 Mark Norton and Steve Karg
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Functional
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* Description: Defines the hardware implementation for the Microchip
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* microprocessor used in the Synergy lighting control project.
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*
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*********************************************************************/
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#ifndef HARDWARE_H
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#define HARDWARE_H
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#include <p18F452.h>
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#include <portb.h>
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#include <timers.h>
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/****************************************************************************
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* Card IO *
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****************************************************************************/
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/*
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TRIS masks are:
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0 = OUTPUT
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1 = INPUT
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The IO on this card is as follows:
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RA0 - SDA - SEEPROM (input)
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RA1 - SCL - SEEPROM (input)
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RA2 - not used (input)
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RA3 - not used (input)
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RA4 - LK2a - jumper (input)
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RA5 - LK2b - jumper (input)
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TRISA - 0011 1111 - 3Fh
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RB0 - INT - Zero Cross Interrupt (input)
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RB1 - LED - I2C Bus Indication (output)
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RB2 - LED - Labeled 'DATA' (output)
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RB3 - not used (input)
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RB4 - CTS input for RS-232 (not used unless LT1180A chip is there)
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RB5 - RTS output for RS-232 (not used unless LT1180A chip is there)
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RB6 - PGC - in circuit programming (input)
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RB7 - PGD - in circuit programming (input)
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TRISB - 1101 1001 - D9h
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RC0 - QH of 74165 shift register (input)
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RC1 - SHIFTREG_CKL of 74165 shift register (output)
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RC2 - SHIFTREG_LOAD of 74165 shift register (output)
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RC3 - SCL for I2C bus (input)
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RC4 - SDA for I2C bus (input)
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RC5 - RS-485 TXEN (or RS232) (output)
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RC6 - RS-485 TXD (or RS232) (output)
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RC7 - RS-485 RXD (or RS232) (input)
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TRISC - 1001 1001 - 99h
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*/
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#define PORT_A_TRIS_MASK 0x3F
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#define PORT_B_TRIS_MASK 0xD9
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#define PORT_C_TRIS_MASK 0x99
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/* hardware mapping of functionality */
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#define DATA_LED_ON() PORTBbits.RB2=0
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#define DATA_LED_OFF() PORTBbits.RB2=1
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#define ABUS_LED_ON() PORTBbits.RB1=0
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#define ABUS_LED_OFF() PORTBbits.RB1=1
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#define RS485_TRANSMIT_DISABLE() PORTCbits.RC5=0
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#define RS485_TRANSMIT_ENABLE() PORTCbits.RC5=1
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/* note: board is inverted logic */
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#define JUMPER_LK2_TOP_OFF() PORTAbits.RA4
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#define JUMPER_LK2_TOP_ON() (!PORTAbits.RA4)
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#define JUMPER_LK2_BOTTOM_OFF() PORTAbits.RA5
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#define JUMPER_LK2_BOTTOM_ON() (!PORTAbits.RA5)
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#define ZERO_CROSS PORTBbits.RB0
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#define I2C_CLK_LATCH LATCbits.LATC3
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#define I2C_DATA_LATCH LATCbits.LATC4
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#define I2C_CLK PORTCbits.RC3
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#define I2C_DATA PORTCbits.RC4
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#define I2C_CLK_HI_Z TRISCbits.TRISC3
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#define I2C_SDA_HI_Z TRISCbits.TRISC4
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#define EEPROM_DATA_LATCH LATAbits.LATA0
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#define EEPROM_CLK_LATCH LATAbits.LATA1
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#define EEPROM_SDA PORTAbits.RA0
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#define EEPROM_CLK PORTAbits.RA1
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#define EEPROM_SDA_HI_Z TRISAbits.TRISA0
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#define EEPROM_CLK_HI_Z TRISAbits.TRISA1
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#define SHIFTREG_LOAD PORTCbits.RC2
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#define SHIFTREG_CLK PORTCbits.RC1
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#define SHIFTREG_DATA PORTCbits.RC0
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#define NO_ANALOGS 0x06 // None
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#define ALL_ANALOG 0x00 // RA0 RA1 RA2 RA3 RA5 RE0 RE1 RE2 Ref=Vdd
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#define ANALOG_RA3_REF 0x01 // RA0 RA1 RA2 RA5 RE0 RE1 RE2 Ref=RA3
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#define A_ANALOG 0x02 // RA0 RA1 RA2 RA3 RA5 Ref=Vdd
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#define A_ANALOG_RA3_REF 0x03 // RA0 RA1 RA2 RA5 Ref=RA3
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#define RA0_RA1_RA3_ANALOG 0x04 // RA0 RA1 RA3 Ref=Vdd
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#define RA0_RA1_ANALOG_RA3_REF 0x05 // RA0 RA1 Ref=RA3
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#define ANALOG_RA3_RA2_REF 0x08
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#define ANALOG_NOT_RE1_RE2 0x09
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#define ANALOG_NOT_RE1_RE2_REF_RA3 0x0A
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#define ANALOG_NOT_RE1_RE2_REF_RA3_RA2 0x0B
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#define A_ANALOG_RA3_RA2_REF 0x0C
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#define RA0_RA1_ANALOG_RA3_RA2_REF 0x0D
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#define RA0_ANALOG 0x0E
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#define RA0_ANALOG_RA3_RA2_REF 0x0F
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// Constants used for SETUP_ADC() are:
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#define ADC_OFF 0
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#define ADC_START 4
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#define ADC_CLOCK_DIV_2 1
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#define ADC_CLOCK_DIV_4 0x101
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#define ADC_CLOCK_DIV_8 0x41
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#define ADC_CLOCK_DIV_16 0x141
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#define ADC_CLOCK_DIV_32 0x81
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#define ADC_CLOCK_DIV_64 0x181
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#define ADC_CLOCK_INTERNAL 0xc1
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#define ADC_DONE_MASK 0x04
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#define SET_ADC_CHAN(x) ADCON0 = (ADC_CLOCK_DIV_32 | ((x) << 3))
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#define T1_DISABLED 0
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#define T1_INTERNAL 0x85
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#define T1_EXTERNAL 0x87
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#define T1_EXTERNAL_SYNC 0x83
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#define T1_CLK_OUT 8
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#define T1_DIV_BY_1 0
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#define T1_DIV_BY_2 0x10
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#define T1_DIV_BY_4 0x20
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#define T1_DIV_BY_8 0x30
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#define SETUP_TIMER1(mode) T1CON = (mode)
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#define T2_DISABLED 0
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#define T2_DIV_BY_1 4
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#define T2_DIV_BY_4 5
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#define T2_DIV_BY_16 6
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#define SETUP_TIMER2(mode, period, postscale) \
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{ \
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T2CON = ((mode) | ((postscale)-1)<<3); \
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PR2 = (period); \
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}
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#define T3_DISABLED 0
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#define T3_INTERNAL 0x85
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#define T3_EXTERNAL 0x87
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#define T3_EXTERNAL_SYNC 0x83
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#define T3_DIV_BY_1 0
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#define T3_DIV_BY_2 0x10
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#define T3_DIV_BY_4 0x20
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#define T3_DIV_BY_8 0x30
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#define SETUP_TIMER3(mode) T3CON = (mode)
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#define CCP_OFF 0
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#define CCP_CAPTURE_FE 4
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#define CCP_CAPTURE_RE 5
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#define CCP_CAPTURE_DIV_4 6
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#define CCP_CAPTURE_DIV_16 7
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#define CCP_COMPARE_SET_ON_MATCH 8
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#define CCP_COMPARE_CLR_ON_MATCH 9
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#define CCP_COMPARE_INT 0xA
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#define CCP_COMPARE_RESET_TIMER 0xB
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#define CCP_PWM 0xC
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#define CCP_PWM_PLUS_1 0x1c
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#define CCP_PWM_PLUS_2 0x2c
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#define CCP_PWM_PLUS_3 0x3c
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#define SETUP_CCP1(mode) CCP1CON = (mode)
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#define SETUP_CCP2(mode) CCP2CON = (mode)
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#define WATCHDOG_TIMER() \
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{ \
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_asm \
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CLRWDT \
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_endasm \
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}
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#define GLOBAL_INT_ENABLE() INTCONbits.GIE = 1
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#define GLOBAL_INT_DISABLE() INTCONbits.GIE = 0
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#define PERIPHERAL_INT_ENABLE() INTCONbits.PEIE = 1
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#define PERIPHERAL_INT_DISABLE() INTCONbits.PEIE = 0
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#define TIMER0_INT_ENABLE() INTCONbits.TMR0IE = 1
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#define TIMER0_INT_DISABLE() INTCONbits.TMR0IE = 0
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#define TIMER2_INT_ENABLE() PIE1bits.TMR2IE = 1
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#define TIMER2_INT_DISABLE() PIE1bits.TMR2IE = 0
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#define CCP2_INT_ENABLE() PIE2bits.CCP2IE = 1
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#define CCP2_INT_DISABLE() PIE2bits.CCP2IE = 0
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#define CCP1_INT_ENABLE() PIE1bits.CCP1IE = 1
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#define CCP1_INT_DISABLE() PIE1bits.CCP1IE = 0
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#define ABUS_INT_ENABLE() PIE1bits.SSPIE = 1
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#define ABUS_INT_DISABLE() PIE1bits.SSPIE = 0
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#define ABUS_INT_FLAG_CLEAR() PIR1bits.SSPIF = 0
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#define USART_RX_INT_DISABLE() PIE1bits.RCIE = 0
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#define USART_RX_INT_ENABLE() PIE1bits.RCIE = 1
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#define USART_TX_INTERRUPT() PIE1bits.TXIE
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#define USART_TX_INT_DISABLE() PIE1bits.TXIE = 0
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#define USART_TX_INT_ENABLE() PIE1bits.TXIE = 1
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#define USART_TX_ENABLE() TXSTAbits.TXEN = 1
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#define USART_TX_INT_FLAG_CLEAR() PIR1bits.TXIF = 0
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#define USART_TX_EMPTY() TXSTAbits.TRMT
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#define USART_CONTINUOUS_RX_ENABLE() RCSTAbits.CREN = 1
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#define USART_CONTINUOUS_RX_DISABLE() RCSTAbits.CREN = 0
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#define USART_RX_COMPLETE() PIR1bits.RCIF
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#define USART_RX_STATUS() RCSTAbits
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#define USART_RX_STATUS() RCSTAbits
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#define USART_TRANSMIT(x) TXREG = (x)
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#define USART_RECEIVE() RCREG
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#define USART_RX_FRAME_ERROR() rcstabits.FERR
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// combine the sequence correctly
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#define USART_RX_SETUP() PIE1bits.RCIE = 1; RCSTAbits.CREN = 1
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#define USART_TX_SETUP() PIE1bits.TXIE = 1; TXSTAbits.TXEN = 1
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#endif /* HARDWARE_H */
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