Kari Argillander
cb243c36a8
* Change MIT license texts to SPDX-License-Identifier SPDX-License-Identifier is much easier to understand and grep than license text so use that instead. * Change GPL exception license texts to SPDX-License-Identifier SPDX-License-Identifier is much easier to understand and grep than license text so use that instead. * Change misc license texts to SPDX-License-Identifier There are some external code in repo which are not licenses as most of the stuff in this repo. We still want every file to have SPDX identifier to easily grep licenses. * Add currently used license files Even though Bacnet-Stack is using SPDX identifiers we still need to give those license files with source. For this reason add all license files to license/ folder. SPDX has also files which would make same thing but this is style which example Linux kernel is using and it is quite clear so I choose that one for now. I choosed not yet bring CC-PDDC as that is not right license for those files. --------- Co-authored-by: Kari Argillander <kari.argillander@fidelix.com>
152 lines
3.9 KiB
C
152 lines
3.9 KiB
C
/**************************************************************************
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*
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* Copyright (C) 2009 Steve Karg <skarg@users.sourceforge.net>
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*
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* SPDX-License-Identifier: MIT
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*
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*********************************************************************/
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#include <stdbool.h>
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#include <stdint.h>
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#include "hardware.h"
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/* me */
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#include "adc.h"
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/* prescale select bits */
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#if (F_CPU >> 1) < 1000000
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#define ADPS_8BIT (1)
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#define ADPS_10BIT (3)
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#elif (F_CPU >> 2) < 1000000
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#define ADPS_8BIT (2)
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#define ADPS_10BIT (4)
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#elif (F_CPU >> 3) < 1000000
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#define ADPS_8BIT (3)
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#define ADPS_10BIT (5)
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#elif (F_CPU >> 4) < 1000000
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#define ADPS_8BIT (4)
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#define ADPS_10BIT (6)
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#elif (F_CPU >> 5) < 1000000
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#define ADPS_8BIT (5)
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#define ADPS_10BIT (7)
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#else
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#error "ADC: F_CPU too large for accuracy."
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#endif
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/* Array of ADC results */
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#define ADC_CHANNELS_MAX 8
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static volatile uint16_t Sample_Result[ADC_CHANNELS_MAX];
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static volatile uint8_t Enabled_Channels;
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ISR(ADC_vect)
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{
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uint8_t index;
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uint8_t mask;
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uint8_t channels;
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uint16_t value = 0;
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/* determine which conversion finished */
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index = BITMASK_CHECK(ADMUX, ((1 << MUX2) | (1 << MUX1) | (1 << MUX0)));
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/* read the results */
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value = ADCL;
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value |= (ADCH << 8);
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Sample_Result[index] = value;
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channels = Enabled_Channels;
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__enable_interrupt();
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/* clear the mux */
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BITMASK_CLEAR(ADMUX, ((1 << MUX2) | (1 << MUX1) | (1 << MUX0)));
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/* find the next enabled channel */
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while (channels) {
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index++;
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if (index >= ADC_CHANNELS_MAX) {
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index = 0;
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}
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mask = 1 << index;
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if (channels & mask) {
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break;
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}
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}
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/* configure the next channel */
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BITMASK_SET(ADMUX, ((index) << MUX0));
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/* Start the next conversion */
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BIT_SET(ADCSRA, ADSC);
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}
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void adc_enable(uint8_t index)
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{ /* 0..7 = ADC0..ADC7, respectively */
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if (Enabled_Channels) {
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/* ADC interupt is already started */
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BIT_SET(Enabled_Channels, index);
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} else {
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if (index < ADC_CHANNELS_MAX) {
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/* not running yet */
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BIT_SET(Enabled_Channels, index);
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/* clear the mux */
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BITMASK_CLEAR(ADMUX, ((1 << MUX2) | (1 << MUX1) | (1 << MUX0)));
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/* configure the channel */
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BITMASK_SET(ADMUX, ((index) << MUX0));
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/* Start the next conversion */
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BIT_SET(ADCSRA, ADSC);
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}
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}
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}
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uint8_t adc_result_8bit(uint8_t index)
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{ /* 0..7 = ADC0..ADC7, respectively */
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uint8_t result = 0;
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uint8_t sreg;
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if (index < ADC_CHANNELS_MAX) {
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adc_enable(index);
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sreg = SREG;
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__disable_interrupt();
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result = (uint8_t)(Sample_Result[index] >> 2);
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SREG = sreg;
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}
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return result;
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}
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uint16_t adc_result_10bit(uint8_t index)
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{ /* 0..7 = ADC0..ADC7, respectively */
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uint16_t result = 0;
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uint8_t sreg;
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if (index < ADC_CHANNELS_MAX) {
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adc_enable(index);
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sreg = SREG;
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__disable_interrupt();
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result = Sample_Result[index];
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SREG = sreg;
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}
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return result;
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}
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void adc_init(void)
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{
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/* Initial channel selection */
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/* ADLAR = Left Adjust Result
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REFSx = hardware setup: cap on AREF
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*/
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ADMUX = (0 << ADLAR) | (0 << REFS1) | (1 << REFS0);
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/* ADEN = Enable
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ADSC = Start conversion
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ADIF = Interrupt Flag - write 1 to clear!
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ADIE = Interrupt Enable
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ADATE = Auto Trigger Enable
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*/
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ADCSRA =
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(1 << ADEN) | (1 << ADIE) | (1 << ADIF) | (0 << ADATE) | ADPS_10BIT;
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/* trigger selection bits
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0 0 0 Free Running mode
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0 0 1 Analog Comparator
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0 1 0 External Interrupt Request 0
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0 1 1 Timer/Counter0 Compare Match
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1 0 0 Timer/Counter0 Overflow
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1 0 1 Timer/Counter1 Compare Match B
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1 1 0 Timer/Counter1 Overflow
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1 1 1 Timer/Counter1 Capture Event
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*/
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ADCSRB = (0 << ADTS2) | (0 << ADTS1) | (0 << ADTS0);
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power_adc_enable();
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}
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