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Kari Argillander 369da70f2a Strip tabs and trailing white spaces, and fix end of files (#748) 
* format: Strip trailing whitespaces

We want to get rid of trailing whitespaces completly as they make just git
noice. Much better to start using automated tools to get rid of them once and
not getting them back again. This way git history will be cleaner and review
easier.

Commit was generated with:

    pre-commit run --all-files trailing-whitespace

* format: Files should have exactly one new line end of them

It is good practice that every file has one new line. It is not now days so
mandatory but it also is not nice if file has lot of newlines end of it. We will
use pre-commit which takes automatically care about this so let's fix all.

Commit was generated with:

    pre-commit run --all-files end-of-file-fixer

* format: Convert tabs to spaces

Project mostly use spaces over tabs. When mixing tabs and spaces this usually
makes formatting issues and also when changing those in commits it will make lot
of git noise. We will force spaces most of the time and use pre-commit to fix.

Commit was generated with:

    pre-commit run --all-files remove-tabs

---------

Co-authored-by: Kari Argillander <kari.argillander@fidelix.com>
2024-08-25 14:13:57 -05:00

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<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32F429</name>
<version>1.2</version>
<description>STM32F429</description>
<cpu>
<name>CM4</name>
<revision>r1p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>0x20</size>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>RNG</name>
<description>Random number generator</description>
<groupName>RNG</groupName>
<baseAddress>0x50060800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FPU</name>
<description>FPU interrupt</description>
<value>81</value>
</interrupt>
<interrupt>
<name>FPU</name>
<description>FPU interrupt</description>
<value>81</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IE</name>
<description>Interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RNG interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RNG interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RNGEN</name>
<description>Random number generator
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RNGEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Random number generator is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Random number generator is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEIS</name>
<description>Seed error interrupt
status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CEIS</name>
<description>Clock error interrupt
status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SECS</name>
<description>Seed error current status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CECS</name>
<description>Clock error current status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DRDY</name>
<description>Data ready</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>data register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RNDATA</name>
<description>Random data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>HASH</name>
<description>Hash processor</description>
<groupName>HASH</groupName>
<baseAddress>0x50060400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>HASH_RNG</name>
<description>Hash and Rng global interrupt</description>
<value>80</value>
</interrupt>
<interrupt>
<name>HASH_RNG</name>
<description>Hash and Rng global interrupt</description>
<value>80</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INIT</name>
<description>Initialize message digest
calculation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>DMAE</name>
<description>DMA enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATATYPE</name>
<description>Data type selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MODE</name>
<description>Mode selection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALGO0</name>
<description>Algorithm selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NBW</name>
<description>Number of words already
pushed</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DINNE</name>
<description>DIN not empty</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MDMAT</name>
<description>Multiple DMA Transfers</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LKEY</name>
<description>Long key selection</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALGO1</name>
<description>ALGO</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIN</name>
<displayName>DIN</displayName>
<description>data input register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATAIN</name>
<description>Data input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STR</name>
<displayName>STR</displayName>
<description>start register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DCAL</name>
<description>Digest calculation</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>NBLW</name>
<description>Number of valid bits in the last word of
the message</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>5</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4</dimIndex><name>HR%s</name>
<displayName>HR0</displayName>
<description>digest registers</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>H</name>
<description>H0</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMR</name>
<displayName>IMR</displayName>
<description>interrupt enable register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DCIE</name>
<description>Digest calculation completion interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DINIE</name>
<description>Data input interrupt
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>BUSY</name>
<description>Busy bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DMAS</name>
<description>DMA Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DCIS</name>
<description>Digest calculation completion interrupt
status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DINIS</name>
<description>Data input interrupt
status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>54</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53</dimIndex><name>CSR%s</name>
<displayName>CSR0</displayName>
<description>context swap registers</description>
<addressOffset>0xF8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSR</name>
<description>CSR0</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>8</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4,5,6,7</dimIndex><name>HASH_HR%s</name>
<displayName>HASH_HR0</displayName>
<description>HASH digest register</description>
<addressOffset>0x310</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>H</name>
<description>H0</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRYP</name>
<description>Cryptographic processor</description>
<groupName>CRYP</groupName>
<baseAddress>0x50060000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CRYP</name>
<description>CRYP crypto global interrupt</description>
<value>79</value>
</interrupt>
<interrupt>
<name>CRYP</name>
<description>CRYP crypto global interrupt</description>
<value>79</value>
</interrupt>
<registers>
<cluster><dim>4</dim><dimIncrement>0x8</dimIncrement><dimIndex>0,1,2,3</dimIndex><name>KEY%s</name><description>Cluster KEY%s, containing K?LR, K?RR</description><addressOffset>0x20</addressOffset><register>
<name>KLR</name>
<displayName>K0LR</displayName>
<description>key registers</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>b2</name><description>b224</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields>
</register>
<register>
<name>KRR</name>
<displayName>K0RR</displayName>
<description>key registers</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>b</name><description>b192</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields>
</register>
</cluster><cluster><dim>2</dim><dimIncrement>0x8</dimIncrement><dimIndex>0,1</dimIndex><name>INIT%s</name><description>Cluster INIT%s, containing IV?LR, IV?RR</description><addressOffset>0x40</addressOffset><register>
<name>IVLR</name>
<displayName>IV0LR</displayName>
<description>initialization vector
registers</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>IV</name><description>IV31</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields>
</register>
<register>
<name>IVRR</name>
<displayName>IV0RR</displayName>
<description>initialization vector
registers</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>IV</name><description>IV63</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields>
</register>
</cluster><register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALGODIR</name>
<description>Algorithm direction</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALGOMODE0</name>
<description>Algorithm mode</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATATYPE</name>
<description>Data type selection</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>KEYSIZE</name>
<description>Key size selection (AES mode
only)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FFLUSH</name>
<description>FIFO flush</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CRYPEN</name>
<description>Cryptographic processor
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GCM_CCMPH</name>
<description>GCM_CCMPH</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALGOMODE3</name>
<description>ALGOMODE</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000003</resetValue>
<fields>
<field>
<name>BUSY</name>
<description>Busy bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFFU</name>
<description>Output FIFO full</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFNE</name>
<description>Output FIFO not empty</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IFNF</name>
<description>Input FIFO not full</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IFEM</name>
<description>Input FIFO empty</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIN</name>
<displayName>DIN</displayName>
<description>data input register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATAIN</name>
<description>Data input</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOUT</name>
<displayName>DOUT</displayName>
<description>data output register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATAOUT</name>
<description>Data output</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMACR</name>
<displayName>DMACR</displayName>
<description>DMA control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DOEN</name>
<description>DMA output enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIEN</name>
<description>DMA input enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMSCR</name>
<displayName>IMSCR</displayName>
<description>interrupt mask set/clear
register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTIM</name>
<description>Output FIFO service interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INIM</name>
<description>Input FIFO service interrupt
mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RISR</name>
<displayName>RISR</displayName>
<description>raw interrupt status register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>OUTRIS</name>
<description>Output FIFO service raw interrupt
status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INRIS</name>
<description>Input FIFO service raw interrupt
status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MISR</name>
<displayName>MISR</displayName>
<description>masked interrupt status
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTMIS</name>
<description>Output FIFO service masked interrupt
status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INMIS</name>
<description>Input FIFO service masked interrupt
status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<dim>8</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4,5,6,7</dimIndex><name>CSGCMCCM%sR</name>
<displayName>CSGCMCCM0R</displayName>
<description>context swap register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSGCMCCM0R</name>
<description>CSGCMCCM0R</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>8</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4,5,6,7</dimIndex><name>CSGCM%sR</name>
<displayName>CSGCM0R</displayName>
<description>context swap register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSGCMR</name>
<description>CSGCM0R</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DCMI</name>
<description>Digital camera interface</description>
<groupName>DCMI</groupName>
<baseAddress>0x50050000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DCMI</name>
<description>DCMI global interrupt</description>
<value>78</value>
</interrupt>
<interrupt>
<name>DCMI</name>
<description>DCMI global interrupt</description>
<value>78</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>DCMI enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EDM</name>
<description>Extended data mode</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FCRC</name>
<description>Frame capture rate control</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>VSPOL</name>
<description>Vertical synchronization
polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSPOL</name>
<description>Horizontal synchronization
polarity</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCKPOL</name>
<description>Pixel clock polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESS</name>
<description>Embedded synchronization
select</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JPEG</name>
<description>JPEG format</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CROP</name>
<description>Crop feature</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CM</name>
<description>Capture mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAPTURE</name>
<description>Capture enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>FNE</name>
<description>FIFO not empty</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC</name>
<description>VSYNC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSYNC</name>
<description>HSYNC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RIS</name>
<displayName>RIS</displayName>
<description>raw interrupt status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LINE_RIS</name>
<description>Line raw interrupt status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC_RIS</name>
<description>VSYNC raw interrupt status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERR_RIS</name>
<description>Synchronization error raw interrupt
status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_RIS</name>
<description>Overrun raw interrupt
status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME_RIS</name>
<description>Capture complete raw interrupt
status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LINE_IE</name>
<description>Line interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC_IE</name>
<description>VSYNC interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERR_IE</name>
<description>Synchronization error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_IE</name>
<description>Overrun interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME_IE</name>
<description>Capture complete interrupt
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MIS</name>
<displayName>MIS</displayName>
<description>masked interrupt status
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LINE_MIS</name>
<description>Line masked interrupt
status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC_MIS</name>
<description>VSYNC masked interrupt
status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERR_MIS</name>
<description>Synchronization error masked interrupt
status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_MIS</name>
<description>Overrun masked interrupt
status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME_MIS</name>
<description>Capture complete masked interrupt
status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>interrupt clear register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LINE_ISC</name>
<description>line interrupt status
clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VSYNC_ISC</name>
<description>Vertical synch interrupt status
clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERR_ISC</name>
<description>Synchronization error interrupt status
clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OVR_ISC</name>
<description>Overrun interrupt status
clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRAME_ISC</name>
<description>Capture complete interrupt status
clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ESCR</name>
<displayName>ESCR</displayName>
<description>embedded synchronization code
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>FEC</name>
<description>Frame end delimiter code</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LEC</name>
<description>Line end delimiter code</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LSC</name>
<description>Line start delimiter code</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FSC</name>
<description>Frame start delimiter code</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ESUR</name>
<displayName>ESUR</displayName>
<description>embedded synchronization unmask
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>FEU</name>
<description>Frame end delimiter unmask</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LEU</name>
<description>Line end delimiter unmask</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>LSU</name>
<description>Line start delimiter
unmask</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FSU</name>
<description>Frame start delimiter
unmask</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CWSTRT</name>
<displayName>CWSTRT</displayName>
<description>crop window start</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>VST</name>
<description>Vertical start line count</description>
<bitOffset>16</bitOffset>
<bitWidth>13</bitWidth>
</field>
<field>
<name>HOFFCNT</name>
<description>Horizontal offset count</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>CWSIZE</name>
<displayName>CWSIZE</displayName>
<description>crop window size</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>VLINE</name>
<description>Vertical line count</description>
<bitOffset>16</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>CAPCNT</name>
<description>Capture count</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>data register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>Byte3</name>
<description>Data byte 3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>Byte2</name>
<description>Data byte 2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>Byte1</name>
<description>Data byte 1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>Byte0</name>
<description>Data byte 0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FMC</name>
<description>Flexible memory controller</description>
<groupName>FSMC</groupName>
<baseAddress>0xA0000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FMC</name>
<description>FMC global interrupt</description>
<value>48</value>
</interrupt>
<interrupt>
<name>FMC</name>
<description>FMC global interrupt</description>
<value>48</value>
</interrupt>
<registers>
<register>
<name>BCR1</name>
<displayName>BCR1</displayName>
<description>SRAM/NOR-Flash chip-select control register
1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000030D0</resetValue>
<fields>
<field>
<name>CCLKEN</name>
<description>CCLKEN</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CBURSTRW</name>
<description>CBURSTRW</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CBURSTRW</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Write operations are performed in synchronous mode</description><value>1</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Write operations are always performed in asynchronous mode</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ASYNCWAIT</name>
<description>ASYNCWAIT</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ASYNCWAIT</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wait signal not used in asynchronous mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wait signal used even in asynchronous mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EXTMOD</name>
<description>EXTMOD</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EXTMOD</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Values inside the FMC_BWTR are not taken into account</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Values inside the FMC_BWTR are taken into account</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WAITEN</name>
<description>WAITEN</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WAITEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Values inside the FMC_BWTR are taken into account</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>NWAIT signal enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WREN</name>
<description>WREN</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Write operations disabled for the bank by the FMC</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Write operations enabled for the bank by the FMC</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WAITCFG</name>
<description>WAITCFG</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WAITCFG</name><usage>read-write</usage><enumeratedValue><name>BeforeWaitState</name><description>NWAIT signal is active one data cycle before wait state</description><value>0</value></enumeratedValue><enumeratedValue><name>DuringWaitState</name><description>NWAIT signal is active during wait state</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WAITPOL</name>
<description>WAITPOL</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WAITPOL</name><usage>read-write</usage><enumeratedValue><name>ActiveLow</name><description>NWAIT active low</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveHigh</name><description>NWAIT active high</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BURSTEN</name>
<description>BURSTEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BURSTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Burst mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Burst mode enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FACCEN</name>
<description>FACCEN</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FACCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Corresponding NOR Flash memory access is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Corresponding NOR Flash memory access is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MWID</name>
<description>MWID</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>MWID</name><usage>read-write</usage><enumeratedValue><name>Bits8</name><description>Memory data bus width 8 bits</description><value>0</value></enumeratedValue><enumeratedValue><name>Bits16</name><description>Memory data bus width 16 bits</description><value>1</value></enumeratedValue><enumeratedValue><name>Bits32</name><description>Memory data bus width 32 bits</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MTYP</name>
<description>MTYP</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>MTYP</name><usage>read-write</usage><enumeratedValue><name>SRAM</name><description>SRAM memory type</description><value>0</value></enumeratedValue><enumeratedValue><name>PSRAM</name><description>PSRAM (CRAM) memory type</description><value>1</value></enumeratedValue><enumeratedValue><name>Flash</name><description>NOR Flash/OneNAND Flash</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MUXEN</name>
<description>MUXEN</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MUXEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Address/Data non-multiplexed</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address/Data multiplexed on databus</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MBKEN</name>
<description>MBKEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MBKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Corresponding memory bank is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Corresponding memory bank is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field><name>WRAPMOD</name><description>WRAPMOD</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field>
<field><name>CPSIZE</name><description>CRAM page size</description><bitOffset>16</bitOffset><bitWidth>3</bitWidth><access>read-write</access><enumeratedValues><name>CPSIZE</name><usage>read-write</usage><enumeratedValue><name>NoBurstSplit</name><description>No burst split when crossing page boundary</description><value>0</value></enumeratedValue><enumeratedValue><name>Bytes128</name><description>128 bytes CRAM page size</description><value>1</value></enumeratedValue><enumeratedValue><name>Bytes256</name><description>256 bytes CRAM page size</description><value>2</value></enumeratedValue><enumeratedValue><name>Bytes512</name><description>512 bytes CRAM page size</description><value>3</value></enumeratedValue><enumeratedValue><name>Bytes1024</name><description>1024 bytes CRAM page size</description><value>4</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim><dimIncrement>0x8</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>BTR%s</name>
<displayName>BTR1</displayName>
<description>SRAM/NOR-Flash chip-select timing register
1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>ACCMOD</name>
<description>ACCMOD</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>ACCMOD</name><usage>read-write</usage><enumeratedValue><name>A</name><description>Access mode A</description><value>0</value></enumeratedValue><enumeratedValue><name>B</name><description>Access mode B</description><value>1</value></enumeratedValue><enumeratedValue><name>C</name><description>Access mode C</description><value>2</value></enumeratedValue><enumeratedValue><name>D</name><description>Access mode D</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DATLAT</name>
<description>DATLAT</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>CLKDIV</name>
<description>CLKDIV</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>BUSTURN</name>
<description>BUSTURN</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>DATAST</name>
<description>DATAST</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>ADDHLD</name>
<description>ADDHLD</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>ADDSET</name>
<description>ADDSET</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<dim>3</dim><dimIncrement>0x8</dimIncrement><dimIndex>2,3,4</dimIndex><name>BCR%s</name>
<displayName>BCR2</displayName>
<description>SRAM/NOR-Flash chip-select control register
2</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000030D0</resetValue>
<fields>
<field>
<name>CBURSTRW</name>
<description>CBURSTRW</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CBURSTRW</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Write operations are performed in synchronous mode</description><value>1</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Write operations are always performed in asynchronous mode</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ASYNCWAIT</name>
<description>ASYNCWAIT</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ASYNCWAIT</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wait signal not used in asynchronous mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wait signal used even in asynchronous mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EXTMOD</name>
<description>EXTMOD</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EXTMOD</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Values inside the FMC_BWTR are not taken into account</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Values inside the FMC_BWTR are taken into account</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WAITEN</name>
<description>WAITEN</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WAITEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Values inside the FMC_BWTR are taken into account</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>NWAIT signal enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WREN</name>
<description>WREN</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Write operations disabled for the bank by the FMC</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Write operations enabled for the bank by the FMC</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WAITCFG</name>
<description>WAITCFG</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WAITCFG</name><usage>read-write</usage><enumeratedValue><name>BeforeWaitState</name><description>NWAIT signal is active one data cycle before wait state</description><value>0</value></enumeratedValue><enumeratedValue><name>DuringWaitState</name><description>NWAIT signal is active during wait state</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WRAPMOD</name>
<description>WRAPMOD</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAITPOL</name>
<description>WAITPOL</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WAITPOL</name><usage>read-write</usage><enumeratedValue><name>ActiveLow</name><description>NWAIT active low</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveHigh</name><description>NWAIT active high</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BURSTEN</name>
<description>BURSTEN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BURSTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Burst mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Burst mode enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FACCEN</name>
<description>FACCEN</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FACCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Corresponding NOR Flash memory access is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Corresponding NOR Flash memory access is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MWID</name>
<description>MWID</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>MWID</name><usage>read-write</usage><enumeratedValue><name>Bits8</name><description>Memory data bus width 8 bits</description><value>0</value></enumeratedValue><enumeratedValue><name>Bits16</name><description>Memory data bus width 16 bits</description><value>1</value></enumeratedValue><enumeratedValue><name>Bits32</name><description>Memory data bus width 32 bits</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MTYP</name>
<description>MTYP</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>MTYP</name><usage>read-write</usage><enumeratedValue><name>SRAM</name><description>SRAM memory type</description><value>0</value></enumeratedValue><enumeratedValue><name>PSRAM</name><description>PSRAM (CRAM) memory type</description><value>1</value></enumeratedValue><enumeratedValue><name>Flash</name><description>NOR Flash/OneNAND Flash</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MUXEN</name>
<description>MUXEN</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MUXEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Address/Data non-multiplexed</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address/Data multiplexed on databus</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MBKEN</name>
<description>MBKEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MBKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Corresponding memory bank is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Corresponding memory bank is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field><name>CPSIZE</name><description>CRAM page size</description><bitOffset>16</bitOffset><bitWidth>3</bitWidth><access>read-write</access><enumeratedValues><name>CPSIZE</name><usage>read-write</usage><enumeratedValue><name>NoBurstSplit</name><description>No burst split when crossing page boundary</description><value>0</value></enumeratedValue><enumeratedValue><name>Bytes128</name><description>128 bytes CRAM page size</description><value>1</value></enumeratedValue><enumeratedValue><name>Bytes256</name><description>256 bytes CRAM page size</description><value>2</value></enumeratedValue><enumeratedValue><name>Bytes512</name><description>512 bytes CRAM page size</description><value>3</value></enumeratedValue><enumeratedValue><name>Bytes1024</name><description>1024 bytes CRAM page size</description><value>4</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>3</dim><dimIncrement>0x20</dimIncrement><dimIndex>2,3,4</dimIndex><name>PCR%s</name>
<displayName>PCR2</displayName>
<description>PC Card/NAND Flash control register
2</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000018</resetValue>
<fields>
<field>
<name>ECCPS</name>
<description>ECCPS</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>ECCPS</name><usage>read-write</usage><enumeratedValue><name>Bytes256</name><description>ECC page size 256 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>Bytes512</name><description>ECC page size 512 bytes</description><value>1</value></enumeratedValue><enumeratedValue><name>Bytes1024</name><description>ECC page size 1024 bytes</description><value>2</value></enumeratedValue><enumeratedValue><name>Bytes2048</name><description>ECC page size 2048 bytes</description><value>3</value></enumeratedValue><enumeratedValue><name>Bytes4096</name><description>ECC page size 4096 bytes</description><value>4</value></enumeratedValue><enumeratedValue><name>Bytes8192</name><description>ECC page size 8192 bytes</description><value>5</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TAR</name>
<description>TAR</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>TCLR</name>
<description>TCLR</description>
<bitOffset>9</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>ECCEN</name>
<description>ECCEN</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ECCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ECC logic is disabled and reset</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ECC logic is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PWID</name>
<description>PWID</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PWID</name><usage>read-write</usage><enumeratedValue><name>Bits8</name><description>External memory device width 8 bits</description><value>0</value></enumeratedValue><enumeratedValue><name>Bits16</name><description>External memory device width 16 bits</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PTYP</name>
<description>PTYP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PTYP</name><usage>read-write</usage><enumeratedValue><name>NANDFlash</name><description>NAND Flash</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PBKEN</name>
<description>PBKEN</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PBKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Corresponding memory bank is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Corresponding memory bank is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PWAITEN</name>
<description>PWAITEN</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PWAITEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wait feature disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wait feature enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>3</dim><dimIncrement>0x20</dimIncrement><dimIndex>2,3,4</dimIndex><name>SR%s</name>
<displayName>SR2</displayName>
<description>FIFO status and interrupt register
2</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>FEMPT</name>
<description>FEMPT</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>FEMPT</name><usage>read-write</usage><enumeratedValue><name>NotEmpty</name><description>FIFO not empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Empty</name><description>FIFO empty</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IFEN</name>
<description>IFEN</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>IFEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt falling edge detection request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt falling edge detection request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ILEN</name>
<description>ILEN</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>ILEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt high-level detection request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt high-level detection request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IREN</name>
<description>IREN</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>IREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt rising edge detection request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt rising edge detection request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IFS</name>
<description>IFS</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>IFS</name><usage>read-write</usage><enumeratedValue><name>DidNotOccur</name><description>Interrupt falling edge did not occur</description><value>0</value></enumeratedValue><enumeratedValue><name>Occurred</name><description>Interrupt falling edge occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ILS</name>
<description>ILS</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>ILS</name><usage>read-write</usage><enumeratedValue><name>DidNotOccur</name><description>Interrupt high-level did not occur</description><value>0</value></enumeratedValue><enumeratedValue><name>Occurred</name><description>Interrupt high-level occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IRS</name>
<description>IRS</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>IRS</name><usage>read-write</usage><enumeratedValue><name>DidNotOccur</name><description>Interrupt rising edge did not occur</description><value>0</value></enumeratedValue><enumeratedValue><name>Occurred</name><description>Interrupt rising edge occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PMEM2</name>
<displayName>PMEM2</displayName>
<description>Common memory space timing register
2</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFCFCFCFC</resetValue>
<fields>
<field>
<name>MEMHIZ</name>
<description>MEMHIZx</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>MEMHOLD</name>
<description>MEMHOLDx</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>MEMWAIT</name>
<description>MEMWAITx</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>MEMSET</name>
<description>MEMSETx</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PATT2</name>
<displayName>PATT2</displayName>
<description>Attribute memory space timing register
2</description>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFCFCFCFC</resetValue>
<fields>
<field>
<name>ATTHIZ</name>
<description>ATTHIZx</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>ATTHOLD</name>
<description>ATTHOLDx</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>ATTWAIT</name>
<description>ATTWAITx</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>ATTSET</name>
<description>ATTSETx</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ECCR2</name>
<displayName>ECCR2</displayName>
<description>ECC result register 2</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ECC</name>
<description>ECCx</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PMEM3</name>
<displayName>PMEM3</displayName>
<description>Common memory space timing register
3</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFCFCFCFC</resetValue>
<fields>
<field>
<name>MEMHIZ</name>
<description>MEMHIZx</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>MEMHOLD</name>
<description>MEMHOLDx</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>MEMWAIT</name>
<description>MEMWAITx</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>MEMSET</name>
<description>MEMSETx</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PATT3</name>
<displayName>PATT3</displayName>
<description>Attribute memory space timing register
3</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFCFCFCFC</resetValue>
<fields>
<field>
<name>ATTHIZ</name>
<description>ATTHIZx</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>ATTHOLD</name>
<description>ATTHOLDx</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>ATTWAIT</name>
<description>ATTWAITx</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>ATTSET</name>
<description>ATTSETx</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ECCR3</name>
<displayName>ECCR3</displayName>
<description>ECC result register 3</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ECC</name>
<description>ECCx</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PMEM4</name>
<displayName>PMEM4</displayName>
<description>Common memory space timing register
4</description>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFCFCFCFC</resetValue>
<fields>
<field>
<name>MEMHIZ</name>
<description>MEMHIZx</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>MEMHOLD</name>
<description>MEMHOLDx</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>MEMWAIT</name>
<description>MEMWAITx</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>MEMSET</name>
<description>MEMSETx</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PATT4</name>
<displayName>PATT4</displayName>
<description>Attribute memory space timing register
4</description>
<addressOffset>0xAC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFCFCFCFC</resetValue>
<fields>
<field>
<name>ATTHIZ</name>
<description>ATTHIZx</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>ATTHOLD</name>
<description>ATTHOLDx</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>ATTWAIT</name>
<description>ATTWAITx</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint>
</field>
<field>
<name>ATTSET</name>
<description>ATTSETx</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PIO4</name>
<displayName>PIO4</displayName>
<description>I/O space timing register 4</description>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFCFCFCFC</resetValue>
<fields>
<field>
<name>IOHIZx</name>
<description>IOHIZx</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IOHOLDx</name>
<description>IOHOLDx</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IOWAITx</name>
<description>IOWAITx</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IOSETx</name>
<description>IOSETx</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<dim>4</dim><dimIncrement>0x8</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>BWTR%s</name>
<displayName>BWTR1</displayName>
<description>SRAM/NOR-Flash write timing registers
1</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>ACCMOD</name>
<description>ACCMOD</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>ACCMOD</name><usage>read-write</usage><enumeratedValue><name>A</name><description>Access mode A</description><value>0</value></enumeratedValue><enumeratedValue><name>B</name><description>Access mode B</description><value>1</value></enumeratedValue><enumeratedValue><name>C</name><description>Access mode C</description><value>2</value></enumeratedValue><enumeratedValue><name>D</name><description>Access mode D</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DATLAT</name>
<description>DATLAT</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CLKDIV</name>
<description>CLKDIV</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DATAST</name>
<description>DATAST</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>ADDHLD</name>
<description>ADDHLD</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>ADDSET</name>
<description>ADDSET</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field><name>BUSTURN</name><description>Bus turnaround phase duration</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth><access>read-write</access><writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<dim>2</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2</dimIndex><name>SDCR%s</name>
<displayName>SDCR1</displayName>
<description>SDRAM Control Register 1</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000002D0</resetValue>
<fields>
<field>
<name>NC</name>
<description>Number of column address
bits</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>NC</name><usage>read-write</usage><enumeratedValue><name>Bits8</name><description>8 bits</description><value>0</value></enumeratedValue><enumeratedValue><name>Bits9</name><description>9 bits</description><value>1</value></enumeratedValue><enumeratedValue><name>Bits10</name><description>10 bits</description><value>2</value></enumeratedValue><enumeratedValue><name>Bits11</name><description>11 bits</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>NR</name>
<description>Number of row address bits</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>NR</name><usage>read-write</usage><enumeratedValue><name>Bits11</name><description>11 bits</description><value>0</value></enumeratedValue><enumeratedValue><name>Bits12</name><description>12 bits</description><value>1</value></enumeratedValue><enumeratedValue><name>Bits13</name><description>13 bits</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MWID</name>
<description>Memory data bus width</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>MWID</name><usage>read-write</usage><enumeratedValue><name>Bits8</name><description>Memory data bus width 8 bits</description><value>0</value></enumeratedValue><enumeratedValue><name>Bits16</name><description>Memory data bus width 16 bits</description><value>1</value></enumeratedValue><enumeratedValue><name>Bits32</name><description>Memory data bus width 32 bits</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>NB</name>
<description>Number of internal banks</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>NB</name><usage>read-write</usage><enumeratedValue><name>NB2</name><description>Two internal Banks</description><value>0</value></enumeratedValue><enumeratedValue><name>NB4</name><description>Four internal Banks</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CAS</name>
<description>CAS latency</description>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CAS</name><usage>read-write</usage><enumeratedValue><name>Clocks1</name><description>1 cycle</description><value>1</value></enumeratedValue><enumeratedValue><name>Clocks2</name><description>2 cycles</description><value>2</value></enumeratedValue><enumeratedValue><name>Clocks3</name><description>3 cycles</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WP</name>
<description>Write protection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WP</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Write accesses allowed</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Write accesses ignored</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SDCLK</name>
<description>SDRAM clock configuration</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>SDCLK</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>SDCLK clock disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>SDCLK period = 2 x HCLK period</description><value>2</value></enumeratedValue><enumeratedValue><name>Div3</name><description>SDCLK period = 3 x HCLK period</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RBURST</name>
<description>Burst read</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RBURST</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Single read requests are not managed as bursts</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Single read requests are always managed as bursts</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RPIPE</name>
<description>Read pipe</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>RPIPE</name><usage>read-write</usage><enumeratedValue><name>NoDelay</name><description>No clock cycle delay</description><value>0</value></enumeratedValue><enumeratedValue><name>Clocks1</name><description>One clock cycle delay</description><value>1</value></enumeratedValue><enumeratedValue><name>Clocks2</name><description>Two clock cycles delay</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>2</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2</dimIndex><name>SDTR%s</name>
<displayName>SDTR1</displayName>
<description>SDRAM Timing register 1</description>
<addressOffset>0x148</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFFFFF</resetValue>
<fields>
<field>
<name>TMRD</name>
<description>Load Mode Register to
Active</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>TXSR</name>
<description>Exit self-refresh delay</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>TRAS</name>
<description>Self refresh time</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>TRC</name>
<description>Row cycle delay</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>TWR</name>
<description>Recovery delay</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>TRP</name>
<description>Row precharge delay</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>TRCD</name>
<description>Row to column delay</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>SDCMR</name>
<displayName>SDCMR</displayName>
<description>SDRAM Command Mode register</description>
<addressOffset>0x150</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MODE</name>
<description>Command mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>write-only</access>
<enumeratedValues><name>MODE</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal Mode</description><value>0</value></enumeratedValue><enumeratedValue><name>ClockConfigurationEnable</name><description>Clock Configuration Enable</description><value>1</value></enumeratedValue><enumeratedValue><name>PALL</name><description>PALL (All Bank Precharge) command</description><value>2</value></enumeratedValue><enumeratedValue><name>AutoRefreshCommand</name><description>Auto-refresh command</description><value>3</value></enumeratedValue><enumeratedValue><name>LoadModeRegister</name><description>Load Mode Resgier</description><value>4</value></enumeratedValue><enumeratedValue><name>SelfRefreshCommand</name><description>Self-refresh command</description><value>5</value></enumeratedValue><enumeratedValue><name>PowerDownCommand</name><description>Power-down command</description><value>6</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CTB2</name>
<description>Command target bank 2</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues><name>CTB2</name><usage>read-write</usage><enumeratedValue><name>NotIssued</name><description>Command not issued to SDRAM Bank 1</description><value>0</value></enumeratedValue><enumeratedValue><name>Issued</name><description>Command issued to SDRAM Bank 1</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CTB1</name>
<description>Command target bank 1</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues derivedFrom="CTB2"/>
</field>
<field>
<name>NRFS</name>
<description>Number of Auto-refresh</description>
<bitOffset>5</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>MRD</name>
<description>Mode Register definition</description>
<bitOffset>9</bitOffset>
<bitWidth>13</bitWidth>
<access>read-write</access>
<writeConstraint><range><minimum>0</minimum><maximum>8191</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>SDRTR</name>
<displayName>SDRTR</displayName>
<description>SDRAM Refresh Timer register</description>
<addressOffset>0x154</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRE</name>
<description>Clear Refresh error flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues><name>CRE</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Refresh Error Flag is cleared</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>COUNT</name>
<description>Refresh Timer Count</description>
<bitOffset>1</bitOffset>
<bitWidth>13</bitWidth>
<access>read-write</access>
<writeConstraint><range><minimum>0</minimum><maximum>8191</maximum></range></writeConstraint>
</field>
<field>
<name>REIE</name>
<description>RES Interrupt Enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>REIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is generated if RE = 1</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SDSR</name>
<displayName>SDSR</displayName>
<description>SDRAM Status register</description>
<addressOffset>0x158</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RE</name>
<description>Refresh error flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RE</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No refresh error has been detected</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A refresh error has been detected</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MODES1</name>
<description>Status Mode for Bank 1</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>MODES1</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal Mode</description><value>0</value></enumeratedValue><enumeratedValue><name>SelfRefresh</name><description>Self-refresh mode</description><value>1</value></enumeratedValue><enumeratedValue><name>PowerDown</name><description>Power-down mode</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MODES2</name>
<description>Status Mode for Bank 2</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODES1"/>
</field>
<field>
<name>BUSY</name>
<description>Busy status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BUSY</name><usage>read-write</usage><enumeratedValue><name>NotBusy</name><description>SDRAM Controller is ready to accept a new request</description><value>0</value></enumeratedValue><enumeratedValue><name>Busy</name><description>SDRAM Controller is not ready to accept a new request</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DBGMCU</name>
<description>Debug support</description>
<groupName>DBG</groupName>
<baseAddress>0xE0042000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>IDCODE</name>
<displayName>IDCODE</displayName>
<description>IDCODE</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x10006411</resetValue>
<fields>
<field>
<name>DEV_ID</name>
<description>DEV_ID</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>REV_ID</name>
<description>REV_ID</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBG_SLEEP</name>
<description>DBG_SLEEP</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_STOP</name>
<description>DBG_STOP</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_STANDBY</name>
<description>DBG_STANDBY</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRACE_IOEN</name>
<description>TRACE_IOEN</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRACE_MODE</name>
<description>TRACE_MODE</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB1_FZ</name>
<displayName>APB1_FZ</displayName>
<description>Debug MCU APB1 Freeze registe</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBG_TIM2_STOP</name>
<description>DBG_TIM2_STOP</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM3_STOP</name>
<description>DBG_TIM3 _STOP</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM4_STOP</name>
<description>DBG_TIM4_STOP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM5_STOP</name>
<description>DBG_TIM5_STOP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM6_STOP</name>
<description>DBG_TIM6_STOP</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM7_STOP</name>
<description>DBG_TIM7_STOP</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM12_STOP</name>
<description>DBG_TIM12_STOP</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM13_STOP</name>
<description>DBG_TIM13_STOP</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM14_STOP</name>
<description>DBG_TIM14_STOP</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_WWDG_STOP</name>
<description>DBG_WWDG_STOP</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_IWDG_STOP</name>
<description>DBG_IWDEG_STOP</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_J2C1_SMBUS_TIMEOUT</name>
<description>DBG_J2C1_SMBUS_TIMEOUT</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_J2C2_SMBUS_TIMEOUT</name>
<description>DBG_J2C2_SMBUS_TIMEOUT</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_J2C3SMBUS_TIMEOUT</name>
<description>DBG_J2C3SMBUS_TIMEOUT</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_CAN1_STOP</name>
<description>DBG_CAN1_STOP</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_CAN2_STOP</name>
<description>DBG_CAN2_STOP</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB2_FZ</name>
<displayName>APB2_FZ</displayName>
<description>Debug MCU APB2 Freeze registe</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DBG_TIM1_STOP</name>
<description>TIM1 counter stopped when core is
halted</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM8_STOP</name>
<description>TIM8 counter stopped when core is
halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM9_STOP</name>
<description>TIM9 counter stopped when core is
halted</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM10_STOP</name>
<description>TIM10 counter stopped when core is
halted</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_TIM11_STOP</name>
<description>TIM11 counter stopped when core is
halted</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DMA2</name>
<description>DMA controller</description>
<groupName>DMA</groupName>
<baseAddress>0x40026400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA2_Stream0</name>
<description>DMA2 Stream0 global interrupt</description>
<value>56</value>
</interrupt>
<interrupt>
<name>DMA2_Stream0</name>
<description>DMA2 Stream0 global interrupt</description>
<value>56</value>
</interrupt>
<interrupt>
<name>DMA2_Stream1</name>
<description>DMA2 Stream1 global interrupt</description>
<value>57</value>
</interrupt>
<interrupt>
<name>DMA2_Stream1</name>
<description>DMA2 Stream1 global interrupt</description>
<value>57</value>
</interrupt>
<interrupt>
<name>DMA2_Stream2</name>
<description>DMA2 Stream2 global interrupt</description>
<value>58</value>
</interrupt>
<interrupt>
<name>DMA2_Stream2</name>
<description>DMA2 Stream2 global interrupt</description>
<value>58</value>
</interrupt>
<interrupt>
<name>DMA2_Stream3</name>
<description>DMA2 Stream3 global interrupt</description>
<value>59</value>
</interrupt>
<interrupt>
<name>DMA2_Stream3</name>
<description>DMA2 Stream3 global interrupt</description>
<value>59</value>
</interrupt>
<interrupt>
<name>DMA2_Stream4</name>
<description>DMA2 Stream4 global interrupt</description>
<value>60</value>
</interrupt>
<interrupt>
<name>DMA2_Stream4</name>
<description>DMA2 Stream4 global interrupt</description>
<value>60</value>
</interrupt>
<interrupt>
<name>DMA2_Stream5</name>
<description>DMA2 Stream5 global interrupt</description>
<value>68</value>
</interrupt>
<interrupt>
<name>DMA2_Stream5</name>
<description>DMA2 Stream5 global interrupt</description>
<value>68</value>
</interrupt>
<interrupt>
<name>DMA2_Stream6</name>
<description>DMA2 Stream6 global interrupt</description>
<value>69</value>
</interrupt>
<interrupt>
<name>DMA2_Stream6</name>
<description>DMA2 Stream6 global interrupt</description>
<value>69</value>
</interrupt>
<interrupt>
<name>DMA2_Stream7</name>
<description>DMA2 Stream7 global interrupt</description>
<value>70</value>
</interrupt>
<interrupt>
<name>DMA2_Stream7</name>
<description>DMA2 Stream7 global interrupt</description>
<value>70</value>
</interrupt>
<registers>
<cluster><dim>8</dim><dimIncrement>0x18</dimIncrement><dimIndex>0,1,2,3,4,5,6,7</dimIndex><name>ST%s</name><description>Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers</description><addressOffset>0x10</addressOffset><register>
<name>CR</name>
<displayName>S0CR</displayName>
<description>stream x configuration
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CHSEL</name>
<description>Channel selection</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint>
</field>
<field>
<name>MBURST</name>
<description>Memory burst transfer
configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PBURST"/>
</field>
<field>
<name>PBURST</name>
<description>Peripheral burst transfer
configuration</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PBURST</name><usage>read-write</usage><enumeratedValue><name>Single</name><description>Single transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>INCR4</name><description>Incremental burst of 4 beats</description><value>1</value></enumeratedValue><enumeratedValue><name>INCR8</name><description>Incremental burst of 8 beats</description><value>2</value></enumeratedValue><enumeratedValue><name>INCR16</name><description>Incremental burst of 16 beats</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CT</name>
<description>Current target (only in double buffer
mode)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CT</name><usage>read-write</usage><enumeratedValue><name>Memory0</name><description>The current target memory is Memory 0</description><value>0</value></enumeratedValue><enumeratedValue><name>Memory1</name><description>The current target memory is Memory 1</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DBM</name>
<description>Double buffer mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DBM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No buffer switching at the end of transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Memory target switched at the end of the DMA transfer</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PL</name>
<description>Priority level</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PL</name><usage>read-write</usage><enumeratedValue><name>Low</name><description>Low</description><value>0</value></enumeratedValue><enumeratedValue><name>Medium</name><description>Medium</description><value>1</value></enumeratedValue><enumeratedValue><name>High</name><description>High</description><value>2</value></enumeratedValue><enumeratedValue><name>VeryHigh</name><description>Very high</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PINCOS</name>
<description>Peripheral increment offset
size</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PINCOS</name><usage>read-write</usage><enumeratedValue><name>PSIZE</name><description>The offset size for the peripheral address calculation is linked to the PSIZE</description><value>0</value></enumeratedValue><enumeratedValue><name>Fixed4</name><description>The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MSIZE</name>
<description>Memory data size</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PSIZE"/>
</field>
<field>
<name>PSIZE</name>
<description>Peripheral data size</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PSIZE</name><usage>read-write</usage><enumeratedValue><name>Bits8</name><description>Byte (8-bit)</description><value>0</value></enumeratedValue><enumeratedValue><name>Bits16</name><description>Half-word (16-bit)</description><value>1</value></enumeratedValue><enumeratedValue><name>Bits32</name><description>Word (32-bit)</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MINC</name>
<description>Memory increment mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PINC"/>
</field>
<field>
<name>PINC</name>
<description>Peripheral increment mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PINC</name><usage>read-write</usage><enumeratedValue><name>Fixed</name><description>Address pointer is fixed</description><value>0</value></enumeratedValue><enumeratedValue><name>Incremented</name><description>Address pointer is incremented after each data transfer</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CIRC</name>
<description>Circular mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CIRC</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Circular mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Circular mode enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DIR</name>
<description>Data transfer direction</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>DIR</name><usage>read-write</usage><enumeratedValue><name>PeripheralToMemory</name><description>Peripheral-to-memory</description><value>0</value></enumeratedValue><enumeratedValue><name>MemoryToPeripheral</name><description>Memory-to-peripheral</description><value>1</value></enumeratedValue><enumeratedValue><name>MemoryToMemory</name><description>Memory-to-memory</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PFCTRL</name>
<description>Peripheral flow controller</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PFCTRL</name><usage>read-write</usage><enumeratedValue><name>DMA</name><description>The DMA is the flow controller</description><value>0</value></enumeratedValue><enumeratedValue><name>Peripheral</name><description>The peripheral is the flow controller</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TCIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TC interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TC interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HTIE</name>
<description>Half transfer interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>HTIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>HT interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>HT interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMEIE</name>
<description>Direct mode error interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DME interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DME interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EN</name>
<description>Stream enable / flag stream ready when
read low</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Stream disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Stream enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>NDTR</name>
<displayName>S0NDTR</displayName>
<description>stream x number of data
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NDT</name>
<description>Number of data items to
transfer</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PAR</name>
<displayName>S0PAR</displayName>
<description>stream x peripheral address
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PA</name>
<description>Peripheral address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M0AR</name>
<displayName>S0M0AR</displayName>
<description>stream x memory 0 address
register</description>
<addressOffset>0xc</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M0A</name>
<description>Memory 0 address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>M1AR</name>
<displayName>S0M1AR</displayName>
<description>stream x memory 1 address
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>M1A</name>
<description>Memory 1 address (used in case of Double
buffer mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FCR</name>
<displayName>S0FCR</displayName>
<description>stream x FIFO control register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<resetValue>0x00000021</resetValue>
<fields>
<field>
<name>FEIE</name>
<description>FIFO error interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>FEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>FE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>FE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FS</name>
<description>FIFO status</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues><name>FS</name><usage>read-write</usage><enumeratedValue><name>Quarter1</name><description>0 &lt; fifo_level &lt; 1/4</description><value>0</value></enumeratedValue><enumeratedValue><name>Quarter2</name><description>1/4 &lt;= fifo_level &lt; 1/2</description><value>1</value></enumeratedValue><enumeratedValue><name>Quarter3</name><description>1/2 &lt;= fifo_level &lt; 3/4</description><value>2</value></enumeratedValue><enumeratedValue><name>Quarter4</name><description>3/4 &lt;= fifo_level &lt; full</description><value>3</value></enumeratedValue><enumeratedValue><name>Empty</name><description>FIFO is empty</description><value>4</value></enumeratedValue><enumeratedValue><name>Full</name><description>FIFO is full</description><value>5</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMDIS</name>
<description>Direct mode disable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>DMDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Direct mode is enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Direct mode is disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues><name>FTH</name><usage>read-write</usage><enumeratedValue><name>Quarter</name><description>1/4 full FIFO</description><value>0</value></enumeratedValue><enumeratedValue><name>Half</name><description>1/2 full FIFO</description><value>1</value></enumeratedValue><enumeratedValue><name>ThreeQuarters</name><description>3/4 full FIFO</description><value>2</value></enumeratedValue><enumeratedValue><name>Full</name><description>Full FIFO</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</cluster><register>
<name>LISR</name>
<displayName>LISR</displayName>
<description>low interrupt status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TCIF3</name>
<description>Stream x transfer complete interrupt
flag (x = 3..0)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TCIF0"/>
</field>
<field>
<name>HTIF3</name>
<description>Stream x half transfer interrupt flag
(x=3..0)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="HTIF0"/>
</field>
<field>
<name>TEIF3</name>
<description>Stream x transfer error interrupt flag
(x=3..0)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TEIF0"/>
</field>
<field>
<name>DMEIF3</name>
<description>Stream x direct mode error interrupt
flag (x=3..0)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DMEIF0"/>
</field>
<field>
<name>FEIF3</name>
<description>Stream x FIFO error interrupt flag
(x=3..0)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="FEIF0"/>
</field>
<field>
<name>TCIF2</name>
<description>Stream x transfer complete interrupt
flag (x = 3..0)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TCIF0"/>
</field>
<field>
<name>HTIF2</name>
<description>Stream x half transfer interrupt flag
(x=3..0)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="HTIF0"/>
</field>
<field>
<name>TEIF2</name>
<description>Stream x transfer error interrupt flag
(x=3..0)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TEIF0"/>
</field>
<field>
<name>DMEIF2</name>
<description>Stream x direct mode error interrupt
flag (x=3..0)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DMEIF0"/>
</field>
<field>
<name>FEIF2</name>
<description>Stream x FIFO error interrupt flag
(x=3..0)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="FEIF0"/>
</field>
<field>
<name>TCIF1</name>
<description>Stream x transfer complete interrupt
flag (x = 3..0)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TCIF0"/>
</field>
<field>
<name>HTIF1</name>
<description>Stream x half transfer interrupt flag
(x=3..0)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="HTIF0"/>
</field>
<field>
<name>TEIF1</name>
<description>Stream x transfer error interrupt flag
(x=3..0)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TEIF0"/>
</field>
<field>
<name>DMEIF1</name>
<description>Stream x direct mode error interrupt
flag (x=3..0)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DMEIF0"/>
</field>
<field>
<name>FEIF1</name>
<description>Stream x FIFO error interrupt flag
(x=3..0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="FEIF0"/>
</field>
<field>
<name>TCIF0</name>
<description>Stream x transfer complete interrupt
flag (x = 3..0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TCIF0</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>No transfer complete event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>A transfer complete event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HTIF0</name>
<description>Stream x half transfer interrupt flag
(x=3..0)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>HTIF0</name><usage>read-write</usage><enumeratedValue><name>NotHalf</name><description>No half transfer event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Half</name><description>A half transfer event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TEIF0</name>
<description>Stream x transfer error interrupt flag
(x=3..0)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TEIF0</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No transfer error on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A transfer error occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMEIF0</name>
<description>Stream x direct mode error interrupt
flag (x=3..0)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMEIF0</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No Direct Mode error on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A Direct Mode error occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FEIF0</name>
<description>Stream x FIFO error interrupt flag
(x=3..0)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FEIF0</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No FIFO error event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A FIFO error event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>HISR</name>
<displayName>HISR</displayName>
<description>high interrupt status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TCIF7</name>
<description>Stream x transfer complete interrupt
flag (x=7..4)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TCIF4"/>
</field>
<field>
<name>HTIF7</name>
<description>Stream x half transfer interrupt flag
(x=7..4)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="HTIF4"/>
</field>
<field>
<name>TEIF7</name>
<description>Stream x transfer error interrupt flag
(x=7..4)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TEIF4"/>
</field>
<field>
<name>DMEIF7</name>
<description>Stream x direct mode error interrupt
flag (x=7..4)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DMEIF4"/>
</field>
<field>
<name>FEIF7</name>
<description>Stream x FIFO error interrupt flag
(x=7..4)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="FEIF4"/>
</field>
<field>
<name>TCIF6</name>
<description>Stream x transfer complete interrupt
flag (x=7..4)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TCIF4"/>
</field>
<field>
<name>HTIF6</name>
<description>Stream x half transfer interrupt flag
(x=7..4)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="HTIF4"/>
</field>
<field>
<name>TEIF6</name>
<description>Stream x transfer error interrupt flag
(x=7..4)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TEIF4"/>
</field>
<field>
<name>DMEIF6</name>
<description>Stream x direct mode error interrupt
flag (x=7..4)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DMEIF4"/>
</field>
<field>
<name>FEIF6</name>
<description>Stream x FIFO error interrupt flag
(x=7..4)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="FEIF4"/>
</field>
<field>
<name>TCIF5</name>
<description>Stream x transfer complete interrupt
flag (x=7..4)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TCIF4"/>
</field>
<field>
<name>HTIF5</name>
<description>Stream x half transfer interrupt flag
(x=7..4)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="HTIF4"/>
</field>
<field>
<name>TEIF5</name>
<description>Stream x transfer error interrupt flag
(x=7..4)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TEIF4"/>
</field>
<field>
<name>DMEIF5</name>
<description>Stream x direct mode error interrupt
flag (x=7..4)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DMEIF4"/>
</field>
<field>
<name>FEIF5</name>
<description>Stream x FIFO error interrupt flag
(x=7..4)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="FEIF4"/>
</field>
<field>
<name>TCIF4</name>
<description>Stream x transfer complete interrupt
flag (x=7..4)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TCIF4</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>No transfer complete event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>A transfer complete event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HTIF4</name>
<description>Stream x half transfer interrupt flag
(x=7..4)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>HTIF4</name><usage>read-write</usage><enumeratedValue><name>NotHalf</name><description>No half transfer event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Half</name><description>A half transfer event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TEIF4</name>
<description>Stream x transfer error interrupt flag
(x=7..4)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TEIF4</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No transfer error on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A transfer error occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMEIF4</name>
<description>Stream x direct mode error interrupt
flag (x=7..4)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMEIF4</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No Direct Mode error on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A Direct Mode error occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FEIF4</name>
<description>Stream x FIFO error interrupt flag
(x=7..4)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FEIF4</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No FIFO error event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A FIFO error event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LIFCR</name>
<displayName>LIFCR</displayName>
<description>low interrupt flag clear
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTCIF3</name>
<description>Stream x clear transfer complete
interrupt flag (x = 3..0)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTCIF0"/>
</field>
<field>
<name>CHTIF3</name>
<description>Stream x clear half transfer interrupt
flag (x = 3..0)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CHTIF0"/>
</field>
<field>
<name>CTEIF3</name>
<description>Stream x clear transfer error interrupt
flag (x = 3..0)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTEIF0"/>
</field>
<field>
<name>CDMEIF3</name>
<description>Stream x clear direct mode error
interrupt flag (x = 3..0)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CDMEIF0"/>
</field>
<field>
<name>CFEIF3</name>
<description>Stream x clear FIFO error interrupt flag
(x = 3..0)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CFEIF0"/>
</field>
<field>
<name>CTCIF2</name>
<description>Stream x clear transfer complete
interrupt flag (x = 3..0)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTCIF0"/>
</field>
<field>
<name>CHTIF2</name>
<description>Stream x clear half transfer interrupt
flag (x = 3..0)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CHTIF0"/>
</field>
<field>
<name>CTEIF2</name>
<description>Stream x clear transfer error interrupt
flag (x = 3..0)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTEIF0"/>
</field>
<field>
<name>CDMEIF2</name>
<description>Stream x clear direct mode error
interrupt flag (x = 3..0)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CDMEIF0"/>
</field>
<field>
<name>CFEIF2</name>
<description>Stream x clear FIFO error interrupt flag
(x = 3..0)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CFEIF0"/>
</field>
<field>
<name>CTCIF1</name>
<description>Stream x clear transfer complete
interrupt flag (x = 3..0)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTCIF0"/>
</field>
<field>
<name>CHTIF1</name>
<description>Stream x clear half transfer interrupt
flag (x = 3..0)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CHTIF0"/>
</field>
<field>
<name>CTEIF1</name>
<description>Stream x clear transfer error interrupt
flag (x = 3..0)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTEIF0"/>
</field>
<field>
<name>CDMEIF1</name>
<description>Stream x clear direct mode error
interrupt flag (x = 3..0)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CDMEIF0"/>
</field>
<field>
<name>CFEIF1</name>
<description>Stream x clear FIFO error interrupt flag
(x = 3..0)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CFEIF0"/>
</field>
<field>
<name>CTCIF0</name>
<description>Stream x clear transfer complete
interrupt flag (x = 3..0)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CTCIF0</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding TCIFx flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CHTIF0</name>
<description>Stream x clear half transfer interrupt
flag (x = 3..0)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CHTIF0</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding HTIFx flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CTEIF0</name>
<description>Stream x clear transfer error interrupt
flag (x = 3..0)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CTEIF0</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding TEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CDMEIF0</name>
<description>Stream x clear direct mode error
interrupt flag (x = 3..0)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CDMEIF0</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding DMEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CFEIF0</name>
<description>Stream x clear FIFO error interrupt flag
(x = 3..0)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CFEIF0</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding CFEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>HIFCR</name>
<displayName>HIFCR</displayName>
<description>high interrupt flag clear
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CTCIF7</name>
<description>Stream x clear transfer complete
interrupt flag (x = 7..4)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTCIF4"/>
</field>
<field>
<name>CHTIF7</name>
<description>Stream x clear half transfer interrupt
flag (x = 7..4)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CHTIF4"/>
</field>
<field>
<name>CTEIF7</name>
<description>Stream x clear transfer error interrupt
flag (x = 7..4)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTEIF4"/>
</field>
<field>
<name>CDMEIF7</name>
<description>Stream x clear direct mode error
interrupt flag (x = 7..4)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CDMEIF4"/>
</field>
<field>
<name>CFEIF7</name>
<description>Stream x clear FIFO error interrupt flag
(x = 7..4)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CFEIF4"/>
</field>
<field>
<name>CTCIF6</name>
<description>Stream x clear transfer complete
interrupt flag (x = 7..4)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTCIF4"/>
</field>
<field>
<name>CHTIF6</name>
<description>Stream x clear half transfer interrupt
flag (x = 7..4)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CHTIF4"/>
</field>
<field>
<name>CTEIF6</name>
<description>Stream x clear transfer error interrupt
flag (x = 7..4)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTEIF4"/>
</field>
<field>
<name>CDMEIF6</name>
<description>Stream x clear direct mode error
interrupt flag (x = 7..4)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CDMEIF4"/>
</field>
<field>
<name>CFEIF6</name>
<description>Stream x clear FIFO error interrupt flag
(x = 7..4)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CFEIF4"/>
</field>
<field>
<name>CTCIF5</name>
<description>Stream x clear transfer complete
interrupt flag (x = 7..4)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTCIF4"/>
</field>
<field>
<name>CHTIF5</name>
<description>Stream x clear half transfer interrupt
flag (x = 7..4)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CHTIF4"/>
</field>
<field>
<name>CTEIF5</name>
<description>Stream x clear transfer error interrupt
flag (x = 7..4)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CTEIF4"/>
</field>
<field>
<name>CDMEIF5</name>
<description>Stream x clear direct mode error
interrupt flag (x = 7..4)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CDMEIF4"/>
</field>
<field>
<name>CFEIF5</name>
<description>Stream x clear FIFO error interrupt flag
(x = 7..4)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CFEIF4"/>
</field>
<field>
<name>CTCIF4</name>
<description>Stream x clear transfer complete
interrupt flag (x = 7..4)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CTCIF4</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding TCIFx flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CHTIF4</name>
<description>Stream x clear half transfer interrupt
flag (x = 7..4)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CHTIF4</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding HTIFx flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CTEIF4</name>
<description>Stream x clear transfer error interrupt
flag (x = 7..4)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CTEIF4</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding TEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CDMEIF4</name>
<description>Stream x clear direct mode error
interrupt flag (x = 7..4)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CDMEIF4</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding DMEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CFEIF4</name>
<description>Stream x clear FIFO error interrupt flag
(x = 7..4)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CFEIF4</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding CFEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="DMA2">
<name>DMA1</name>
<baseAddress>0x40026000</baseAddress>
<interrupt>
<name>DMA1_Stream0</name>
<description>DMA1 Stream0 global interrupt</description>
<value>11</value>
</interrupt>
<interrupt>
<name>DMA1_Stream0</name>
<description>DMA1 Stream0 global interrupt</description>
<value>11</value>
</interrupt>
<interrupt>
<name>DMA1_Stream1</name>
<description>DMA1 Stream1 global interrupt</description>
<value>12</value>
</interrupt>
<interrupt>
<name>DMA1_Stream1</name>
<description>DMA1 Stream1 global interrupt</description>
<value>12</value>
</interrupt>
<interrupt>
<name>DMA1_Stream2</name>
<description>DMA1 Stream2 global interrupt</description>
<value>13</value>
</interrupt>
<interrupt>
<name>DMA1_Stream2</name>
<description>DMA1 Stream2 global interrupt</description>
<value>13</value>
</interrupt>
<interrupt>
<name>DMA1_Stream3</name>
<description>DMA1 Stream3 global interrupt</description>
<value>14</value>
</interrupt>
<interrupt>
<name>DMA1_Stream3</name>
<description>DMA1 Stream3 global interrupt</description>
<value>14</value>
</interrupt>
<interrupt>
<name>DMA1_Stream4</name>
<description>DMA1 Stream4 global interrupt</description>
<value>15</value>
</interrupt>
<interrupt>
<name>DMA1_Stream4</name>
<description>DMA1 Stream4 global interrupt</description>
<value>15</value>
</interrupt>
<interrupt>
<name>DMA1_Stream5</name>
<description>DMA1 Stream5 global interrupt</description>
<value>16</value>
</interrupt>
<interrupt>
<name>DMA1_Stream5</name>
<description>DMA1 Stream5 global interrupt</description>
<value>16</value>
</interrupt>
<interrupt>
<name>DMA1_Stream6</name>
<description>DMA1 Stream6 global interrupt</description>
<value>17</value>
</interrupt>
<interrupt>
<name>DMA1_Stream6</name>
<description>DMA1 Stream6 global interrupt</description>
<value>17</value>
</interrupt>
<interrupt>
<name>DMA1_Stream7</name>
<description>DMA1 Stream7 global interrupt</description>
<value>47</value>
</interrupt>
<interrupt>
<name>DMA1_Stream7</name>
<description>DMA1 Stream7 global interrupt</description>
<value>47</value>
</interrupt>
</peripheral>
<peripheral>
<name>RCC</name>
<description>Reset and clock control</description>
<groupName>RCC</groupName>
<baseAddress>0x40023800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RCC</name>
<description>RCC global interrupt</description>
<value>5</value>
</interrupt>
<interrupt>
<name>RCC</name>
<description>RCC global interrupt</description>
<value>5</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>clock control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000083</resetValue>
<fields>
<field>
<name>PLLI2SRDY</name>
<description>PLLI2S clock ready flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues derivedFrom="HSIRDYR"/>
</field>
<field>
<name>PLLI2SON</name>
<description>PLLI2S enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="HSION"/>
</field>
<field>
<name>PLLRDY</name>
<description>Main PLL (PLL) clock ready
flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues derivedFrom="HSIRDYR"/>
</field>
<field>
<name>PLLON</name>
<description>Main PLL (PLL) enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="HSION"/>
</field>
<field>
<name>CSSON</name>
<description>Clock security system
enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>CSSON</name><usage>read-write</usage><enumeratedValue><name>Off</name><description>Clock security system disabled (clock detector OFF)</description><value>0</value></enumeratedValue><enumeratedValue><name>On</name><description>Clock security system enable (clock detector ON if the HSE is ready, OFF if not)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HSEBYP</name>
<description>HSE clock bypass</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>HSEBYP</name><usage>read-write</usage><enumeratedValue><name>NotBypassed</name><description>HSE crystal oscillator not bypassed</description><value>0</value></enumeratedValue><enumeratedValue><name>Bypassed</name><description>HSE crystal oscillator bypassed with external clock</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HSERDY</name>
<description>HSE clock ready flag</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues derivedFrom="HSIRDYR"/>
</field>
<field>
<name>HSEON</name>
<description>HSE clock enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="HSION"/>
</field>
<field>
<name>HSICAL</name>
<description>Internal high-speed clock
calibration</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>HSITRIM</name>
<description>Internal high-speed clock
trimming</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
<field>
<name>HSIRDY</name>
<description>Internal high-speed clock ready
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>HSIRDYR</name><usage>read</usage><enumeratedValue><name>NotReady</name><description>Clock not ready</description><value>0</value></enumeratedValue><enumeratedValue><name>Ready</name><description>Clock ready</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HSION</name>
<description>Internal high-speed clock
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>HSION</name><usage>read-write</usage><enumeratedValue><name>Off</name><description>Clock Off</description><value>0</value></enumeratedValue><enumeratedValue><name>On</name><description>Clock On</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field><name>PLLSAIRDY</name><description>PLLSAI clock ready flag</description><bitOffset>29</bitOffset><bitWidth>1</bitWidth><access>read-only</access><enumeratedValues derivedFrom="HSIRDYR"/>
</field>
<field><name>PLLSAION</name><description>PLLSAI enable</description><bitOffset>28</bitOffset><bitWidth>1</bitWidth><access>read-write</access><enumeratedValues derivedFrom="HSION"/>
</field>
</fields>
</register>
<register>
<name>PLLCFGR</name>
<displayName>PLLCFGR</displayName>
<description>PLL configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x24003010</resetValue>
<fields>
<field>
<name>PLLSRC</name>
<description>Main PLL(PLL) and audio PLL (PLLI2S)
entry clock source</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PLLSRC</name><usage>read-write</usage><enumeratedValue><name>HSI</name><description>HSI clock selected as PLL and PLLI2S clock entry</description><value>0</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE oscillator clock selected as PLL and PLLI2S clock entry</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field><name>PLLM</name><description>Division factor for the main PLL (PLL)
and audio PLL (PLLI2S) input clock</description><bitOffset>0</bitOffset><bitWidth>6</bitWidth><writeConstraint><range><minimum>2</minimum><maximum>63</maximum></range></writeConstraint>
</field><field><name>PLLN</name><description>Main PLL (PLL) multiplication factor for
VCO</description><bitOffset>6</bitOffset><bitWidth>9</bitWidth><writeConstraint><range><minimum>50</minimum><maximum>432</maximum></range></writeConstraint>
</field><field><name>PLLP</name><description>Main PLL (PLL) division factor for main
system clock</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth><enumeratedValues><name>PLLP</name><usage>read-write</usage><enumeratedValue><name>Div2</name><description>PLLP=2</description><value>0</value></enumeratedValue><enumeratedValue><name>Div4</name><description>PLLP=4</description><value>1</value></enumeratedValue><enumeratedValue><name>Div6</name><description>PLLP=6</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>PLLP=8</description><value>3</value></enumeratedValue></enumeratedValues>
</field><field><name>PLLQ</name><description>Main PLL (PLL) division factor for USB
OTG FS, SDIO and random number generator
clocks</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth><writeConstraint><range><minimum>2</minimum><maximum>15</maximum></range></writeConstraint>
</field></fields>
</register>
<register>
<name>CFGR</name>
<displayName>CFGR</displayName>
<description>clock configuration register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCO2</name>
<description>Microcontroller clock output
2</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues><name>MCO2</name><usage>read-write</usage><enumeratedValue><name>SYSCLK</name><description>System clock (SYSCLK) selected</description><value>0</value></enumeratedValue><enumeratedValue><name>PLLI2S</name><description>PLLI2S clock selected</description><value>1</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE oscillator clock selected</description><value>2</value></enumeratedValue><enumeratedValue><name>PLL</name><description>PLL clock selected</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MCO2PRE</name>
<description>MCO2 prescaler</description>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="MCO1PRE"/>
</field>
<field>
<name>MCO1PRE</name>
<description>MCO1 prescaler</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues><name>MCO1PRE</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>No division</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>Division by 2</description><value>4</value></enumeratedValue><enumeratedValue><name>Div3</name><description>Division by 3</description><value>5</value></enumeratedValue><enumeratedValue><name>Div4</name><description>Division by 4</description><value>6</value></enumeratedValue><enumeratedValue><name>Div5</name><description>Division by 5</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>I2SSRC</name>
<description>I2S clock selection</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>I2SSRC</name><usage>read-write</usage><enumeratedValue><name>PLLI2S</name><description>PLLI2S clock used as I2S clock source</description><value>0</value></enumeratedValue><enumeratedValue><name>CKIN</name><description>External clock mapped on the I2S_CKIN pin used as I2S clock source</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MCO1</name>
<description>Microcontroller clock output
1</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
<enumeratedValues><name>MCO1</name><usage>read-write</usage><enumeratedValue><name>HSI</name><description>HSI clock selected</description><value>0</value></enumeratedValue><enumeratedValue><name>LSE</name><description>LSE oscillator selected</description><value>1</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE oscillator clock selected</description><value>2</value></enumeratedValue><enumeratedValue><name>PLL</name><description>PLL clock selected</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RTCPRE</name>
<description>HSE division factor for RTC
clock</description>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
<field>
<name>PPRE2</name>
<description>APB high-speed prescaler
(APB2)</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="PPRE1"/>
</field>
<field>
<name>PPRE1</name>
<description>APB Low speed prescaler
(APB1)</description>
<bitOffset>10</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues><name>PPRE1</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>HCLK not divided</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>HCLK divided by 2</description><value>4</value></enumeratedValue><enumeratedValue><name>Div4</name><description>HCLK divided by 4</description><value>5</value></enumeratedValue><enumeratedValue><name>Div8</name><description>HCLK divided by 8</description><value>6</value></enumeratedValue><enumeratedValue><name>Div16</name><description>HCLK divided by 16</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HPRE</name>
<description>AHB prescaler</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues><name>HPRE</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>SYSCLK not divided</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>SYSCLK divided by 2</description><value>8</value></enumeratedValue><enumeratedValue><name>Div4</name><description>SYSCLK divided by 4</description><value>9</value></enumeratedValue><enumeratedValue><name>Div8</name><description>SYSCLK divided by 8</description><value>10</value></enumeratedValue><enumeratedValue><name>Div16</name><description>SYSCLK divided by 16</description><value>11</value></enumeratedValue><enumeratedValue><name>Div64</name><description>SYSCLK divided by 64</description><value>12</value></enumeratedValue><enumeratedValue><name>Div128</name><description>SYSCLK divided by 128</description><value>13</value></enumeratedValue><enumeratedValue><name>Div256</name><description>SYSCLK divided by 256</description><value>14</value></enumeratedValue><enumeratedValue><name>Div512</name><description>SYSCLK divided by 512</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
<field><name>SW</name><description>System clock switch</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth><enumeratedValues><name>SW</name><usage>read-write</usage><enumeratedValue><name>HSI</name><description>HSI selected as system clock</description><value>0</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE selected as system clock</description><value>1</value></enumeratedValue><enumeratedValue><name>PLL</name><description>PLL selected as system clock</description><value>2</value></enumeratedValue></enumeratedValues>
</field><field><name>SWS</name><description>System clock switch status</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth><enumeratedValues><name>SWSR</name><usage>read</usage><enumeratedValue><name>HSI</name><description>HSI oscillator used as system clock</description><value>0</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE oscillator used as system clock</description><value>1</value></enumeratedValue><enumeratedValue><name>PLL</name><description>PLL used as system clock</description><value>2</value></enumeratedValue></enumeratedValues>
</field></fields>
</register>
<register>
<name>CIR</name>
<displayName>CIR</displayName>
<description>clock interrupt register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CSSC</name>
<description>Clock security system interrupt
clear</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues><name>CSSCW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear CSSF flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PLLI2SRDYC</name>
<description>PLLI2S ready interrupt
clear</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues derivedFrom="LSIRDYCW"/>
</field>
<field>
<name>PLLRDYC</name>
<description>Main PLL(PLL) ready interrupt
clear</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues derivedFrom="LSIRDYCW"/>
</field>
<field>
<name>HSERDYC</name>
<description>HSE ready interrupt clear</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues derivedFrom="LSIRDYCW"/>
</field>
<field>
<name>HSIRDYC</name>
<description>HSI ready interrupt clear</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues derivedFrom="LSIRDYCW"/>
</field>
<field>
<name>LSERDYC</name>
<description>LSE ready interrupt clear</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues derivedFrom="LSIRDYCW"/>
</field>
<field>
<name>LSIRDYC</name>
<description>LSI ready interrupt clear</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues><name>LSIRDYCW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear interrupt flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PLLI2SRDYIE</name>
<description>PLLI2S ready interrupt
enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="LSIRDYIE"/>
</field>
<field>
<name>PLLRDYIE</name>
<description>Main PLL (PLL) ready interrupt
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="LSIRDYIE"/>
</field>
<field>
<name>HSERDYIE</name>
<description>HSE ready interrupt enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="LSIRDYIE"/>
</field>
<field>
<name>HSIRDYIE</name>
<description>HSI ready interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="LSIRDYIE"/>
</field>
<field>
<name>LSERDYIE</name>
<description>LSE ready interrupt enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="LSIRDYIE"/>
</field>
<field>
<name>LSIRDYIE</name>
<description>LSI ready interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>LSIRDYIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CSSF</name>
<description>Clock security system interrupt
flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>CSSFR</name><usage>read</usage><enumeratedValue><name>NotInterrupted</name><description>No clock security interrupt caused by HSE clock failure</description><value>0</value></enumeratedValue><enumeratedValue><name>Interrupted</name><description>Clock security interrupt caused by HSE clock failure</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PLLI2SRDYF</name>
<description>PLLI2S ready interrupt
flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues derivedFrom="LSIRDYFR"/>
</field>
<field>
<name>PLLRDYF</name>
<description>Main PLL (PLL) ready interrupt
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues derivedFrom="LSIRDYFR"/>
</field>
<field>
<name>HSERDYF</name>
<description>HSE ready interrupt flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues derivedFrom="LSIRDYFR"/>
</field>
<field>
<name>HSIRDYF</name>
<description>HSI ready interrupt flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues derivedFrom="LSIRDYFR"/>
</field>
<field>
<name>LSERDYF</name>
<description>LSE ready interrupt flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues derivedFrom="LSIRDYFR"/>
</field>
<field>
<name>LSIRDYF</name>
<description>LSI ready interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>LSIRDYFR</name><usage>read</usage><enumeratedValue><name>NotInterrupted</name><description>No clock ready interrupt</description><value>0</value></enumeratedValue><enumeratedValue><name>Interrupted</name><description>Clock ready interrupt</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AHB1RSTR</name>
<displayName>AHB1RSTR</displayName>
<description>AHB1 peripheral reset register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OTGHSRST</name>
<description>USB OTG HS module reset</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>ETHMACRST</name>
<description>Ethernet MAC reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>DMA2RST</name>
<description>DMA2 reset</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>DMA1RST</name>
<description>DMA2 reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>CRCRST</name>
<description>CRC reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>GPIOIRST</name>
<description>IO port I reset</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>GPIOHRST</name>
<description>IO port H reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>GPIOGRST</name>
<description>IO port G reset</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>GPIOFRST</name>
<description>IO port F reset</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>GPIOERST</name>
<description>IO port E reset</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>GPIODRST</name>
<description>IO port D reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>GPIOCRST</name>
<description>IO port C reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>GPIOBRST</name>
<description>IO port B reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field>
<name>GPIOARST</name>
<description>IO port A reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>GPIOARST</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset the selected module</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field><name>DMA2DRST</name><description>DMA2D reset</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field><name>GPIOJRST</name><description>IO port J reset</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="GPIOARST"/>
</field>
<field><name>GPIOKRST</name><description>IO port K reset</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="GPIOARST"/>
</field>
</fields>
</register>
<register>
<name>AHB2RSTR</name>
<displayName>AHB2RSTR</displayName>
<description>AHB2 peripheral reset register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OTGFSRST</name>
<description>USB OTG FS module reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMIRST"/>
</field>
<field>
<name>RNGRST</name>
<description>Random number generator module
reset</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMIRST"/>
</field>
<field>
<name>HSAHRST</name>
<description>Hash module reset</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMIRST"/>
</field>
<field>
<name>CRYPRST</name>
<description>Cryptographic module reset</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMIRST"/>
</field>
<field>
<name>DCMIRST</name>
<description>Camera interface reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DCMIRST</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset the selected module</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AHB3RSTR</name>
<displayName>AHB3RSTR</displayName>
<description>AHB3 peripheral reset register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FMCRST</name>
<description>Flexible memory controller module
reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FMCRST</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset the selected module</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>APB1RSTR</name>
<displayName>APB1RSTR</displayName>
<description>APB1 peripheral reset register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIM2RST</name>
<description>TIM2 reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIM2RST</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset the selected module</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIM3RST</name>
<description>TIM3 reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>TIM4RST</name>
<description>TIM4 reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>TIM5RST</name>
<description>TIM5 reset</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>TIM6RST</name>
<description>TIM6 reset</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>TIM7RST</name>
<description>TIM7 reset</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>TIM12RST</name>
<description>TIM12 reset</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>TIM13RST</name>
<description>TIM13 reset</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>TIM14RST</name>
<description>TIM14 reset</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>WWDGRST</name>
<description>Window watchdog reset</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>SPI2RST</name>
<description>SPI 2 reset</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>SPI3RST</name>
<description>SPI 3 reset</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>USART2RST</name>
<description>USART 2 reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>USART3RST</name>
<description>USART 3 reset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>UART4RST</name>
<description>USART 4 reset</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>UART5RST</name>
<description>USART 5 reset</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>I2C1RST</name>
<description>I2C 1 reset</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>I2C2RST</name>
<description>I2C 2 reset</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>I2C3RST</name>
<description>I2C3 reset</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>CAN1RST</name>
<description>CAN1 reset</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>CAN2RST</name>
<description>CAN2 reset</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>PWRRST</name>
<description>Power interface reset</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field>
<name>DACRST</name>
<description>DAC reset</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field><name>UART7RST</name><description>UART7 reset</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM2RST"/>
</field>
<field><name>UART8RST</name><description>UART8 reset</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM2RST"/>
</field>
</fields>
</register>
<register>
<name>APB2RSTR</name>
<displayName>APB2RSTR</displayName>
<description>APB2 peripheral reset register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIM1RST</name>
<description>TIM1 reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIM1RST</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset the selected module</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIM8RST</name>
<description>TIM8 reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field>
<name>USART1RST</name>
<description>USART1 reset</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field>
<name>USART6RST</name>
<description>USART6 reset</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field>
<name>ADCRST</name>
<description>ADC interface reset (common to all
ADCs)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field>
<name>SDIORST</name>
<description>SDIO reset</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field>
<name>SPI1RST</name>
<description>SPI 1 reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field>
<name>SYSCFGRST</name>
<description>System configuration controller
reset</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field>
<name>TIM9RST</name>
<description>TIM9 reset</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field>
<name>TIM10RST</name>
<description>TIM10 reset</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field>
<name>TIM11RST</name>
<description>TIM11 reset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field><name>SPI6RST</name><description>SPI6 reset</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field><name>SAI1RST</name><description>SAI1 reset</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field><name>LTDCRST</name><description>LTDC reset</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field><name>SPI4RST</name><description>SPI4 reset</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1RST"/>
</field>
<field><name>SPI5RST</name><description>SPI5 reset</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1RST"/>
</field>
</fields>
</register>
<register>
<name>AHB1ENR</name>
<displayName>AHB1ENR</displayName>
<description>AHB1 peripheral clock register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00100000</resetValue>
<fields>
<field>
<name>OTGHSULPIEN</name>
<description>USB OTG HSULPI clock
enable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>OTGHSEN</name>
<description>USB OTG HS clock enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>ETHMACPTPEN</name>
<description>Ethernet PTP clock enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>ETHMACRXEN</name>
<description>Ethernet Reception clock
enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>ETHMACTXEN</name>
<description>Ethernet Transmission clock
enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>ETHMACEN</name>
<description>Ethernet MAC clock enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>DMA2EN</name>
<description>DMA2 clock enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>DMA1EN</name>
<description>DMA1 clock enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>CCMDATARAMEN</name>
<description>CCM data RAM clock enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>BKPSRAMEN</name>
<description>Backup SRAM interface clock
enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>CRCEN</name>
<description>CRC clock enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>GPIOIEN</name>
<description>IO port I clock enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>GPIOHEN</name>
<description>IO port H clock enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>GPIOGEN</name>
<description>IO port G clock enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>GPIOFEN</name>
<description>IO port F clock enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>GPIOEEN</name>
<description>IO port E clock enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>GPIODEN</name>
<description>IO port D clock enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>GPIOCEN</name>
<description>IO port C clock enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>GPIOBEN</name>
<description>IO port B clock enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field>
<name>GPIOAEN</name>
<description>IO port A clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>GPIOAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>The selected clock is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>The selected clock is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field><name>DMA2DEN</name><description>DMA2D clock enable</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field><name>GPIOJEN</name><description>IO port J clock enable</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="GPIOAEN"/>
</field>
<field><name>GPIOKEN</name><description>IO port K clock enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="GPIOAEN"/>
</field>
</fields>
</register>
<register>
<name>AHB2ENR</name>
<displayName>AHB2ENR</displayName>
<description>AHB2 peripheral clock enable
register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OTGFSEN</name>
<description>USB OTG FS clock enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMIEN"/>
</field>
<field>
<name>RNGEN</name>
<description>Random number generator clock
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMIEN"/>
</field>
<field>
<name>HASHEN</name>
<description>Hash modules clock enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMIEN"/>
</field>
<field>
<name>CRYPEN</name>
<description>Cryptographic modules clock
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMIEN"/>
</field>
<field>
<name>DCMIEN</name>
<description>Camera interface enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DCMIEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>The selected clock is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>The selected clock is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AHB3ENR</name>
<displayName>AHB3ENR</displayName>
<description>AHB3 peripheral clock enable
register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FMCEN</name>
<description>Flexible memory controller module clock
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FMCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>The selected clock is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>The selected clock is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>APB1ENR</name>
<displayName>APB1ENR</displayName>
<description>APB1 peripheral clock enable
register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIM2EN</name>
<description>TIM2 clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIM2EN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>The selected clock is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>The selected clock is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIM3EN</name>
<description>TIM3 clock enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>TIM4EN</name>
<description>TIM4 clock enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>TIM5EN</name>
<description>TIM5 clock enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>TIM6EN</name>
<description>TIM6 clock enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>TIM7EN</name>
<description>TIM7 clock enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>TIM12EN</name>
<description>TIM12 clock enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>TIM13EN</name>
<description>TIM13 clock enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>TIM14EN</name>
<description>TIM14 clock enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>WWDGEN</name>
<description>Window watchdog clock
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>SPI2EN</name>
<description>SPI2 clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>SPI3EN</name>
<description>SPI3 clock enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>USART2EN</name>
<description>USART 2 clock enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>USART3EN</name>
<description>USART3 clock enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>UART4EN</name>
<description>UART4 clock enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>UART5EN</name>
<description>UART5 clock enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>I2C1EN</name>
<description>I2C1 clock enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>I2C2EN</name>
<description>I2C2 clock enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>I2C3EN</name>
<description>I2C3 clock enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>CAN1EN</name>
<description>CAN 1 clock enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>CAN2EN</name>
<description>CAN 2 clock enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>PWREN</name>
<description>Power interface clock
enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field>
<name>DACEN</name>
<description>DAC interface clock enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field><name>UART7EN</name><description>UART7 clock enable</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM2EN"/>
</field>
<field><name>UART8EN</name><description>UART8 clock enable</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM2EN"/>
</field>
</fields>
</register>
<register>
<name>APB2ENR</name>
<displayName>APB2ENR</displayName>
<description>APB2 peripheral clock enable
register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIM1EN</name>
<description>TIM1 clock enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIM1EN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>The selected clock is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>The selected clock is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIM8EN</name>
<description>TIM8 clock enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field>
<name>USART1EN</name>
<description>USART1 clock enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field>
<name>USART6EN</name>
<description>USART6 clock enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field>
<name>ADC1EN</name>
<description>ADC1 clock enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field>
<name>ADC2EN</name>
<description>ADC2 clock enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field>
<name>ADC3EN</name>
<description>ADC3 clock enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field>
<name>SDIOEN</name>
<description>SDIO clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field>
<name>SPI1EN</name>
<description>SPI1 clock enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field>
<name>SYSCFGEN</name>
<description>System configuration controller clock
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field>
<name>TIM9EN</name>
<description>TIM9 clock enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field>
<name>TIM10EN</name>
<description>TIM10 clock enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field>
<name>TIM11EN</name>
<description>TIM11 clock enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field><name>SPI6EN</name><description>SPI6 clock enable</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field><name>SAI1EN</name><description>SAI1 clock enable</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field><name>LTDCEN</name><description>LTDC clock enable</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field><name>SPI4EN</name><description>SPI4 clock enable</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1EN"/>
</field>
<field><name>SPI5EN</name><description>SPI5 clock enable</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1EN"/>
</field>
</fields>
</register>
<register>
<name>AHB1LPENR</name>
<displayName>AHB1LPENR</displayName>
<description>AHB1 peripheral clock enable in low power
mode register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x7E6791FF</resetValue>
<fields>
<field>
<name>GPIOALPEN</name>
<description>IO port A clock enable during sleep
mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>GPIOALPEN</name><usage>read-write</usage><enumeratedValue><name>DisabledInSleep</name><description>Selected module is disabled during Sleep mode</description><value>0</value></enumeratedValue><enumeratedValue><name>EnabledInSleep</name><description>Selected module is enabled during Sleep mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>GPIOBLPEN</name>
<description>IO port B clock enable during Sleep
mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>GPIOCLPEN</name>
<description>IO port C clock enable during Sleep
mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>GPIODLPEN</name>
<description>IO port D clock enable during Sleep
mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>GPIOELPEN</name>
<description>IO port E clock enable during Sleep
mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>GPIOFLPEN</name>
<description>IO port F clock enable during Sleep
mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>GPIOGLPEN</name>
<description>IO port G clock enable during Sleep
mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>GPIOHLPEN</name>
<description>IO port H clock enable during Sleep
mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>GPIOILPEN</name>
<description>IO port I clock enable during Sleep
mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>CRCLPEN</name>
<description>CRC clock enable during Sleep
mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>FLITFLPEN</name>
<description>Flash interface clock enable during
Sleep mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>SRAM1LPEN</name>
<description>SRAM 1interface clock enable during
Sleep mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>SRAM2LPEN</name>
<description>SRAM 2 interface clock enable during
Sleep mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>BKPSRAMLPEN</name>
<description>Backup SRAM interface clock enable
during Sleep mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>DMA1LPEN</name>
<description>DMA1 clock enable during Sleep
mode</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>DMA2LPEN</name>
<description>DMA2 clock enable during Sleep
mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>ETHMACLPEN</name>
<description>Ethernet MAC clock enable during Sleep
mode</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>ETHMACTXLPEN</name>
<description>Ethernet transmission clock enable
during Sleep mode</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>ETHMACRXLPEN</name>
<description>Ethernet reception clock enable during
Sleep mode</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>ETHMACPTPLPEN</name>
<description>Ethernet PTP clock enable during Sleep
mode</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>OTGHSLPEN</name>
<description>USB OTG HS clock enable during Sleep
mode</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field>
<name>OTGHSULPILPEN</name>
<description>USB OTG HS ULPI clock enable during
Sleep mode</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field><name>SRAM3LPEN</name><description>SRAM3 interface clock enable during Sleep mode</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field><name>DMA2DLPEN</name><description>DMA2D clock enable during Sleep mode</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field><name>GPIOJLPEN</name><description>IO port J clock enable during Sleep mode</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
<field><name>GPIOKLPEN</name><description>IO port K clock enable during Sleep mode</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="GPIOALPEN"/>
</field>
</fields>
</register>
<register>
<name>AHB2LPENR</name>
<displayName>AHB2LPENR</displayName>
<description>AHB2 peripheral clock enable in low power
mode register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000000F1</resetValue>
<fields>
<field>
<name>OTGFSLPEN</name>
<description>USB OTG FS clock enable during Sleep
mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMILPEN"/>
</field>
<field>
<name>RNGLPEN</name>
<description>Random number generator clock enable
during Sleep mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMILPEN"/>
</field>
<field>
<name>HASHLPEN</name>
<description>Hash modules clock enable during Sleep
mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMILPEN"/>
</field>
<field>
<name>CRYPLPEN</name>
<description>Cryptography modules clock enable during
Sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DCMILPEN"/>
</field>
<field>
<name>DCMILPEN</name>
<description>Camera interface enable during Sleep
mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DCMILPEN</name><usage>read-write</usage><enumeratedValue><name>DisabledInSleep</name><description>Selected module is disabled during Sleep mode</description><value>0</value></enumeratedValue><enumeratedValue><name>EnabledInSleep</name><description>Selected module is enabled during Sleep mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AHB3LPENR</name>
<displayName>AHB3LPENR</displayName>
<description>AHB3 peripheral clock enable in low power
mode register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>FMCLPEN</name>
<description>Flexible memory controller module clock
enable during Sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FMCLPEN</name><usage>read-write</usage><enumeratedValue><name>DisabledInSleep</name><description>Selected module is disabled during Sleep mode</description><value>0</value></enumeratedValue><enumeratedValue><name>EnabledInSleep</name><description>Selected module is enabled during Sleep mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>APB1LPENR</name>
<displayName>APB1LPENR</displayName>
<description>APB1 peripheral clock enable in low power
mode register</description>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x36FEC9FF</resetValue>
<fields>
<field>
<name>TIM2LPEN</name>
<description>TIM2 clock enable during Sleep
mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIM2LPEN</name><usage>read-write</usage><enumeratedValue><name>DisabledInSleep</name><description>Selected module is disabled during Sleep mode</description><value>0</value></enumeratedValue><enumeratedValue><name>EnabledInSleep</name><description>Selected module is enabled during Sleep mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIM3LPEN</name>
<description>TIM3 clock enable during Sleep
mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>TIM4LPEN</name>
<description>TIM4 clock enable during Sleep
mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>TIM5LPEN</name>
<description>TIM5 clock enable during Sleep
mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>TIM6LPEN</name>
<description>TIM6 clock enable during Sleep
mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>TIM7LPEN</name>
<description>TIM7 clock enable during Sleep
mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>TIM12LPEN</name>
<description>TIM12 clock enable during Sleep
mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>TIM13LPEN</name>
<description>TIM13 clock enable during Sleep
mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>TIM14LPEN</name>
<description>TIM14 clock enable during Sleep
mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>WWDGLPEN</name>
<description>Window watchdog clock enable during
Sleep mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>SPI2LPEN</name>
<description>SPI2 clock enable during Sleep
mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>SPI3LPEN</name>
<description>SPI3 clock enable during Sleep
mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>USART2LPEN</name>
<description>USART2 clock enable during Sleep
mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>USART3LPEN</name>
<description>USART3 clock enable during Sleep
mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>UART4LPEN</name>
<description>UART4 clock enable during Sleep
mode</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>UART5LPEN</name>
<description>UART5 clock enable during Sleep
mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>I2C1LPEN</name>
<description>I2C1 clock enable during Sleep
mode</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>I2C2LPEN</name>
<description>I2C2 clock enable during Sleep
mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>I2C3LPEN</name>
<description>I2C3 clock enable during Sleep
mode</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>CAN1LPEN</name>
<description>CAN 1 clock enable during Sleep
mode</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>CAN2LPEN</name>
<description>CAN 2 clock enable during Sleep
mode</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>PWRLPEN</name>
<description>Power interface clock enable during
Sleep mode</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field>
<name>DACLPEN</name>
<description>DAC interface clock enable during Sleep
mode</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field><name>UART7LPEN</name><description>UART7 clock enable during Sleep mode</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
<field><name>UART8LPEN</name><description>UART8 clock enable during Sleep mode</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM2LPEN"/>
</field>
</fields>
</register>
<register>
<name>APB2LPENR</name>
<displayName>APB2LPENR</displayName>
<description>APB2 peripheral clock enabled in low power
mode register</description>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00075F33</resetValue>
<fields>
<field>
<name>TIM1LPEN</name>
<description>TIM1 clock enable during Sleep
mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIM1LPEN</name><usage>read-write</usage><enumeratedValue><name>DisabledInSleep</name><description>Selected module is disabled during Sleep mode</description><value>0</value></enumeratedValue><enumeratedValue><name>EnabledInSleep</name><description>Selected module is enabled during Sleep mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIM8LPEN</name>
<description>TIM8 clock enable during Sleep
mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field>
<name>USART1LPEN</name>
<description>USART1 clock enable during Sleep
mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field>
<name>USART6LPEN</name>
<description>USART6 clock enable during Sleep
mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field>
<name>ADC1LPEN</name>
<description>ADC1 clock enable during Sleep
mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field>
<name>ADC2LPEN</name>
<description>ADC2 clock enable during Sleep
mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field>
<name>ADC3LPEN</name>
<description>ADC 3 clock enable during Sleep
mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field>
<name>SDIOLPEN</name>
<description>SDIO clock enable during Sleep
mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field>
<name>SPI1LPEN</name>
<description>SPI 1 clock enable during Sleep
mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field>
<name>SYSCFGLPEN</name>
<description>System configuration controller clock
enable during Sleep mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field>
<name>TIM9LPEN</name>
<description>TIM9 clock enable during sleep
mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field>
<name>TIM10LPEN</name>
<description>TIM10 clock enable during Sleep
mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field>
<name>TIM11LPEN</name>
<description>TIM11 clock enable during Sleep
mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field><name>SPI6LPEN</name><description>SPI6 clock enable during Sleep mode</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field><name>SAI1LPEN</name><description>SAI1 clock enable during Sleep mode</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field><name>LTDCLPEN</name><description>LTDC clock enable during Sleep mode</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field><name>SPI4LPEN</name><description>SPI4 clock enable during Sleep mode</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
<field><name>SPI5LPEN</name><description>SPI5 clock enable during Sleep mode</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth><enumeratedValues derivedFrom="TIM1LPEN"/>
</field>
</fields>
</register>
<register>
<name>BDCR</name>
<displayName>BDCR</displayName>
<description>Backup domain control register</description>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BDRST</name>
<description>Backup domain software
reset</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>BDRST</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Reset not activated</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Reset the entire RTC domain</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RTCEN</name>
<description>RTC clock enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>RTCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RTC clock disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RTC clock enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LSEBYP</name>
<description>External low-speed oscillator
bypass</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>LSEBYP</name><usage>read-write</usage><enumeratedValue><name>NotBypassed</name><description>LSE crystal oscillator not bypassed</description><value>0</value></enumeratedValue><enumeratedValue><name>Bypassed</name><description>LSE crystal oscillator bypassed with external clock</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LSERDY</name>
<description>External low-speed oscillator
ready</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>LSERDYR</name><usage>read</usage><enumeratedValue><name>NotReady</name><description>LSE oscillator not ready</description><value>0</value></enumeratedValue><enumeratedValue><name>Ready</name><description>LSE oscillator ready</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LSEON</name>
<description>External low-speed oscillator
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>LSEON</name><usage>read-write</usage><enumeratedValue><name>Off</name><description>LSE oscillator Off</description><value>0</value></enumeratedValue><enumeratedValue><name>On</name><description>LSE oscillator On</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field><name>RTCSEL</name><description>RTC clock source selection</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth><enumeratedValues><name>RTCSEL</name><usage>read-write</usage><enumeratedValue><name>NoClock</name><description>No clock</description><value>0</value></enumeratedValue><enumeratedValue><name>LSE</name><description>LSE oscillator clock used as RTC clock</description><value>1</value></enumeratedValue><enumeratedValue><name>LSI</name><description>LSI oscillator clock used as RTC clock</description><value>2</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE oscillator clock divided by a prescaler used as RTC clock</description><value>3</value></enumeratedValue></enumeratedValues>
</field></fields>
</register>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>clock control &amp; status
register</description>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<resetValue>0x0E000000</resetValue>
<fields>
<field>
<name>LPWRRSTF</name>
<description>Low-power reset flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="BORRSTFR"/>
</field>
<field>
<name>WWDGRSTF</name>
<description>Window watchdog reset flag</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="BORRSTFR"/>
</field>
<field>
<name>WDGRSTF</name>
<description>Independent watchdog reset
flag</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="BORRSTFR"/>
</field>
<field>
<name>SFTRSTF</name>
<description>Software reset flag</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="BORRSTFR"/>
</field>
<field>
<name>PORRSTF</name>
<description>POR/PDR reset flag</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="BORRSTFR"/>
</field>
<field>
<name>PADRSTF</name>
<description>PIN reset flag</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="BORRSTFR"/>
</field>
<field>
<name>BORRSTF</name>
<description>BOR reset flag</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>BORRSTFR</name><usage>read</usage><enumeratedValue><name>NoReset</name><description>No reset has occured</description><value>0</value></enumeratedValue><enumeratedValue><name>Reset</name><description>A reset has occured</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RMVF</name>
<description>Remove reset flag</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>RMVFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the reset flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LSIRDY</name>
<description>Internal low-speed oscillator
ready</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>LSIRDYR</name><usage>read</usage><enumeratedValue><name>NotReady</name><description>LSI oscillator not ready</description><value>0</value></enumeratedValue><enumeratedValue><name>Ready</name><description>LSI oscillator ready</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LSION</name>
<description>Internal low-speed oscillator
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>LSION</name><usage>read-write</usage><enumeratedValue><name>Off</name><description>LSI oscillator Off</description><value>0</value></enumeratedValue><enumeratedValue><name>On</name><description>LSI oscillator On</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SSCGR</name>
<displayName>SSCGR</displayName>
<description>spread spectrum clock generation
register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SSCGEN</name>
<description>Spread spectrum modulation
enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SSCGEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Spread spectrum modulation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Spread spectrum modulation enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SPREADSEL</name>
<description>Spread Select</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SPREADSEL</name><usage>read-write</usage><enumeratedValue><name>Center</name><description>Center spread</description><value>0</value></enumeratedValue><enumeratedValue><name>Down</name><description>Down spread</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>INCSTEP</name>
<description>Incrementation step</description>
<bitOffset>13</bitOffset>
<bitWidth>15</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>32767</maximum></range></writeConstraint>
</field>
<field>
<name>MODPER</name>
<description>Modulation period</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>8191</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PLLI2SCFGR</name>
<displayName>PLLI2SCFGR</displayName>
<description>PLLI2S configuration register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x20003000</resetValue>
<fields>
<field>
<name>PLLI2SR</name>
<description>PLLI2S division factor for I2S
clocks</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<writeConstraint><range><minimum>2</minimum><maximum>7</maximum></range></writeConstraint>
</field>
<field>
<name>PLLI2SQ</name>
<description>PLLI2S division factor for SAI1
clock</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>2</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>PLLI2SN</name>
<description>PLLI2S multiplication factor for
VCO</description>
<bitOffset>6</bitOffset>
<bitWidth>9</bitWidth>
<writeConstraint><range><minimum>50</minimum><maximum>432</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DCKCFGR</name>
<displayName>DCKCFGR</displayName>
<description>RCC Dedicated Clock Configuration
Register</description>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLLI2SDIVQ</name>
<description>PLLI2S division factor for SAI1
clock</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues><name>PLLI2SDIVQ</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>PLLI2SDIVQ = /1</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>PLLI2SDIVQ = /2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div3</name><description>PLLI2SDIVQ = /3</description><value>2</value></enumeratedValue><enumeratedValue><name>Div4</name><description>PLLI2SDIVQ = /4</description><value>3</value></enumeratedValue><enumeratedValue><name>Div5</name><description>PLLI2SDIVQ = /5</description><value>4</value></enumeratedValue><enumeratedValue><name>Div6</name><description>PLLI2SDIVQ = /6</description><value>5</value></enumeratedValue><enumeratedValue><name>Div7</name><description>PLLI2SDIVQ = /7</description><value>6</value></enumeratedValue><enumeratedValue><name>Div8</name><description>PLLI2SDIVQ = /8</description><value>7</value></enumeratedValue><enumeratedValue><name>Div9</name><description>PLLI2SDIVQ = /9</description><value>8</value></enumeratedValue><enumeratedValue><name>Div10</name><description>PLLI2SDIVQ = /10</description><value>9</value></enumeratedValue><enumeratedValue><name>Div11</name><description>PLLI2SDIVQ = /11</description><value>10</value></enumeratedValue><enumeratedValue><name>Div12</name><description>PLLI2SDIVQ = /12</description><value>11</value></enumeratedValue><enumeratedValue><name>Div13</name><description>PLLI2SDIVQ = /13</description><value>12</value></enumeratedValue><enumeratedValue><name>Div14</name><description>PLLI2SDIVQ = /14</description><value>13</value></enumeratedValue><enumeratedValue><name>Div15</name><description>PLLI2SDIVQ = /15</description><value>14</value></enumeratedValue><enumeratedValue><name>Div16</name><description>PLLI2SDIVQ = /16</description><value>15</value></enumeratedValue><enumeratedValue><name>Div17</name><description>PLLI2SDIVQ = /17</description><value>16</value></enumeratedValue><enumeratedValue><name>Div18</name><description>PLLI2SDIVQ = /18</description><value>17</value></enumeratedValue><enumeratedValue><name>Div19</name><description>PLLI2SDIVQ = /19</description><value>18</value></enumeratedValue><enumeratedValue><name>Div20</name><description>PLLI2SDIVQ = /20</description><value>19</value></enumeratedValue><enumeratedValue><name>Div21</name><description>PLLI2SDIVQ = /21</description><value>20</value></enumeratedValue><enumeratedValue><name>Div22</name><description>PLLI2SDIVQ = /22</description><value>21</value></enumeratedValue><enumeratedValue><name>Div23</name><description>PLLI2SDIVQ = /23</description><value>22</value></enumeratedValue><enumeratedValue><name>Div24</name><description>PLLI2SDIVQ = /24</description><value>23</value></enumeratedValue><enumeratedValue><name>Div25</name><description>PLLI2SDIVQ = /25</description><value>24</value></enumeratedValue><enumeratedValue><name>Div26</name><description>PLLI2SDIVQ = /26</description><value>25</value></enumeratedValue><enumeratedValue><name>Div27</name><description>PLLI2SDIVQ = /27</description><value>26</value></enumeratedValue><enumeratedValue><name>Div28</name><description>PLLI2SDIVQ = /28</description><value>27</value></enumeratedValue><enumeratedValue><name>Div29</name><description>PLLI2SDIVQ = /29</description><value>28</value></enumeratedValue><enumeratedValue><name>Div30</name><description>PLLI2SDIVQ = /30</description><value>29</value></enumeratedValue><enumeratedValue><name>Div31</name><description>PLLI2SDIVQ = /31</description><value>30</value></enumeratedValue><enumeratedValue><name>Div32</name><description>PLLI2SDIVQ = /32</description><value>31</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PLLSAIDIVQ</name>
<description>PLLSAI division factor for SAI1
clock</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues><name>PLLSAIDIVQ</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>PLLSAIDIVQ = /1</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>PLLSAIDIVQ = /2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div3</name><description>PLLSAIDIVQ = /3</description><value>2</value></enumeratedValue><enumeratedValue><name>Div4</name><description>PLLSAIDIVQ = /4</description><value>3</value></enumeratedValue><enumeratedValue><name>Div5</name><description>PLLSAIDIVQ = /5</description><value>4</value></enumeratedValue><enumeratedValue><name>Div6</name><description>PLLSAIDIVQ = /6</description><value>5</value></enumeratedValue><enumeratedValue><name>Div7</name><description>PLLSAIDIVQ = /7</description><value>6</value></enumeratedValue><enumeratedValue><name>Div8</name><description>PLLSAIDIVQ = /8</description><value>7</value></enumeratedValue><enumeratedValue><name>Div9</name><description>PLLSAIDIVQ = /9</description><value>8</value></enumeratedValue><enumeratedValue><name>Div10</name><description>PLLSAIDIVQ = /10</description><value>9</value></enumeratedValue><enumeratedValue><name>Div11</name><description>PLLSAIDIVQ = /11</description><value>10</value></enumeratedValue><enumeratedValue><name>Div12</name><description>PLLSAIDIVQ = /12</description><value>11</value></enumeratedValue><enumeratedValue><name>Div13</name><description>PLLSAIDIVQ = /13</description><value>12</value></enumeratedValue><enumeratedValue><name>Div14</name><description>PLLSAIDIVQ = /14</description><value>13</value></enumeratedValue><enumeratedValue><name>Div15</name><description>PLLSAIDIVQ = /15</description><value>14</value></enumeratedValue><enumeratedValue><name>Div16</name><description>PLLSAIDIVQ = /16</description><value>15</value></enumeratedValue><enumeratedValue><name>Div17</name><description>PLLSAIDIVQ = /17</description><value>16</value></enumeratedValue><enumeratedValue><name>Div18</name><description>PLLSAIDIVQ = /18</description><value>17</value></enumeratedValue><enumeratedValue><name>Div19</name><description>PLLSAIDIVQ = /19</description><value>18</value></enumeratedValue><enumeratedValue><name>Div20</name><description>PLLSAIDIVQ = /20</description><value>19</value></enumeratedValue><enumeratedValue><name>Div21</name><description>PLLSAIDIVQ = /21</description><value>20</value></enumeratedValue><enumeratedValue><name>Div22</name><description>PLLSAIDIVQ = /22</description><value>21</value></enumeratedValue><enumeratedValue><name>Div23</name><description>PLLSAIDIVQ = /23</description><value>22</value></enumeratedValue><enumeratedValue><name>Div24</name><description>PLLSAIDIVQ = /24</description><value>23</value></enumeratedValue><enumeratedValue><name>Div25</name><description>PLLSAIDIVQ = /25</description><value>24</value></enumeratedValue><enumeratedValue><name>Div26</name><description>PLLSAIDIVQ = /26</description><value>25</value></enumeratedValue><enumeratedValue><name>Div27</name><description>PLLSAIDIVQ = /27</description><value>26</value></enumeratedValue><enumeratedValue><name>Div28</name><description>PLLSAIDIVQ = /28</description><value>27</value></enumeratedValue><enumeratedValue><name>Div29</name><description>PLLSAIDIVQ = /29</description><value>28</value></enumeratedValue><enumeratedValue><name>Div30</name><description>PLLSAIDIVQ = /30</description><value>29</value></enumeratedValue><enumeratedValue><name>Div31</name><description>PLLSAIDIVQ = /31</description><value>30</value></enumeratedValue><enumeratedValue><name>Div32</name><description>PLLSAIDIVQ = /32</description><value>31</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PLLSAIDIVR</name>
<description>division factor for
LCD_CLK</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PLLSAIDIVR</name><usage>read-write</usage><enumeratedValue><name>Div2</name><description>PLLSAIDIVR = /2</description><value>0</value></enumeratedValue><enumeratedValue><name>Div4</name><description>PLLSAIDIVR = /4</description><value>1</value></enumeratedValue><enumeratedValue><name>Div8</name><description>PLLSAIDIVR = /8</description><value>2</value></enumeratedValue><enumeratedValue><name>Div16</name><description>PLLSAIDIVR = /16</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SAI1ASRC</name>
<description>SAI1-A clock source
selection</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>SAI1ASRC</name><usage>read-write</usage><enumeratedValue><name>PLLSAI</name><description>SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ</description><value>0</value></enumeratedValue><enumeratedValue><name>PLLI2S</name><description>SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ</description><value>1</value></enumeratedValue><enumeratedValue><name>I2S_CKIN</name><description>SAI1-A clock frequency = Alternate function input frequency</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SAI1BSRC</name>
<description>SAI1-B clock source
selection</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>SAI1BSRC</name><usage>read-write</usage><enumeratedValue><name>PLLSAI</name><description>SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ</description><value>0</value></enumeratedValue><enumeratedValue><name>PLLI2S</name><description>SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ</description><value>1</value></enumeratedValue><enumeratedValue><name>I2S_CKIN</name><description>SAI1-B clock frequency = Alternate function input frequency</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIMPRE</name>
<description>Timers clocks prescalers
selection</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIMPRE</name><usage>read-write</usage><enumeratedValue><name>Mul2</name><description>If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx</description><value>0</value></enumeratedValue><enumeratedValue><name>Mul4</name><description>If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PLLSAICFGR</name>
<displayName>PLLSAICFGR</displayName>
<description>RCC PLL configuration register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x24003000</resetValue>
<fields>
<field>
<name>PLLSAIR</name>
<description>PLLSAI division factor for LCD
clock</description>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<writeConstraint><range><minimum>2</minimum><maximum>7</maximum></range></writeConstraint>
</field>
<field>
<name>PLLSAIQ</name>
<description>PLLSAI division factor for SAI1
clock</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>2</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>PLLSAIN</name>
<description>PLLSAI division factor for
VCO</description>
<bitOffset>6</bitOffset>
<bitWidth>9</bitWidth>
<writeConstraint><range><minimum>50</minimum><maximum>432</maximum></range></writeConstraint>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOK</name>
<description>General-purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x40022800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MODER15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>MODER0</name><usage>read-write</usage><enumeratedValue><name>Input</name><description>Input mode (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>Output</name><description>General purpose output mode</description><value>1</value></enumeratedValue><enumeratedValue><name>Alternate</name><description>Alternate function mode</description><value>2</value></enumeratedValue><enumeratedValue><name>Analog</name><description>Analog mode</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OT0</name><usage>read-write</usage><enumeratedValue><name>PushPull</name><description>Output push-pull (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>OpenDrain</name><description>Output open-drain</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OSPEEDR15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>OSPEEDR0</name><usage>read-write</usage><enumeratedValue><name>LowSpeed</name><description>Low speed</description><value>0</value></enumeratedValue><enumeratedValue><name>MediumSpeed</name><description>Medium speed</description><value>1</value></enumeratedValue><enumeratedValue><name>HighSpeed</name><description>High speed</description><value>2</value></enumeratedValue><enumeratedValue><name>VeryHighSpeed</name><description>Very high speed</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PUPDR15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PUPDR0</name><usage>read-write</usage><enumeratedValue><name>Floating</name><description>No pull-up, pull-down</description><value>0</value></enumeratedValue><enumeratedValue><name>PullUp</name><description>Pull-up</description><value>1</value></enumeratedValue><enumeratedValue><name>PullDown</name><description>Pull-down</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR15</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR14</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR13</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR12</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR11</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR10</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR9</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR8</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR7</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR6</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR5</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR4</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR3</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR2</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR1</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR0</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IDR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Input is logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Input is logic low</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR15</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR14</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR13</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR12</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR11</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR10</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR9</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR8</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR7</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR6</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR5</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR4</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR3</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR2</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR1</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR0</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ODR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Set output to logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Set output to logic low</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR15</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR14</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR13</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR12</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR11</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR10</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR9</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR8</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR7</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR6</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR5</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR4</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR3</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR2</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR0</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BR0W</name><usage>write</usage><enumeratedValue><name>Reset</name><description>Resets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BS15</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS14</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS13</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS12</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS11</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS10</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS9</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS8</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS7</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS6</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS5</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS4</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS2</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS0</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BS0W</name><usage>write</usage><enumeratedValue><name>Set</name><description>Sets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>GPIO port configuration lock
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCKK</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LCKK</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Port configuration lock key not active</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Port configuration lock key active</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LCK15</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK14</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK13</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK12</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK11</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK10</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LCK10</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LCK9</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK8</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK7</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK6</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK5</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK4</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK2</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LCK0</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRL7</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL6</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL5</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL4</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL3</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL2</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL1</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL0</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>AFRL0</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRH15</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH14</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH13</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH12</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH11</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH10</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH9</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH8</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>AFRH8</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="GPIOK">
<name>GPIOJ</name>
<baseAddress>0x40022400</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOK">
<name>GPIOI</name>
<baseAddress>0x40022000</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOK">
<name>GPIOH</name>
<baseAddress>0x40021C00</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOK">
<name>GPIOG</name>
<baseAddress>0x40021800</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOK">
<name>GPIOF</name>
<baseAddress>0x40021400</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOK">
<name>GPIOE</name>
<baseAddress>0x40021000</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOK">
<name>GPIOD</name>
<baseAddress>0X40020C00</baseAddress>
</peripheral>
<peripheral derivedFrom="GPIOK">
<name>GPIOC</name>
<baseAddress>0x40020800</baseAddress>
</peripheral>
<peripheral>
<name>GPIOB</name>
<description>General-purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x40020400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000280</resetValue>
<fields>
<field>
<name>MODER15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>MODER0</name><usage>read-write</usage><enumeratedValue><name>Input</name><description>Input mode (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>Output</name><description>General purpose output mode</description><value>1</value></enumeratedValue><enumeratedValue><name>Alternate</name><description>Alternate function mode</description><value>2</value></enumeratedValue><enumeratedValue><name>Analog</name><description>Analog mode</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OT0</name><usage>read-write</usage><enumeratedValue><name>PushPull</name><description>Output push-pull (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>OpenDrain</name><description>Output open-drain</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000000C0</resetValue>
<fields>
<field>
<name>OSPEEDR15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>OSPEEDR0</name><usage>read-write</usage><enumeratedValue><name>LowSpeed</name><description>Low speed</description><value>0</value></enumeratedValue><enumeratedValue><name>MediumSpeed</name><description>Medium speed</description><value>1</value></enumeratedValue><enumeratedValue><name>HighSpeed</name><description>High speed</description><value>2</value></enumeratedValue><enumeratedValue><name>VeryHighSpeed</name><description>Very high speed</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000100</resetValue>
<fields>
<field>
<name>PUPDR15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PUPDR0</name><usage>read-write</usage><enumeratedValue><name>Floating</name><description>No pull-up, pull-down</description><value>0</value></enumeratedValue><enumeratedValue><name>PullUp</name><description>Pull-up</description><value>1</value></enumeratedValue><enumeratedValue><name>PullDown</name><description>Pull-down</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR15</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR14</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR13</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR12</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR11</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR10</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR9</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR8</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR7</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR6</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR5</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR4</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR3</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR2</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR1</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR0</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IDR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Input is logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Input is logic low</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR15</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR14</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR13</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR12</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR11</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR10</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR9</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR8</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR7</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR6</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR5</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR4</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR3</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR2</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR1</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR0</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ODR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Set output to logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Set output to logic low</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR15</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR14</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR13</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR12</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR11</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR10</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR9</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR8</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR7</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR6</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR5</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR4</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR3</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR2</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR0</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BR0W</name><usage>write</usage><enumeratedValue><name>Reset</name><description>Resets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BS15</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS14</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS13</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS12</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS11</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS10</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS9</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS8</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS7</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS6</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS5</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS4</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS2</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS0</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BS0W</name><usage>write</usage><enumeratedValue><name>Set</name><description>Sets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>GPIO port configuration lock
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCKK</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LCKK</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Port configuration lock key not active</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Port configuration lock key active</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LCK15</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK14</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK13</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK12</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK11</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK10</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LCK10</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LCK9</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK8</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK7</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK6</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK5</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK4</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK2</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LCK0</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRL7</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL6</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL5</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL4</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL3</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL2</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL1</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL0</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>AFRL0</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRH15</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH14</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH13</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH12</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH11</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH10</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH9</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH8</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>AFRH8</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>GPIOA</name>
<description>General-purpose I/Os</description>
<groupName>GPIO</groupName>
<baseAddress>0x40020000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MODER</name>
<displayName>MODER</displayName>
<description>GPIO port mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xA8000000</resetValue>
<fields>
<field>
<name>MODER15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="MODER0"/>
</field>
<field>
<name>MODER0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>MODER0</name><usage>read-write</usage><enumeratedValue><name>Input</name><description>Input mode (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>Output</name><description>General purpose output mode</description><value>1</value></enumeratedValue><enumeratedValue><name>Alternate</name><description>Alternate function mode</description><value>2</value></enumeratedValue><enumeratedValue><name>Analog</name><description>Analog mode</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OTYPER</name>
<displayName>OTYPER</displayName>
<description>GPIO port output type register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OT15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OT0"/>
</field>
<field>
<name>OT0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OT0</name><usage>read-write</usage><enumeratedValue><name>PushPull</name><description>Output push-pull (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>OpenDrain</name><description>Output open-drain</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OSPEEDR</name>
<displayName>OSPEEDR</displayName>
<description>GPIO port output speed
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OSPEEDR15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="OSPEEDR0"/>
</field>
<field>
<name>OSPEEDR0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>OSPEEDR0</name><usage>read-write</usage><enumeratedValue><name>LowSpeed</name><description>Low speed</description><value>0</value></enumeratedValue><enumeratedValue><name>MediumSpeed</name><description>Medium speed</description><value>1</value></enumeratedValue><enumeratedValue><name>HighSpeed</name><description>High speed</description><value>2</value></enumeratedValue><enumeratedValue><name>VeryHighSpeed</name><description>Very high speed</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PUPDR</name>
<displayName>PUPDR</displayName>
<description>GPIO port pull-up/pull-down
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x64000000</resetValue>
<fields>
<field>
<name>PUPDR15</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR14</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR13</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR12</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR11</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR10</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR9</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR8</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR7</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR6</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR5</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR4</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR3</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR2</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR1</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="PUPDR0"/>
</field>
<field>
<name>PUPDR0</name>
<description>Port x configuration bits (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PUPDR0</name><usage>read-write</usage><enumeratedValue><name>Floating</name><description>No pull-up, pull-down</description><value>0</value></enumeratedValue><enumeratedValue><name>PullUp</name><description>Pull-up</description><value>1</value></enumeratedValue><enumeratedValue><name>PullDown</name><description>Pull-down</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>GPIO port input data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR15</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR14</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR13</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR12</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR11</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR10</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR9</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR8</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR7</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR6</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR5</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR4</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR3</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR2</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR1</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="IDR0"/>
</field>
<field>
<name>IDR0</name>
<description>Port input data (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IDR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Input is logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Input is logic low</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ODR</name>
<displayName>ODR</displayName>
<description>GPIO port output data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ODR15</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR14</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR13</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR12</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR11</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR10</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR9</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR8</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR7</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR6</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR5</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR4</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR3</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR2</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR1</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="ODR0"/>
</field>
<field>
<name>ODR0</name>
<description>Port output data (y =
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ODR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Set output to logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Set output to logic low</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BSRR</name>
<displayName>BSRR</displayName>
<description>GPIO port bit set/reset
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BR15</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR14</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR13</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR12</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR11</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR10</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR9</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR8</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR7</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR6</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR5</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR4</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR3</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR2</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR1</name>
<description>Port x reset bit y (y =
0..15)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BR0W"/>
</field>
<field>
<name>BR0</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BR0W</name><usage>write</usage><enumeratedValue><name>Reset</name><description>Resets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BS15</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS14</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS13</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS12</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS11</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS10</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS9</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS8</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS7</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS6</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS5</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS4</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS3</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS2</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS1</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BS0W"/>
</field>
<field>
<name>BS0</name>
<description>Port x set bit y (y=
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BS0W</name><usage>write</usage><enumeratedValue><name>Set</name><description>Sets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LCKR</name>
<displayName>LCKR</displayName>
<description>GPIO port configuration lock
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LCKK</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LCKK</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Port configuration lock key not active</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Port configuration lock key active</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LCK15</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK14</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK13</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK12</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK11</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK10"/>
</field>
<field>
<name>LCK10</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LCK10</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LCK9</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK8</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK7</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK6</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK5</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK4</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK3</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK2</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK1</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="LCK0"/>
</field>
<field>
<name>LCK0</name>
<description>Port x lock bit y (y=
0..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LCK0</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AFRL</name>
<displayName>AFRL</displayName>
<description>GPIO alternate function low
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRL7</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL6</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL5</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL4</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL3</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL2</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL1</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRL0"/>
</field>
<field>
<name>AFRL0</name>
<description>Alternate function selection for port x
bit y (y = 0..7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>AFRL0</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>AFRH</name>
<displayName>AFRH</displayName>
<description>GPIO alternate function high
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AFRH15</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH14</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH13</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH12</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH11</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH10</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH9</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues derivedFrom="AFRH8"/>
</field>
<field>
<name>AFRH8</name>
<description>Alternate function selection for port x
bit y (y = 8..15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>AFRH8</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SYSCFG</name>
<description>System configuration controller</description>
<groupName>SYSCFG</groupName>
<baseAddress>0x40013800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MEMRM</name>
<displayName>MEMRM</displayName>
<description>memory remap register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM_MODE</name>
<description>Memory mapping selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>FB_MODE</name>
<description>Flash bank mode selection</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SWP_FMC</name>
<description>FMC memory mapping swap</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PMC</name>
<displayName>PMC</displayName>
<description>peripheral mode configuration
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MII_RMII_SEL</name>
<description>Ethernet PHY interface
selection</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC1DC2</name>
<description>ADC1DC2</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC2DC2</name>
<description>ADC2DC2</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC3DC2</name>
<description>ADC3DC2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR1</name>
<displayName>EXTICR1</displayName>
<description>external interrupt configuration register
1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXTI3</name>
<description>EXTI x configuration (x = 0 to
3)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI2</name>
<description>EXTI x configuration (x = 0 to
3)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI1</name>
<description>EXTI x configuration (x = 0 to
3)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI0</name>
<description>EXTI x configuration (x = 0 to
3)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR2</name>
<displayName>EXTICR2</displayName>
<description>external interrupt configuration register
2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXTI7</name>
<description>EXTI x configuration (x = 4 to
7)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI6</name>
<description>EXTI x configuration (x = 4 to
7)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI5</name>
<description>EXTI x configuration (x = 4 to
7)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI4</name>
<description>EXTI x configuration (x = 4 to
7)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR3</name>
<displayName>EXTICR3</displayName>
<description>external interrupt configuration register
3</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXTI11</name>
<description>EXTI x configuration (x = 8 to
11)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI10</name>
<description>EXTI10</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI9</name>
<description>EXTI x configuration (x = 8 to
11)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI8</name>
<description>EXTI x configuration (x = 8 to
11)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXTICR4</name>
<displayName>EXTICR4</displayName>
<description>external interrupt configuration register
4</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>EXTI15</name>
<description>EXTI x configuration (x = 12 to
15)</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI14</name>
<description>EXTI x configuration (x = 12 to
15)</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI13</name>
<description>EXTI x configuration (x = 12 to
15)</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EXTI12</name>
<description>EXTI x configuration (x = 12 to
15)</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMPCR</name>
<displayName>CMPCR</displayName>
<description>Compensation cell control
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>READY</name>
<description>READY</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMP_PD</name>
<description>Compensation cell
power-down</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI1</name>
<description>Serial peripheral interface</description>
<groupName>SPI</groupName>
<baseAddress>0x40013000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI1</name>
<description>SPI1 global interrupt</description>
<value>35</value>
</interrupt>
<interrupt>
<name>SPI1</name>
<description>SPI1 global interrupt</description>
<value>35</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BIDIMODE</name>
<description>Bidirectional data mode
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BIDIMODE</name><usage>read-write</usage><enumeratedValue><name>Unidirectional</name><description>2-line unidirectional data mode selected</description><value>0</value></enumeratedValue><enumeratedValue><name>Bidirectional</name><description>1-line bidirectional data mode selected</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BIDIOE</name>
<description>Output enable in bidirectional
mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BIDIOE</name><usage>read-write</usage><enumeratedValue><name>OutputDisabled</name><description>Output disabled (receive-only mode)</description><value>0</value></enumeratedValue><enumeratedValue><name>OutputEnabled</name><description>Output enabled (transmit-only mode)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CRCEN</name>
<description>Hardware CRC calculation
enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CRCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CRC calculation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CRC calculation enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CRCNEXT</name>
<description>CRC transfer next</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CRCNEXT</name><usage>read-write</usage><enumeratedValue><name>TxBuffer</name><description>Next transmit value is from Tx buffer</description><value>0</value></enumeratedValue><enumeratedValue><name>CRC</name><description>Next transmit value is from Tx CRC register</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DFF</name>
<description>Data frame format</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DFF</name><usage>read-write</usage><enumeratedValue><name>EightBit</name><description>8-bit data frame format is selected for transmission/reception</description><value>0</value></enumeratedValue><enumeratedValue><name>SixteenBit</name><description>16-bit data frame format is selected for transmission/reception</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXONLY</name>
<description>Receive only</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RXONLY</name><usage>read-write</usage><enumeratedValue><name>FullDuplex</name><description>Full duplex (Transmit and receive)</description><value>0</value></enumeratedValue><enumeratedValue><name>OutputDisabled</name><description>Output disabled (Receive-only mode)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SSM</name>
<description>Software slave management</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SSM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Software slave management disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Software slave management enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SSI</name>
<description>Internal slave select</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SSI</name><usage>read-write</usage><enumeratedValue><name>SlaveSelected</name><description>0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored</description><value>0</value></enumeratedValue><enumeratedValue><name>SlaveNotSelected</name><description>1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LSBFIRST</name>
<description>Frame format</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LSBFIRST</name><usage>read-write</usage><enumeratedValue><name>MSBFirst</name><description>Data is transmitted/received with the MSB first</description><value>0</value></enumeratedValue><enumeratedValue><name>LSBFirst</name><description>Data is transmitted/received with the LSB first</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SPE</name>
<description>SPI enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Peripheral disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Peripheral enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BR</name>
<description>Baud rate control</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>BR</name><usage>read-write</usage><enumeratedValue><name>Div2</name><description>f_PCLK / 2</description><value>0</value></enumeratedValue><enumeratedValue><name>Div4</name><description>f_PCLK / 4</description><value>1</value></enumeratedValue><enumeratedValue><name>Div8</name><description>f_PCLK / 8</description><value>2</value></enumeratedValue><enumeratedValue><name>Div16</name><description>f_PCLK / 16</description><value>3</value></enumeratedValue><enumeratedValue><name>Div32</name><description>f_PCLK / 32</description><value>4</value></enumeratedValue><enumeratedValue><name>Div64</name><description>f_PCLK / 64</description><value>5</value></enumeratedValue><enumeratedValue><name>Div128</name><description>f_PCLK / 128</description><value>6</value></enumeratedValue><enumeratedValue><name>Div256</name><description>f_PCLK / 256</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MSTR</name>
<description>Master selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MSTR</name><usage>read-write</usage><enumeratedValue><name>Slave</name><description>Slave configuration</description><value>0</value></enumeratedValue><enumeratedValue><name>Master</name><description>Master configuration</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CPOL</name><usage>read-write</usage><enumeratedValue><name>IdleLow</name><description>CK to 0 when idle</description><value>0</value></enumeratedValue><enumeratedValue><name>IdleHigh</name><description>CK to 1 when idle</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CPHA</name><usage>read-write</usage><enumeratedValue><name>FirstEdge</name><description>The first clock transition is the first data capture edge</description><value>0</value></enumeratedValue><enumeratedValue><name>SecondEdge</name><description>The second clock transition is the first data capture edge</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TXEIE</name>
<description>Tx buffer empty interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TXEIE</name><usage>read-write</usage><enumeratedValue><name>Masked</name><description>TXE interrupt masked</description><value>0</value></enumeratedValue><enumeratedValue><name>NotMasked</name><description>TXE interrupt not masked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXNEIE</name>
<description>RX buffer not empty interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RXNEIE</name><usage>read-write</usage><enumeratedValue><name>Masked</name><description>RXE interrupt masked</description><value>0</value></enumeratedValue><enumeratedValue><name>NotMasked</name><description>RXE interrupt not masked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ERRIE</name><usage>read-write</usage><enumeratedValue><name>Masked</name><description>Error interrupt masked</description><value>0</value></enumeratedValue><enumeratedValue><name>NotMasked</name><description>Error interrupt not masked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FRF</name>
<description>Frame format</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FRF</name><usage>read-write</usage><enumeratedValue><name>Motorola</name><description>SPI Motorola mode</description><value>0</value></enumeratedValue><enumeratedValue><name>TI</name><description>SPI TI mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SSOE</name>
<description>SS output enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SSOE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>SS output is disabled in master mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>SS output is enabled in master mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TXDMAEN</name>
<description>Tx buffer DMA enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TXDMAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Tx buffer DMA disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Tx buffer DMA enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXDMAEN</name>
<description>Rx buffer DMA enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RXDMAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Rx buffer DMA disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Rx buffer DMA enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x0002</resetValue>
<fields>
<field>
<name>FRE</name>
<description>TI frame format error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>FRER</name><usage>read</usage><enumeratedValue><name>NoError</name><description>No frame format error</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A frame format error occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BSY</name>
<description>Busy flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>BSYR</name><usage>read</usage><enumeratedValue><name>NotBusy</name><description>SPI not busy</description><value>0</value></enumeratedValue><enumeratedValue><name>Busy</name><description>SPI busy</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OVR</name>
<description>Overrun flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>OVRR</name><usage>read</usage><enumeratedValue><name>NoOverrun</name><description>No overrun occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Overrun occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MODF</name>
<description>Mode fault</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>MODFR</name><usage>read</usage><enumeratedValue><name>NoFault</name><description>No mode fault occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Fault</name><description>Mode fault occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CRCERR</name>
<description>CRC error flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>CRCERR</name><usage>read-write</usage><enumeratedValue><name>Match</name><description>CRC value received matches the SPIx_RXCRCR value</description><value>0</value></enumeratedValue><enumeratedValue><name>NoMatch</name><description>CRC value received does not match the SPIx_RXCRCR value</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDR</name>
<description>Underrun flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>UDRR</name><usage>read</usage><enumeratedValue><name>NoUnderrun</name><description>No underrun occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Underrun</name><description>Underrun occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CHSIDE</name>
<description>Channel side</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>CHSIDE</name><usage>read-write</usage><enumeratedValue><name>Left</name><description>Channel left has to be transmitted or has been received</description><value>0</value></enumeratedValue><enumeratedValue><name>Right</name><description>Channel right has to be transmitted or has been received</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TXE</name>
<description>Transmit buffer empty</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>TXE</name><usage>read-write</usage><enumeratedValue><name>NotEmpty</name><description>Tx buffer not empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Empty</name><description>Tx buffer empty</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXNE</name>
<description>Receive buffer not empty</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>RXNE</name><usage>read-write</usage><enumeratedValue><name>Empty</name><description>Rx buffer empty</description><value>0</value></enumeratedValue><enumeratedValue><name>NotEmpty</name><description>Rx buffer not empty</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>data register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DR</name>
<description>Data register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CRCPR</name>
<displayName>CRCPR</displayName>
<description>CRC polynomial register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0007</resetValue>
<fields>
<field>
<name>CRCPOLY</name>
<description>CRC polynomial register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>RXCRCR</name>
<displayName>RXCRCR</displayName>
<description>RX CRC register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>RxCRC</name>
<description>Rx CRC register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>TXCRCR</name>
<displayName>TXCRCR</displayName>
<description>TX CRC register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TxCRC</name>
<description>Tx CRC register</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>I2SCFGR</name>
<displayName>I2SCFGR</displayName>
<description>I2S configuration register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>I2SMOD</name>
<description>I2S mode selection</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>I2SMOD</name><usage>read-write</usage><enumeratedValue><name>SPIMode</name><description>SPI mode is selected</description><value>0</value></enumeratedValue><enumeratedValue><name>I2SMode</name><description>I2S mode is selected</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>I2SE</name>
<description>I2S Enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>I2SE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>I2S peripheral is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>I2S peripheral is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>I2SCFG</name>
<description>I2S configuration mode</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>I2SCFG</name><usage>read-write</usage><enumeratedValue><name>SlaveTx</name><description>Slave - transmit</description><value>0</value></enumeratedValue><enumeratedValue><name>SlaveRx</name><description>Slave - receive</description><value>1</value></enumeratedValue><enumeratedValue><name>MasterTx</name><description>Master - transmit</description><value>2</value></enumeratedValue><enumeratedValue><name>MasterRx</name><description>Master - receive</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PCMSYNC</name>
<description>PCM frame synchronization</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PCMSYNC</name><usage>read-write</usage><enumeratedValue><name>Short</name><description>Short frame synchronisation</description><value>0</value></enumeratedValue><enumeratedValue><name>Long</name><description>Long frame synchronisation</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>I2SSTD</name>
<description>I2S standard selection</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>I2SSTD</name><usage>read-write</usage><enumeratedValue><name>Philips</name><description>I2S Philips standard</description><value>0</value></enumeratedValue><enumeratedValue><name>MSB</name><description>MSB justified standard</description><value>1</value></enumeratedValue><enumeratedValue><name>LSB</name><description>LSB justified standard</description><value>2</value></enumeratedValue><enumeratedValue><name>PCM</name><description>PCM standard</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CKPOL</name>
<description>Steady state clock
polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CKPOL</name><usage>read-write</usage><enumeratedValue><name>IdleLow</name><description>I2S clock inactive state is low level</description><value>0</value></enumeratedValue><enumeratedValue><name>IdleHigh</name><description>I2S clock inactive state is high level</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DATLEN</name>
<description>Data length to be
transferred</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>DATLEN</name><usage>read-write</usage><enumeratedValue><name>SixteenBit</name><description>16-bit data length</description><value>0</value></enumeratedValue><enumeratedValue><name>TwentyFourBit</name><description>24-bit data length</description><value>1</value></enumeratedValue><enumeratedValue><name>ThirtyTwoBit</name><description>32-bit data length</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CHLEN</name>
<description>Channel length (number of bits per audio
channel)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CHLEN</name><usage>read-write</usage><enumeratedValue><name>SixteenBit</name><description>16-bit wide</description><value>0</value></enumeratedValue><enumeratedValue><name>ThirtyTwoBit</name><description>32-bit wide</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>I2SPR</name>
<displayName>I2SPR</displayName>
<description>I2S prescaler register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>00000010</resetValue>
<fields>
<field>
<name>MCKOE</name>
<description>Master clock output enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MCKOE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Master clock output is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Master clock output is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ODD</name>
<description>Odd factor for the
prescaler</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ODD</name><usage>read-write</usage><enumeratedValue><name>Even</name><description>Real divider value is I2SDIV * 2</description><value>0</value></enumeratedValue><enumeratedValue><name>Odd</name><description>Real divider value is (I2SDIV * 2) + 1</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>I2SDIV</name>
<description>I2S Linear prescaler</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>2</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI2</name>
<baseAddress>0x40003800</baseAddress>
<interrupt>
<name>SPI2</name>
<description>SPI2 global interrupt</description>
<value>36</value>
</interrupt>
<interrupt>
<name>SPI2</name>
<description>SPI2 global interrupt</description>
<value>36</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI3</name>
<baseAddress>0x40003C00</baseAddress>
<interrupt>
<name>SPI3</name>
<description>SPI3 global interrupt</description>
<value>51</value>
</interrupt>
<interrupt>
<name>SPI3</name>
<description>SPI3 global interrupt</description>
<value>51</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>I2S2ext</name>
<baseAddress>0x40003400</baseAddress>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>I2S3ext</name>
<baseAddress>0x40004000</baseAddress>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI4</name>
<baseAddress>0x40013400</baseAddress>
<interrupt>
<name>SPI4</name>
<description>SPI 4 global interrupt</description>
<value>84</value>
</interrupt>
<interrupt>
<name>SPI4</name>
<description>SPI 4 global interrupt</description>
<value>84</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI5</name>
<baseAddress>0x40015000</baseAddress>
<interrupt>
<name>SPI5</name>
<description>SPI 5 global interrupt</description>
<value>85</value>
</interrupt>
<interrupt>
<name>SPI5</name>
<description>SPI 5 global interrupt</description>
<value>85</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="SPI1">
<name>SPI6</name>
<baseAddress>0x40015400</baseAddress>
<interrupt>
<name>SPI6</name>
<description>SPI 6 global interrupt</description>
<value>86</value>
</interrupt>
<interrupt>
<name>SPI6</name>
<description>SPI 6 global interrupt</description>
<value>86</value>
</interrupt>
</peripheral>
<peripheral>
<name>SDIO</name>
<description>Secure digital input/output
interface</description>
<groupName>SDIO</groupName>
<baseAddress>0x40012C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SDIO</name>
<description>SDIO global interrupt</description>
<value>49</value>
</interrupt>
<interrupt>
<name>SDIO</name>
<description>SDIO global interrupt</description>
<value>49</value>
</interrupt>
<registers>
<register>
<name>POWER</name>
<displayName>POWER</displayName>
<description>power control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PWRCTRL</name>
<description>PWRCTRL</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PWRCTRL</name><usage>read-write</usage><enumeratedValue><name>PowerOff</name><description>Power off</description><value>0</value></enumeratedValue><enumeratedValue><name>PowerOn</name><description>Power on</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLKCR</name>
<displayName>CLKCR</displayName>
<description>SDI clock control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HWFC_EN</name>
<description>HW Flow Control enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>HWFC_EN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>HW Flow Control is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>HW Flow Control is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>NEGEDGE</name>
<description>SDIO_CK dephasing selection
bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>NEGEDGE</name><usage>read-write</usage><enumeratedValue><name>Rising</name><description>SDIO_CK generated on the rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Falling</name><description>SDIO_CK generated on the falling edge</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WIDBUS</name>
<description>Wide bus mode enable bit</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>WIDBUS</name><usage>read-write</usage><enumeratedValue><name>BusWidth1</name><description>1 lane wide bus</description><value>0</value></enumeratedValue><enumeratedValue><name>BusWidth4</name><description>4 lane wide bus</description><value>1</value></enumeratedValue><enumeratedValue><name>BusWidth8</name><description>8 lane wide bus</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BYPASS</name>
<description>Clock divider bypass enable
bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BYPASS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal.</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>SDIOCLK directly drives the SDIO_CK output signal</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PWRSAV</name>
<description>Power saving configuration
bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PWRSAV</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>SDIO_CK is only enabled when the bus is active</description><value>1</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>SDIO_CK clock is always enabled</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CLKEN</name>
<description>Clock enable bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CLKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Disable clock</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enable clock</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Clock divide factor</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ARG</name>
<displayName>ARG</displayName>
<description>argument register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMDARG</name>
<description>Command argument</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CMD</name>
<displayName>CMD</displayName>
<description>command register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CE_ATACMD</name>
<description>CE-ATA command</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CE_ATACMD</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CE-ATA command disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CE-ATA command enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>nIEN</name>
<description>not Interrupt Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>nIEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupts to the CE-ATA not disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt to the CE-ATA are disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ENCMDcompl</name>
<description>Enable CMD completion</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ENCMDcompl</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Command complete signal disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Command complete signal enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SDIOSuspend</name>
<description>SD I/O suspend command</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SDIOSuspend</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Next command is not a SDIO suspend command</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Next command send is a SDIO suspend command</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CPSMEN</name>
<description>Command path state machine (CPSM) Enable
bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CPSMEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Command path state machine disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Command path state machine enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WAITPEND</name>
<description>CPSM Waits for ends of data transfer
(CmdPend internal signal).</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WAITPEND</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Don't wait for data end</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wait for end of data transfer signal before sending command</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WAITINT</name>
<description>CPSM waits for interrupt
request</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WAITINT</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Don't wait for interrupt request</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wait for interrupt request</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WAITRESP</name>
<description>Wait for response bits</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>WAITRESP</name><usage>read-write</usage><enumeratedValue><name>NoResponse</name><description>No response</description><value>0</value></enumeratedValue><enumeratedValue><name>ShortResponse</name><description>Short response</description><value>1</value></enumeratedValue><enumeratedValue><name>NoResponse2</name><description>No reponse</description><value>2</value></enumeratedValue><enumeratedValue><name>LongResponse</name><description>Long reponse</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CMDINDEX</name>
<description>Command index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>RESPCMD</name>
<displayName>RESPCMD</displayName>
<description>command response register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RESPCMD</name>
<description>Response command index</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>RESP1</name>
<displayName>RESP1</displayName>
<description>response 1..4 register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARDSTATUS1</name>
<description>see Table 132.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>RESP2</name>
<displayName>RESP2</displayName>
<description>response 1..4 register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARDSTATUS2</name>
<description>see Table 132.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>RESP3</name>
<displayName>RESP3</displayName>
<description>response 1..4 register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARDSTATUS3</name>
<description>see Table 132.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>RESP4</name>
<displayName>RESP4</displayName>
<description>response 1..4 register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARDSTATUS4</name>
<description>see Table 132.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DTIMER</name>
<displayName>DTIMER</displayName>
<description>data timer register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATATIME</name>
<description>Data timeout period</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DLEN</name>
<displayName>DLEN</displayName>
<description>data length register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATALENGTH</name>
<description>Data length value</description>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>33554431</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DCTRL</name>
<displayName>DCTRL</displayName>
<description>data control register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDIOEN</name>
<description>SD I/O enable functions</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SDIOEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>SDIO operations disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>SDIO operations enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RWMOD</name>
<description>Read wait mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RWMOD</name><usage>read-write</usage><enumeratedValue><name>D2</name><description>Read wait control stopping using SDIO_D2</description><value>0</value></enumeratedValue><enumeratedValue><name>Ck</name><description>Read wait control using SDIO_CK</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RWSTOP</name>
<description>Read wait stop</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RWSTOP</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Read wait in progress if RWSTART is enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enable for read wait stop if RWSTART is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RWSTART</name>
<description>Read wait start</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RWSTART</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Don't start read wait operation</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Read wait operation starts</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DBLOCKSIZE</name>
<description>Data block size</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Dma disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Dma enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DTMODE</name>
<description>Data transfer mode selection 1: Stream
or SDIO multibyte data transfer.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DTMODE</name><usage>read-write</usage><enumeratedValue><name>BlockMode</name><description>Bloack data transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>StreamMode</name><description>Stream or SDIO multibyte data transfer</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DTDIR</name>
<description>Data transfer direction
selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DTDIR</name><usage>read-write</usage><enumeratedValue><name>ControllerToCard</name><description>From controller to card</description><value>0</value></enumeratedValue><enumeratedValue><name>CardToController</name><description>From card to controller</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DTEN</name>
<description>DTEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Start transfer</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DCOUNT</name>
<displayName>DCOUNT</displayName>
<description>data counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATACOUNT</name>
<description>Data count value</description>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>33554431</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>STA</name>
<displayName>STA</displayName>
<description>status register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CEATAEND</name>
<description>CE-ATA command completion signal
received for CMD61</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CEATAEND</name><usage>read-write</usage><enumeratedValue><name>NotReceived</name><description>Completion signal not received</description><value>0</value></enumeratedValue><enumeratedValue><name>Received</name><description>CE-ATA command completion signal received for CMD61</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SDIOIT</name>
<description>SDIO interrupt received</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SDIOIT</name><usage>read-write</usage><enumeratedValue><name>NotReceived</name><description>SDIO interrupt not receieved</description><value>0</value></enumeratedValue><enumeratedValue><name>Received</name><description>SDIO interrupt received</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXDAVL</name>
<description>Data available in receive
FIFO</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RXDAVL</name><usage>read-write</usage><enumeratedValue><name>NotAvailable</name><description>Data not available in receive FIFO</description><value>0</value></enumeratedValue><enumeratedValue><name>Available</name><description>Data available in receive FIFO</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TXDAVL</name>
<description>Data available in transmit
FIFO</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TXDAVL</name><usage>read-write</usage><enumeratedValue><name>NotAvailable</name><description>Data not available in transmit FIFO</description><value>0</value></enumeratedValue><enumeratedValue><name>Available</name><description>Data available in transmit FIFO</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXFIFOE</name>
<description>Receive FIFO empty</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RXFIFOE</name><usage>read-write</usage><enumeratedValue><name>NotEmpty</name><description>Receive FIFO not empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Empty</name><description>Receive FIFO empty</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TXFIFOE</name>
<description>Transmit FIFO empty</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TXFIFOE</name><usage>read-write</usage><enumeratedValue><name>NotEmpty</name><description>Transmit FIFO not empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Empty</name><description>Transmit FIFO empty. When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXFIFOF</name>
<description>Receive FIFO full</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RXFIFOF</name><usage>read-write</usage><enumeratedValue><name>NotFull</name><description>Transmit FIFO not full</description><value>0</value></enumeratedValue><enumeratedValue><name>Full</name><description>Receive FIFO full. When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TXFIFOF</name>
<description>Transmit FIFO full</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TXFIFOF</name><usage>read-write</usage><enumeratedValue><name>NotFull</name><description>Transmit FIFO not full</description><value>0</value></enumeratedValue><enumeratedValue><name>Full</name><description>Transmit FIFO full</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXFIFOHF</name>
<description>Receive FIFO half full: there are at
least 8 words in the FIFO</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RXFIFOHF</name><usage>read-write</usage><enumeratedValue><name>NotHalfFull</name><description>Receive FIFO not half full</description><value>0</value></enumeratedValue><enumeratedValue><name>HalfFull</name><description>Receive FIFO half full. At least 8 words in the FIFO</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TXFIFOHE</name>
<description>Transmit FIFO half empty: at least 8
words can be written into the FIFO</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TXFIFOHE</name><usage>read-write</usage><enumeratedValue><name>NotHalfEmpty</name><description>Transmit FIFO not half empty</description><value>0</value></enumeratedValue><enumeratedValue><name>HalfEmpty</name><description>Transmit FIFO half empty. At least 8 words can be written into the FIFO</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXACT</name>
<description>Data receive in progress</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RXACT</name><usage>read-write</usage><enumeratedValue><name>NotInProgress</name><description>Data receive not in progress</description><value>0</value></enumeratedValue><enumeratedValue><name>InProgress</name><description>Data receive in progress</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TXACT</name>
<description>Data transmit in progress</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TXACT</name><usage>read-write</usage><enumeratedValue><name>NotInProgress</name><description>Data transmit is not in progress</description><value>0</value></enumeratedValue><enumeratedValue><name>InProgress</name><description>Data transmit in progress</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CMDACT</name>
<description>Command transfer in
progress</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CMDACT</name><usage>read-write</usage><enumeratedValue><name>NotInProgress</name><description>Command transfer not in progress</description><value>0</value></enumeratedValue><enumeratedValue><name>InProgress</name><description>Command tranfer in progress</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DBCKEND</name>
<description>Data block sent/received (CRC check
passed)</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DBCKEND</name><usage>read-write</usage><enumeratedValue><name>NotTransferred</name><description>Data block not sent/received (CRC check failed)</description><value>0</value></enumeratedValue><enumeratedValue><name>Transferred</name><description>Data block sent/received (CRC check passed)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>STBITERR</name>
<description>Start bit not detected on all data
signals in wide bus mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>STBITERR</name><usage>read-write</usage><enumeratedValue><name>Detected</name><description>No start bit detected error</description><value>0</value></enumeratedValue><enumeratedValue><name>NotDetected</name><description>Start bit not detected error</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DATAEND</name>
<description>Data end (data counter, SDIDCOUNT, is
zero)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DATAEND</name><usage>read-write</usage><enumeratedValue><name>Done</name><description>Data end (DCOUNT, is zero)</description><value>1</value></enumeratedValue><enumeratedValue><name>NotDone</name><description>Not done</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CMDSENT</name>
<description>Command sent (no response
required)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CMDSENT</name><usage>read-write</usage><enumeratedValue><name>NotSent</name><description>Command not sent</description><value>0</value></enumeratedValue><enumeratedValue><name>Sent</name><description>Command sent (no response required)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CMDREND</name>
<description>Command response received (CRC check
passed)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CMDREND</name><usage>read-write</usage><enumeratedValue><name>NotDone</name><description>Command not done</description><value>0</value></enumeratedValue><enumeratedValue><name>Done</name><description>Command response received (CRC check passed)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXOVERR</name>
<description>Received FIFO overrun
error</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RXOVERR</name><usage>read-write</usage><enumeratedValue><name>NoOverrun</name><description>No FIFO overrun error</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Receive FIFO overrun error</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TXUNDERR</name>
<description>Transmit FIFO underrun
error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TXUNDERR</name><usage>read-write</usage><enumeratedValue><name>NoUnderrun</name><description>No transmit FIFO underrun error</description><value>0</value></enumeratedValue><enumeratedValue><name>Underrun</name><description>Transmit FIFO underrun error</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DTIMEOUT</name>
<description>Data timeout</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DTIMEOUT</name><usage>read-write</usage><enumeratedValue><name>NoTimeout</name><description>No data timeout</description><value>0</value></enumeratedValue><enumeratedValue><name>Timeout</name><description>Data timeout</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CTIMEOUT</name>
<description>Command response timeout</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CTIMEOUT</name><usage>read-write</usage><enumeratedValue><name>NoTimeout</name><description>No Command timeout</description><value>0</value></enumeratedValue><enumeratedValue><name>Timeout</name><description>Command timeout</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DCRCFAIL</name>
<description>Data block sent/received (CRC check
failed)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DCRCFAIL</name><usage>read-write</usage><enumeratedValue><name>NotFailed</name><description>No Data block sent/received crc check fail</description><value>0</value></enumeratedValue><enumeratedValue><name>Failed</name><description>Data block sent/received crc failed</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CCRCFAIL</name>
<description>Command response received (CRC check
failed)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CCRCFAIL</name><usage>read-write</usage><enumeratedValue><name>NotFailed</name><description>Command response received, crc check passed</description><value>0</value></enumeratedValue><enumeratedValue><name>Failed</name><description>Command response received, crc check failed</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>interrupt clear register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CEATAENDC</name>
<description>CEATAEND flag clear bit</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>SDIOITC</name>
<description>SDIOIT flag clear bit</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>DBCKENDC</name>
<description>DBCKEND flag clear bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>STBITERRC</name>
<description>STBITERR flag clear bit</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>DATAENDC</name>
<description>DATAEND flag clear bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>CMDSENTC</name>
<description>CMDSENT flag clear bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>CMDRENDC</name>
<description>CMDREND flag clear bit</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>RXOVERRC</name>
<description>RXOVERR flag clear bit</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>TXUNDERRC</name>
<description>TXUNDERR flag clear bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>DTIMEOUTC</name>
<description>DTIMEOUT flag clear bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>CTIMEOUTC</name>
<description>CTIMEOUT flag clear bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>DCRCFAILC</name>
<description>DCRCFAIL flag clear bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILCW"/>
</field>
<field>
<name>CCRCFAILC</name>
<description>CCRCFAIL flag clear bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CCRCFAILCW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MASK</name>
<displayName>MASK</displayName>
<description>mask register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CEATAENDIE</name>
<description>CE-ATA command completion signal
received interrupt enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>SDIOITIE</name>
<description>SDIO mode interrupt received interrupt
enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>RXDAVLIE</name>
<description>Data available in Rx FIFO interrupt
enable</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>TXDAVLIE</name>
<description>Data available in Tx FIFO interrupt
enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>RXFIFOEIE</name>
<description>Rx FIFO empty interrupt
enable</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>TXFIFOEIE</name>
<description>Tx FIFO empty interrupt
enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>RXFIFOFIE</name>
<description>Rx FIFO full interrupt
enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>TXFIFOFIE</name>
<description>Tx FIFO full interrupt
enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>RXFIFOHFIE</name>
<description>Rx FIFO half full interrupt
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>TXFIFOHEIE</name>
<description>Tx FIFO half empty interrupt
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>RXACTIE</name>
<description>Data receive acting interrupt
enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>TXACTIE</name>
<description>Data transmit acting interrupt
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>CMDACTIE</name>
<description>Command acting interrupt
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>DBCKENDIE</name>
<description>Data block end interrupt
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>STBITERRIE</name>
<description>Start bit error interrupt
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>DATAENDIE</name>
<description>Data end interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>CMDSENTIE</name>
<description>Command sent interrupt
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>CMDRENDIE</name>
<description>Command response received interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>RXOVERRIE</name>
<description>Rx FIFO overrun error interrupt
enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>TXUNDERRIE</name>
<description>Tx FIFO underrun error interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>DTIMEOUTIE</name>
<description>Data timeout interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>CTIMEOUTIE</name>
<description>Command timeout interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>DCRCFAILIE</name>
<description>Data CRC fail interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CCRCFAILIE"/>
</field>
<field>
<name>CCRCFAILIE</name>
<description>Command CRC fail interrupt
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CCRCFAILIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FIFOCNT</name>
<displayName>FIFOCNT</displayName>
<description>FIFO counter register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FIFOCOUNT</name>
<description>Remaining number of words to be written
to or read from the FIFO.</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>16777215</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>FIFO</name>
<displayName>FIFO</displayName>
<description>data FIFO register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FIFOData</name>
<description>Receive and transmit FIFO
data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>ADC1</name>
<description>Analog-to-digital converter</description>
<groupName>ADC</groupName>
<baseAddress>0x40012000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x51</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OVR</name>
<description>Overrun</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OVR</name><usage>read-write</usage><enumeratedValue><name>NoOverrun</name><description>No overrun occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Overrun occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>STRT</name>
<description>Regular channel start flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>STRT</name><usage>read-write</usage><enumeratedValue><name>NotStarted</name><description>No regular channel conversion started</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Regular channel conversion has started</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>JSTRT</name>
<description>Injected channel start
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>JSTRT</name><usage>read-write</usage><enumeratedValue><name>NotStarted</name><description>No injected channel conversion started</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Injected channel conversion has started</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>JEOC</name>
<description>Injected channel end of
conversion</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>JEOC</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>Conversion is not complete</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>Conversion complete</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EOC</name>
<description>Regular channel end of
conversion</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EOC</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>Conversion is not complete</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>Conversion complete</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AWD</name>
<description>Analog watchdog flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>AWD</name><usage>read-write</usage><enumeratedValue><name>NoEvent</name><description>No analog watchdog event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Event</name><description>Analog watchdog event occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OVRIE</name>
<description>Overrun interrupt enable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OVRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Overrun interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Overrun interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RES</name>
<description>Resolution</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>RES</name><usage>read-write</usage><enumeratedValue><name>TwelveBit</name><description>12-bit (15 ADCCLK cycles)</description><value>0</value></enumeratedValue><enumeratedValue><name>TenBit</name><description>10-bit (13 ADCCLK cycles)</description><value>1</value></enumeratedValue><enumeratedValue><name>EightBit</name><description>8-bit (11 ADCCLK cycles)</description><value>2</value></enumeratedValue><enumeratedValue><name>SixBit</name><description>6-bit (9 ADCCLK cycles)</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AWDEN</name>
<description>Analog watchdog enable on regular
channels</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>AWDEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Analog watchdog disabled on regular channels</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Analog watchdog enabled on regular channels</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>JAWDEN</name>
<description>Analog watchdog enable on injected
channels</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>JAWDEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Analog watchdog disabled on injected channels</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Analog watchdog enabled on injected channels</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DISCNUM</name>
<description>Discontinuous mode channel
count</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint>
</field>
<field>
<name>JDISCEN</name>
<description>Discontinuous mode on injected
channels</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>JDISCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Discontinuous mode on injected channels disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Discontinuous mode on injected channels enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DISCEN</name>
<description>Discontinuous mode on regular
channels</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DISCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Discontinuous mode on regular channels disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Discontinuous mode on regular channels enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>JAUTO</name>
<description>Automatic injected group
conversion</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>JAUTO</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Automatic injected group conversion disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Automatic injected group conversion enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AWDSGL</name>
<description>Enable the watchdog on a single channel
in scan mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>AWDSGL</name><usage>read-write</usage><enumeratedValue><name>AllChannels</name><description>Analog watchdog enabled on all channels</description><value>0</value></enumeratedValue><enumeratedValue><name>SingleChannel</name><description>Analog watchdog enabled on a single channel</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SCAN</name>
<description>Scan mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SCAN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Scan mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Scan mode enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>JEOCIE</name>
<description>Interrupt enable for injected
channels</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>JEOCIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>JEOC interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>JEOC interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AWDIE</name>
<description>Analog watchdog interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>AWDIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Analogue watchdog interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Analogue watchdog interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EOCIE</name>
<description>Interrupt enable for EOC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EOCIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>EOC interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>EOC interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AWDCH</name>
<description>Analog watchdog channel select
bits</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWSTART</name>
<description>Start conversion of regular
channels</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SWSTARTW</name><usage>write</usage><enumeratedValue><name>Start</name><description>Starts conversion of regular channels</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EXTEN</name>
<description>External trigger enable for regular
channels</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>EXTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger detection disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>RisingEdge</name><description>Trigger detection on the rising edge</description><value>1</value></enumeratedValue><enumeratedValue><name>FallingEdge</name><description>Trigger detection on the falling edge</description><value>2</value></enumeratedValue><enumeratedValue><name>BothEdges</name><description>Trigger detection on both the rising and falling edges</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EXTSEL</name>
<description>External event select for regular
group</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>EXTSEL</name><usage>read-write</usage><enumeratedValue><name>TIM1CC1</name><description>Timer 1 CC1 event</description><value>0</value></enumeratedValue><enumeratedValue><name>TIM1CC2</name><description>Timer 1 CC2 event</description><value>1</value></enumeratedValue><enumeratedValue><name>TIM1CC3</name><description>Timer 1 CC3 event</description><value>2</value></enumeratedValue><enumeratedValue><name>TIM2CC2</name><description>Timer 2 CC2 event</description><value>3</value></enumeratedValue><enumeratedValue><name>TIM2CC3</name><description>Timer 2 CC3 event</description><value>4</value></enumeratedValue><enumeratedValue><name>TIM2CC4</name><description>Timer 2 CC4 event</description><value>5</value></enumeratedValue><enumeratedValue><name>TIM2TRGO</name><description>Timer 2 TRGO event</description><value>6</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>JSWSTART</name>
<description>Start conversion of injected
channels</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>JSWSTARTW</name><usage>write</usage><enumeratedValue><name>Start</name><description>Starts conversion of injected channels</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>JEXTEN</name>
<description>External trigger enable for injected
channels</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>JEXTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger detection disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>RisingEdge</name><description>Trigger detection on the rising edge</description><value>1</value></enumeratedValue><enumeratedValue><name>FallingEdge</name><description>Trigger detection on the falling edge</description><value>2</value></enumeratedValue><enumeratedValue><name>BothEdges</name><description>Trigger detection on both the rising and falling edges</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>JEXTSEL</name>
<description>External event select for injected
group</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>JEXTSEL</name><usage>read-write</usage><enumeratedValue><name>TIM1TRGO</name><description>Timer 1 TRGO event</description><value>0</value></enumeratedValue><enumeratedValue><name>TIM1CC4</name><description>Timer 1 CC4 event</description><value>1</value></enumeratedValue><enumeratedValue><name>TIM2TRGO</name><description>Timer 2 TRGO event</description><value>2</value></enumeratedValue><enumeratedValue><name>TIM2CC1</name><description>Timer 2 CC1 event</description><value>3</value></enumeratedValue><enumeratedValue><name>TIM3CC4</name><description>Timer 3 CC4 event</description><value>4</value></enumeratedValue><enumeratedValue><name>TIM4TRGO</name><description>Timer 4 TRGO event</description><value>5</value></enumeratedValue><enumeratedValue><name>TIM8CC4</name><description>Timer 8 CC4 event</description><value>7</value></enumeratedValue><enumeratedValue><name>TIM1TRGO2</name><description>Timer 1 TRGO(2) event</description><value>8</value></enumeratedValue><enumeratedValue><name>TIM8TRGO</name><description>Timer 8 TRGO event</description><value>9</value></enumeratedValue><enumeratedValue><name>TIM8TRGO2</name><description>Timer 8 TRGO(2) event</description><value>10</value></enumeratedValue><enumeratedValue><name>TIM3CC3</name><description>Timer 3 CC3 event</description><value>11</value></enumeratedValue><enumeratedValue><name>TIM5TRGO</name><description>Timer 5 TRGO event</description><value>12</value></enumeratedValue><enumeratedValue><name>TIM3CC1</name><description>Timer 3 CC1 event</description><value>13</value></enumeratedValue><enumeratedValue><name>TIM6TRGO</name><description>Timer 6 TRGO event</description><value>14</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ALIGN</name>
<description>Data alignment</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ALIGN</name><usage>read-write</usage><enumeratedValue><name>Right</name><description>Right alignment</description><value>0</value></enumeratedValue><enumeratedValue><name>Left</name><description>Left alignment</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EOCS</name>
<description>End of conversion
selection</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EOCS</name><usage>read-write</usage><enumeratedValue><name>EachSequence</name><description>The EOC bit is set at the end of each sequence of regular conversions</description><value>0</value></enumeratedValue><enumeratedValue><name>EachConversion</name><description>The EOC bit is set at the end of each regular conversion</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DDS</name>
<description>DMA disable selection (for single ADC
mode)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DDS</name><usage>read-write</usage><enumeratedValue><name>Single</name><description>No new DMA request is issued after the last transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>Continuous</name><description>DMA requests are issued as long as data are converted and DMA=1</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMA</name>
<description>Direct memory access mode (for single
ADC mode)</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMA</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA mode enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CONT</name>
<description>Continuous conversion</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CONT</name><usage>read-write</usage><enumeratedValue><name>Single</name><description>Single conversion mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Continuous</name><description>Continuous conversion mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ADON</name>
<description>A/D Converter ON / OFF</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ADON</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Disable ADC conversion and go to power down mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enable ADC</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SMPR1</name>
<displayName>SMPR1</displayName>
<description>sample time register 1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMP18</name>
<description>Channel 18 sampling time selection</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="SMP10"/>
</field>
<field><name>SMP17</name><description>Channel 17 sampling time selection</description><bitOffset>21</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/>
</field>
<field><name>SMP16</name><description>Channel 16 sampling time selection</description><bitOffset>18</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/>
</field>
<field><name>SMP15</name><description>Channel 15 sampling time selection</description><bitOffset>15</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/>
</field>
<field><name>SMP14</name><description>Channel 14 sampling time selection</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/>
</field>
<field><name>SMP13</name><description>Channel 13 sampling time selection</description><bitOffset>9</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/>
</field>
<field><name>SMP12</name><description>Channel 12 sampling time selection</description><bitOffset>6</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/>
</field>
<field><name>SMP11</name><description>Channel 11 sampling time selection</description><bitOffset>3</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/>
</field>
<field><name>SMP10</name><description>Channel 10 sampling time selection</description><bitOffset>0</bitOffset><bitWidth>3</bitWidth><enumeratedValues><name>SMP10</name><usage>read-write</usage><enumeratedValue><name>Cycles3</name><description>3 cycles</description><value>0</value></enumeratedValue><enumeratedValue><name>Cycles15</name><description>15 cycles</description><value>1</value></enumeratedValue><enumeratedValue><name>Cycles28</name><description>28 cycles</description><value>2</value></enumeratedValue><enumeratedValue><name>Cycles56</name><description>56 cycles</description><value>3</value></enumeratedValue><enumeratedValue><name>Cycles84</name><description>84 cycles</description><value>4</value></enumeratedValue><enumeratedValue><name>Cycles112</name><description>112 cycles</description><value>5</value></enumeratedValue><enumeratedValue><name>Cycles144</name><description>144 cycles</description><value>6</value></enumeratedValue><enumeratedValue><name>Cycles480</name><description>480 cycles</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SMPR2</name>
<displayName>SMPR2</displayName>
<description>sample time register 2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SMP9</name>
<description>Channel 9 sampling time selection</description>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="SMP0"/>
</field>
<field><name>SMP8</name><description>Channel 8 sampling time selection</description><bitOffset>24</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/>
</field>
<field><name>SMP7</name><description>Channel 7 sampling time selection</description><bitOffset>21</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/>
</field>
<field><name>SMP6</name><description>Channel 6 sampling time selection</description><bitOffset>18</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/>
</field>
<field><name>SMP5</name><description>Channel 5 sampling time selection</description><bitOffset>15</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/>
</field>
<field><name>SMP4</name><description>Channel 4 sampling time selection</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/>
</field>
<field><name>SMP3</name><description>Channel 3 sampling time selection</description><bitOffset>9</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/>
</field>
<field><name>SMP2</name><description>Channel 2 sampling time selection</description><bitOffset>6</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/>
</field>
<field><name>SMP1</name><description>Channel 1 sampling time selection</description><bitOffset>3</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/>
</field>
<field><name>SMP0</name><description>Channel 0 sampling time selection</description><bitOffset>0</bitOffset><bitWidth>3</bitWidth><enumeratedValues><name>SMP0</name><usage>read-write</usage><enumeratedValue><name>Cycles3</name><description>3 cycles</description><value>0</value></enumeratedValue><enumeratedValue><name>Cycles15</name><description>15 cycles</description><value>1</value></enumeratedValue><enumeratedValue><name>Cycles28</name><description>28 cycles</description><value>2</value></enumeratedValue><enumeratedValue><name>Cycles56</name><description>56 cycles</description><value>3</value></enumeratedValue><enumeratedValue><name>Cycles84</name><description>84 cycles</description><value>4</value></enumeratedValue><enumeratedValue><name>Cycles112</name><description>112 cycles</description><value>5</value></enumeratedValue><enumeratedValue><name>Cycles144</name><description>144 cycles</description><value>6</value></enumeratedValue><enumeratedValue><name>Cycles480</name><description>480 cycles</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>JOFR%s</name>
<displayName>JOFR1</displayName>
<description>injected channel data offset register
x</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JOFFSET</name>
<description>Data offset for injected channel
x</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>HTR</name>
<displayName>HTR</displayName>
<description>watchdog higher threshold
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>HT</name>
<description>Analog watchdog higher
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>LTR</name>
<displayName>LTR</displayName>
<description>watchdog lower threshold
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LT</name>
<description>Analog watchdog lower
threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>SQR1</name>
<displayName>SQR1</displayName>
<description>regular sequence register 1</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>L</name>
<description>Regular channel sequence
length</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>SQ16</name>
<description>16th conversion in regular
sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ15</name>
<description>15th conversion in regular
sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ14</name>
<description>14th conversion in regular
sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ13</name>
<description>13th conversion in regular
sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>SQR2</name>
<displayName>SQR2</displayName>
<description>regular sequence register 2</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ12</name>
<description>12th conversion in regular
sequence</description>
<bitOffset>25</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ11</name>
<description>11th conversion in regular
sequence</description>
<bitOffset>20</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ10</name>
<description>10th conversion in regular
sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ9</name>
<description>9th conversion in regular
sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ8</name>
<description>8th conversion in regular
sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ7</name>
<description>7th conversion in regular
sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>SQR3</name>
<displayName>SQR3</displayName>
<description>regular sequence register 3</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SQ6</name>
<description>6th conversion in regular
sequence</description>
<bitOffset>25</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ5</name>
<description>5th conversion in regular
sequence</description>
<bitOffset>20</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ4</name>
<description>4th conversion in regular
sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ3</name>
<description>3rd conversion in regular
sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ2</name>
<description>2nd conversion in regular
sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>SQ1</name>
<description>1st conversion in regular
sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>JSQR</name>
<displayName>JSQR</displayName>
<description>injected sequence register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JL</name>
<description>Injected sequence length</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>JSQ4</name>
<description>4th conversion in injected
sequence</description>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>JSQ3</name>
<description>3rd conversion in injected
sequence</description>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>JSQ2</name>
<description>2nd conversion in injected
sequence</description>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>JSQ1</name>
<description>1st conversion in injected
sequence</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>JDR%s</name>
<displayName>JDR1</displayName>
<description>injected data register x</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>JDATA</name>
<description>Injected data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>regular data register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Regular data</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="ADC1">
<name>ADC2</name>
<baseAddress>0x40012100</baseAddress>
<interrupt>
<name>ADC</name>
<description>ADC2 global interrupts</description>
<value>18</value>
</interrupt>
<interrupt>
<name>ADC</name>
<description>ADC2 global interrupts</description>
<value>18</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="ADC1">
<name>ADC3</name>
<baseAddress>0x40012200</baseAddress>
</peripheral>
<peripheral derivedFrom="USART1">
<name>USART6</name>
<baseAddress>0x40011400</baseAddress>
<interrupt>
<name>USART6</name>
<description>USART6 global interrupt</description>
<value>71</value>
</interrupt>
<interrupt>
<name>USART6</name>
<description>USART6 global interrupt</description>
<value>71</value>
</interrupt>
</peripheral>
<peripheral>
<name>USART1</name>
<description>Universal synchronous asynchronous receiver
transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40011000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>USART1</name>
<description>USART1 global interrupt</description>
<value>37</value>
</interrupt>
<interrupt>
<name>USART1</name>
<description>USART1 global interrupt</description>
<value>37</value>
</interrupt>
<registers>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00C00000</resetValue>
<fields>
<field>
<name>CTS</name>
<description>CTS flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LBD</name>
<description>LIN break detection flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXE</name>
<description>Transmit data register
empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TC</name>
<description>Transmission complete</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXNE</name>
<description>Read data register not
empty</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IDLE</name>
<description>IDLE line detected</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ORE</name>
<description>Overrun error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NF</name>
<description>Noise detected flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FE</name>
<description>Framing error</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PE</name>
<description>Parity error</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>Data register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DR</name>
<description>Data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>511</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DIV_Mantissa</name>
<description>mantissa of USARTDIV</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
<field>
<name>DIV_Fraction</name>
<description>fraction of USARTDIV</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OVER8</name>
<description>Oversampling mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OVER8</name><usage>read-write</usage><enumeratedValue><name>Oversample16</name><description>Oversampling by 16</description><value>0</value></enumeratedValue><enumeratedValue><name>Oversample8</name><description>Oversampling by 8</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>USART prescaler and outputs disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>USART enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>M</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>M</name><usage>read-write</usage><enumeratedValue><name>M8</name><description>8 data bits</description><value>0</value></enumeratedValue><enumeratedValue><name>M9</name><description>9 data bits</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WAKE</name><usage>read-write</usage><enumeratedValue><name>IdleLine</name><description>USART wakeup on idle line</description><value>0</value></enumeratedValue><enumeratedValue><name>AddressMark</name><description>USART wakeup on address mark</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PCE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Parity control disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Parity control enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PS</name><usage>read-write</usage><enumeratedValue><name>Even</name><description>Even parity</description><value>0</value></enumeratedValue><enumeratedValue><name>Odd</name><description>Odd parity</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>PE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>PE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TXEIE</name>
<description>TXE interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TXEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TXE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TXE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TCIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TC interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TC interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RXNEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RXNE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RXNE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IDLEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>IDLE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>IDLE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Transmitter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Transmitter enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Receiver disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Receiver enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver wakeup</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RWU</name><usage>read-write</usage><enumeratedValue><name>Active</name><description>Receiver in active mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Mute</name><description>Receiver in mute mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SBK</name>
<description>Send break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SBK</name><usage>read-write</usage><enumeratedValue><name>NoBreak</name><description>No break character is transmitted</description><value>0</value></enumeratedValue><enumeratedValue><name>Break</name><description>Break character transmitted</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LINEN</name>
<description>LIN mode enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LINEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>LIN mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>LIN mode enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>STOP</name><usage>read-write</usage><enumeratedValue><name>Stop1</name><description>1 stop bit</description><value>0</value></enumeratedValue><enumeratedValue><name>Stop0p5</name><description>0.5 stop bits</description><value>1</value></enumeratedValue><enumeratedValue><name>Stop2</name><description>2 stop bits</description><value>2</value></enumeratedValue><enumeratedValue><name>Stop1p5</name><description>1.5 stop bits</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CLKEN</name>
<description>Clock enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CLKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CK pin disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CK pin enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CPOL</name>
<description>Clock polarity</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CPOL</name><usage>read-write</usage><enumeratedValue><name>Low</name><description>Steady low value on CK pin outside transmission window</description><value>0</value></enumeratedValue><enumeratedValue><name>High</name><description>Steady high value on CK pin outside transmission window</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CPHA</name>
<description>Clock phase</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CPHA</name><usage>read-write</usage><enumeratedValue><name>First</name><description>The first clock transition is the first data capture edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Second</name><description>The second clock transition is the first data capture edge</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LBCL</name>
<description>Last bit clock pulse</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LBDIE</name>
<description>LIN break detection interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LBDIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>LIN break detection interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>LIN break detection interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LBDL</name>
<description>lin break detection length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LBDL</name><usage>read-write</usage><enumeratedValue><name>LBDL10</name><description>10-bit break detection</description><value>0</value></enumeratedValue><enumeratedValue><name>LBDL11</name><description>11-bit break detection</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ADD</name>
<description>Address of the USART node</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ONEBIT</name>
<description>One sample bit method
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ONEBIT</name><usage>read-write</usage><enumeratedValue><name>Sample3</name><description>Three sample bit method</description><value>0</value></enumeratedValue><enumeratedValue><name>Sample1</name><description>One sample bit method</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CTSIE</name>
<description>CTS interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CTSIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CTS interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CTS interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CTSE</name>
<description>CTS enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CTSE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CTS hardware flow control disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CTS hardware flow control enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RTSE</name>
<description>RTS enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RTSE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RTS hardware flow control disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RTS hardware flow control enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMAT</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode is disabled for transmission</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA mode is enabled for transmission</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMAR</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode is disabled for reception</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA mode is enabled for reception</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SCEN</name>
<description>Smartcard mode enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Smartcard mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Smartcard mode enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>NACK</name>
<description>Smartcard NACK enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>NACK</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>NACK transmission in case of parity error is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>NACK transmission during parity error is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>HDSEL</name><usage>read-write</usage><enumeratedValue><name>FullDuplex</name><description>Half duplex mode is not selected</description><value>0</value></enumeratedValue><enumeratedValue><name>HalfDuplex</name><description>Half duplex mode is selected</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IRLP</name>
<description>IrDA low-power</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IRLP</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal mode</description><value>0</value></enumeratedValue><enumeratedValue><name>LowPower</name><description>Low-power mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IREN</name>
<description>IrDA mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>IrDA disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>IrDA enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Error interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Error interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>GTPR</name>
<displayName>GTPR</displayName>
<description>Guard time and prescaler
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>GT</name>
<description>Guard time value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="USART1">
<name>USART2</name>
<baseAddress>0x40004400</baseAddress>
<interrupt>
<name>USART2</name>
<description>USART2 global interrupt</description>
<value>38</value>
</interrupt>
<interrupt>
<name>USART2</name>
<description>USART2 global interrupt</description>
<value>38</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART1">
<name>USART3</name>
<baseAddress>0x40004800</baseAddress>
<interrupt>
<name>USART3</name>
<description>USART3 global interrupt</description>
<value>39</value>
</interrupt>
<interrupt>
<name>USART3</name>
<description>USART3 global interrupt</description>
<value>39</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART1">
<name>UART7</name>
<baseAddress>0x40007800</baseAddress>
<interrupt>
<name>UART7</name>
<description>UART 7 global interrupt</description>
<value>82</value>
</interrupt>
<interrupt>
<name>UART7</name>
<description>UART 7 global interrupt</description>
<value>82</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="USART1">
<name>UART8</name>
<baseAddress>0x40007C00</baseAddress>
<interrupt>
<name>UART8</name>
<description>UART 8 global interrupt</description>
<value>83</value>
</interrupt>
<interrupt>
<name>UART8</name>
<description>UART 8 global interrupt</description>
<value>83</value>
</interrupt>
</peripheral>
<peripheral>
<name>DAC</name>
<description>Digital-to-analog converter</description>
<groupName>DAC</groupName>
<baseAddress>0x40007400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM6_DAC</name>
<description>TIM6 global interrupt, DAC1 and DAC2 underrun
error interrupt</description>
<value>54</value>
</interrupt>
<interrupt>
<name>TIM6_DAC</name>
<description>TIM6 global interrupt, DAC1 and DAC2 underrun
error interrupt</description>
<value>54</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAUDRIE2</name>
<description>DAC channel2 DMA underrun interrupt
enable</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DMAUDRIE1"/>
</field>
<field>
<name>DMAEN2</name>
<description>DAC channel2 DMA enable</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DMAEN1"/>
</field>
<field>
<name>MAMP2</name>
<description>DAC channel2 mask/amplitude
selector</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>WAVE2</name>
<description>DAC channel2 noise/triangle wave
generation enable</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>WAVE2</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wave generation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Noise</name><description>Noise wave generation enabled</description><value>1</value></enumeratedValue><enumeratedValue><name>Triangle</name><description>Triangle wave generation enabled</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TSEL2</name>
<description>DAC channel2 trigger
selection</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>TSEL2</name><usage>read-write</usage><enumeratedValue><name>TIM6_TRGO</name><description>Timer 6 TRGO event</description><value>0</value></enumeratedValue><enumeratedValue><name>TIM8_TRGO</name><description>Timer 8 TRGO event</description><value>1</value></enumeratedValue><enumeratedValue><name>TIM7_TRGO</name><description>Timer 7 TRGO event</description><value>2</value></enumeratedValue><enumeratedValue><name>TIM5_TRGO</name><description>Timer 5 TRGO event</description><value>3</value></enumeratedValue><enumeratedValue><name>TIM2_TRGO</name><description>Timer 2 TRGO event</description><value>4</value></enumeratedValue><enumeratedValue><name>TIM4_TRGO</name><description>Timer 4 TRGO event</description><value>5</value></enumeratedValue><enumeratedValue><name>EXTI9</name><description>EXTI line9</description><value>6</value></enumeratedValue><enumeratedValue><name>SOFTWARE</name><description>Software trigger</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TEN2</name>
<description>DAC channel2 trigger
enable</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TEN1"/>
</field>
<field>
<name>BOFF2</name>
<description>DAC channel2 output buffer
disable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="BOFF1"/>
</field>
<field>
<name>EN2</name>
<description>DAC channel2 enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="EN1"/>
</field>
<field>
<name>DMAUDRIE1</name>
<description>DAC channel1 DMA Underrun Interrupt
enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMAUDRIE1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DAC channel X DMA Underrun Interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DAC channel X DMA Underrun Interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMAEN1</name>
<description>DAC channel1 DMA enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMAEN1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DAC channel X DMA mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DAC channel X DMA mode enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MAMP1</name>
<description>DAC channel1 mask/amplitude
selector</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>WAVE1</name>
<description>DAC channel1 noise/triangle wave
generation enable</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>WAVE1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wave generation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Noise</name><description>Noise wave generation enabled</description><value>1</value></enumeratedValue><enumeratedValue><name>Triangle</name><description>Triangle wave generation enabled</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TSEL1</name>
<description>DAC channel1 trigger
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>TSEL1</name><usage>read-write</usage><enumeratedValue><name>TIM6_TRGO</name><description>Timer 6 TRGO event</description><value>0</value></enumeratedValue><enumeratedValue><name>TIM3_TRGO</name><description>Timer 3 TRGO event</description><value>1</value></enumeratedValue><enumeratedValue><name>TIM7_TRGO</name><description>Timer 7 TRGO event</description><value>2</value></enumeratedValue><enumeratedValue><name>TIM15_TRGO</name><description>Timer 15 TRGO event</description><value>3</value></enumeratedValue><enumeratedValue><name>TIM2_TRGO</name><description>Timer 2 TRGO event</description><value>4</value></enumeratedValue><enumeratedValue><name>EXTI9</name><description>EXTI line9</description><value>6</value></enumeratedValue><enumeratedValue><name>SOFTWARE</name><description>Software trigger</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TEN1</name>
<description>DAC channel1 trigger
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TEN1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DAC channel X trigger disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DAC channel X trigger enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BOFF1</name>
<description>DAC channel1 output buffer
disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BOFF1</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>DAC channel X output buffer enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>DAC channel X output buffer disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EN1</name>
<description>DAC channel1 enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EN1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DAC channel X disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DAC channel X enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SWTRIGR</name>
<displayName>SWTRIGR</displayName>
<description>software trigger register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWTRIG2</name>
<description>DAC channel2 software
trigger</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWTRIG1"/>
</field>
<field>
<name>SWTRIG1</name>
<description>DAC channel1 software
trigger</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SWTRIG1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DAC channel X software trigger disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DAC channel X software trigger enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DHR12R1</name>
<displayName>DHR12R1</displayName>
<description>channel1 12-bit right-aligned data holding
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit right-aligned
data</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DHR12L1</name>
<displayName>DHR12L1</displayName>
<description>channel1 12-bit left aligned data holding
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit left-aligned
data</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DHR8R1</name>
<displayName>DHR8R1</displayName>
<description>channel1 8-bit right aligned data holding
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 8-bit right-aligned
data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DHR12R2</name>
<displayName>DHR12R2</displayName>
<description>channel2 12-bit right aligned data holding
register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit right-aligned
data</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DHR12L2</name>
<displayName>DHR12L2</displayName>
<description>channel2 12-bit left aligned data holding
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit left-aligned
data</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DHR8R2</name>
<displayName>DHR8R2</displayName>
<description>channel2 8-bit right-aligned data holding
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 8-bit right-aligned
data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DHR12RD</name>
<displayName>DHR12RD</displayName>
<description>Dual DAC 12-bit right-aligned data holding
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit right-aligned
data</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit right-aligned
data</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DHR12LD</name>
<displayName>DHR12LD</displayName>
<description>DUAL DAC 12-bit left aligned data holding
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 12-bit left-aligned
data</description>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 12-bit left-aligned
data</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DHR8RD</name>
<displayName>DHR8RD</displayName>
<description>DUAL DAC 8-bit right aligned data holding
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DHR</name>
<description>DAC channel2 8-bit right-aligned
data</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>DACC1DHR</name>
<description>DAC channel1 8-bit right-aligned
data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DOR1</name>
<displayName>DOR1</displayName>
<description>channel1 data output register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC1DOR</name>
<description>DAC channel1 data output</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOR2</name>
<displayName>DOR2</displayName>
<description>channel2 data output register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DACC2DOR</name>
<description>DAC channel2 data output</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMAUDR2</name>
<description>DAC channel2 DMA underrun
flag</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="DMAUDR1"/>
</field>
<field>
<name>DMAUDR1</name>
<description>DAC channel1 DMA underrun
flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMAUDR1</name><usage>read-write</usage><enumeratedValue><name>NoUnderrun</name><description>No DMA underrun error condition occurred for DAC channel X</description><value>0</value></enumeratedValue><enumeratedValue><name>Underrun</name><description>DMA underrun error condition occurred for DAC channel X</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>PWR</name>
<description>Power control</description>
<groupName>PWR</groupName>
<baseAddress>0x40007000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PVD</name>
<description>PVD through EXTI line detection
interrupt</description>
<value>1</value>
</interrupt>
<interrupt>
<name>PVD</name>
<description>PVD through EXTI line detection
interrupt</description>
<value>1</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>power control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000C000</resetValue>
<fields>
<field>
<name>LPDS</name>
<description>Low-power deep sleep</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDDS</name>
<description>Power down deepsleep</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CWUF</name>
<description>Clear wakeup flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CSBF</name>
<description>Clear standby flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVDE</name>
<description>Power voltage detector
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLS</name>
<description>PVD level selection</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBP</name>
<description>Disable backup domain write
protection</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FPDS</name>
<description>Flash power down in Stop
mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPLVDS</name>
<description>Low-Power Regulator Low Voltage in
deepsleep</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MRLVDS</name>
<description>Main regulator low voltage in deepsleep
mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VOS</name>
<description>Regulator voltage scaling output
selection</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ODEN</name>
<description>Over-drive enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ODSWEN</name>
<description>Over-drive switching
enabled</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UDEN</name>
<description>Under-drive enable in stop
mode</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>power control/status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WUF</name>
<description>Wakeup flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SBF</name>
<description>Standby flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PVDO</name>
<description>PVD output</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BRR</name>
<description>Backup regulator ready</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EWUP</name>
<description>Enable WKUP pin</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BRE</name>
<description>Backup regulator enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>VOSRDY</name>
<description>Regulator voltage scaling output
selection ready bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ODRDY</name>
<description>Over-drive mode ready</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ODSWRDY</name>
<description>Over-drive mode switching
ready</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>UDRDY</name>
<description>Under-drive ready flag</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>IWDG</name>
<description>Independent watchdog</description>
<groupName>IWDG</groupName>
<baseAddress>0x40003000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>KR</name>
<displayName>KR</displayName>
<description>Key register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>Key value (write only, read
0000h)</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<enumeratedValues><name>KEY</name><usage>read-write</usage><enumeratedValue><name>Enable</name><description>Enable access to PR, RLR and WINR registers (0x5555)</description><value>21845</value></enumeratedValue><enumeratedValue><name>Reset</name><description>Reset the watchdog value (0xAAAA)</description><value>43690</value></enumeratedValue><enumeratedValue><name>Start</name><description>Start the watchdog (0xCCCC)</description><value>52428</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PR</name>
<displayName>PR</displayName>
<description>Prescaler register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR</name>
<description>Prescaler divider</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>PR</name><usage>read-write</usage><enumeratedValue><name>DivideBy4</name><description>Divider /4</description><value>0</value></enumeratedValue><enumeratedValue><name>DivideBy8</name><description>Divider /8</description><value>1</value></enumeratedValue><enumeratedValue><name>DivideBy16</name><description>Divider /16</description><value>2</value></enumeratedValue><enumeratedValue><name>DivideBy32</name><description>Divider /32</description><value>3</value></enumeratedValue><enumeratedValue><name>DivideBy64</name><description>Divider /64</description><value>4</value></enumeratedValue><enumeratedValue><name>DivideBy128</name><description>Divider /128</description><value>5</value></enumeratedValue><enumeratedValue><name>DivideBy256</name><description>Divider /256</description><value>6</value></enumeratedValue><enumeratedValue><name>DivideBy256bis</name><description>Divider /256</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RLR</name>
<displayName>RLR</displayName>
<description>Reload register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000FFF</resetValue>
<fields>
<field>
<name>RL</name>
<description>Watchdog counter reload
value</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RVU</name>
<description>Watchdog counter reload value
update</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVU</name>
<description>Watchdog prescaler value
update</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>WWDG</name>
<description>Window watchdog</description>
<groupName>WWDG</groupName>
<baseAddress>0x40002C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WWDG</name>
<description>Window Watchdog interrupt</description>
<value>0</value>
</interrupt>
<interrupt>
<name>WWDG</name>
<description>Window Watchdog interrupt</description>
<value>0</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x7F</resetValue>
<fields>
<field>
<name>WDGA</name>
<description>Activation bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WDGA</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Watchdog disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Watchdog enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>T</name>
<description>7-bit counter (MSB to LSB)</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>127</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CFR</name>
<displayName>CFR</displayName>
<description>Configuration register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x7F</resetValue>
<fields>
<field>
<name>EWI</name>
<description>Early wakeup interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EWIW</name><usage>write</usage><enumeratedValue><name>Enable</name><description>interrupt occurs whenever the counter reaches the value 0x40</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>W</name>
<description>7-bit window value</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>127</maximum></range></writeConstraint>
</field>
<field><name>WDGTB</name><description>Timer base</description><bitOffset>7</bitOffset><bitWidth>2</bitWidth><enumeratedValues><name>WDGTB</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>Counter clock (PCLK1 div 4096) div 1</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>Counter clock (PCLK1 div 4096) div 2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>Counter clock (PCLK1 div 4096) div 4</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>Counter clock (PCLK1 div 4096) div 8</description><value>3</value></enumeratedValue></enumeratedValues>
</field></fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00</resetValue>
<fields>
<field>
<name>EWIF</name>
<description>Early wakeup interrupt
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EWIFR</name><usage>read</usage><enumeratedValue><name>Pending</name><description>The EWI Interrupt Service Routine has been triggered</description><value>1</value></enumeratedValue><enumeratedValue><name>Finished</name><description>The EWI Interrupt Service Routine has been serviced</description><value>0</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>EWIFW</name><usage>write</usage><enumeratedValue><name>Finished</name><description>The EWI Interrupt Service Routine has been serviced</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTC</name>
<description>Real-time clock</description>
<groupName>RTC</groupName>
<baseAddress>0x40002800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTC_WKUP</name>
<description>RTC Wakeup interrupt through the EXTI
line</description>
<value>3</value>
</interrupt>
<interrupt>
<name>RTC_WKUP</name>
<description>RTC Wakeup interrupt through the EXTI
line</description>
<value>3</value>
</interrupt>
<interrupt>
<name>RTC_Alarm</name>
<description>RTC Alarms (A and B) through EXTI line
interrupt</description>
<value>41</value>
</interrupt>
<interrupt>
<name>RTC_Alarm</name>
<description>RTC Alarms (A and B) through EXTI line
interrupt</description>
<value>41</value>
</interrupt>
<registers>
<register>
<name>TR</name>
<displayName>TR</displayName>
<description>time register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PM</name><usage>read-write</usage><enumeratedValue><name>AM</name><description>AM or 24-hour format</description><value>0</value></enumeratedValue><enumeratedValue><name>PM</name><description>PM</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint>
</field>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>date register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00002101</resetValue>
<fields>
<field>
<name>YT</name>
<description>Year tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>YU</name>
<description>Year units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>WDU</name>
<description>Week day units</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>7</maximum></range></writeConstraint>
</field>
<field>
<name>MT</name>
<description>Month tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>1</maximum></range></writeConstraint>
</field>
<field>
<name>MU</name>
<description>Month units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>DU</name>
<description>Date units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COE</name>
<description>Calibration output enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>COE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Calibration output disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Calibration output enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OSEL</name>
<description>Output selection</description>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>OSEL</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Output disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>AlarmA</name><description>Alarm A output enabled</description><value>1</value></enumeratedValue><enumeratedValue><name>AlarmB</name><description>Alarm B output enabled</description><value>2</value></enumeratedValue><enumeratedValue><name>Wakeup</name><description>Wakeup output enabled</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>POL</name>
<description>Output polarity</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>POL</name><usage>read-write</usage><enumeratedValue><name>High</name><description>The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])</description><value>0</value></enumeratedValue><enumeratedValue><name>Low</name><description>The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BKP</name>
<description>Backup</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BKP</name><usage>read-write</usage><enumeratedValue><name>DST_Not_Changed</name><description>Daylight Saving Time change has not been performed</description><value>0</value></enumeratedValue><enumeratedValue><name>DST_Changed</name><description>Daylight Saving Time change has been performed</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SUB1H</name>
<description>Subtract 1 hour (winter time
change)</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SUB1HW</name><usage>write</usage><enumeratedValue><name>Sub1</name><description>Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ADD1H</name>
<description>Add 1 hour (summer time
change)</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ADD1HW</name><usage>write</usage><enumeratedValue><name>Add1</name><description>Adds 1 hour to the current time. This can be used for summer time change outside initialization mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TSIE</name>
<description>Time-stamp interrupt
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TSIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Time-stamp Interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Time-stamp Interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WUTIE</name>
<description>Wakeup timer interrupt
enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WUTIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wakeup timer interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wakeup timer interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ALRBIE</name>
<description>Alarm B interrupt enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ALRBIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Alarm B Interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Alarm B Interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ALRAIE</name>
<description>Alarm A interrupt enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ALRAIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Alarm A interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Alarm A interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TSE</name>
<description>Time stamp enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TSE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Timestamp disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Timestamp enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WUTE</name>
<description>Wakeup timer enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WUTE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wakeup timer disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wakeup timer enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ALRBE</name>
<description>Alarm B enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ALRBE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Alarm B disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Alarm B enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ALRAE</name>
<description>Alarm A enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ALRAE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Alarm A disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Alarm A enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DCE</name>
<description>Coarse digital calibration
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FMT</name>
<description>Hour format</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FMT</name><usage>read-write</usage><enumeratedValue><name>Twenty_Four_Hour</name><description>24 hour/day format</description><value>0</value></enumeratedValue><enumeratedValue><name>AM_PM</name><description>AM/PM hour format</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>REFCKON</name>
<description>Reference clock detection enable (50 or
60 Hz)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>REFCKON</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RTC_REFIN detection disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RTC_REFIN detection enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TSEDGE</name>
<description>Time-stamp event active
edge</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TSEDGE</name><usage>read-write</usage><enumeratedValue><name>RisingEdge</name><description>RTC_TS input rising edge generates a time-stamp event</description><value>0</value></enumeratedValue><enumeratedValue><name>FallingEdge</name><description>RTC_TS input falling edge generates a time-stamp event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WUCKSEL</name>
<description>Wakeup clock selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>WUCKSEL</name><usage>read-write</usage><enumeratedValue><name>Div16</name><description>RTC/16 clock is selected</description><value>0</value></enumeratedValue><enumeratedValue><name>Div8</name><description>RTC/8 clock is selected</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>RTC/4 clock is selected</description><value>2</value></enumeratedValue><enumeratedValue><name>Div2</name><description>RTC/2 clock is selected</description><value>3</value></enumeratedValue><enumeratedValue><name>ClockSpare</name><description>ck_spre (usually 1 Hz) clock is selected</description><value>4</value></enumeratedValue><enumeratedValue><name>ClockSpareWithOffset</name><description>ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value</description><value>6</value></enumeratedValue></enumeratedValues>
</field>
<field><name>BYPSHAD</name><description>Bypass the shadow registers</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth><access>read-write</access><enumeratedValues><name>BYPSHAD</name><usage>read-write</usage><enumeratedValue><name>ShadowReg</name><description>Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles</description><value>0</value></enumeratedValue><enumeratedValue><name>BypassShadowReg</name><description>Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field><name>COSEL</name><description>Calibration output selection</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth><access>read-write</access><enumeratedValues><name>COSEL</name><usage>read-write</usage><enumeratedValue><name>CalFreq_512Hz</name><description>Calibration output is 512 Hz (with default prescaler setting)</description><value>0</value></enumeratedValue><enumeratedValue><name>CalFreq_1Hz</name><description>Calibration output is 1 Hz (with default prescaler setting)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>initialization and status
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>ALRAWF</name>
<description>Alarm A write flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>ALRAWFR</name><usage>read</usage><enumeratedValue><name>UpdateNotAllowed</name><description>Alarm update not allowed</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdateAllowed</name><description>Alarm update allowed</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ALRBWF</name>
<description>Alarm B write flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues derivedFrom="ALRAWFR"/>
</field>
<field>
<name>WUTWF</name>
<description>Wakeup timer write flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>WUTWFR</name><usage>read</usage><enumeratedValue><name>UpdateNotAllowed</name><description>Wakeup timer configuration update not allowed</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdateAllowed</name><description>Wakeup timer configuration update allowed</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SHPF</name>
<description>Shift operation pending</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>SHPFR</name><usage>read</usage><enumeratedValue><name>NoShiftPending</name><description>No shift operation is pending</description><value>0</value></enumeratedValue><enumeratedValue><name>ShiftPending</name><description>A shift operation is pending</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>INITS</name>
<description>Initialization status flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>INITSR</name><usage>read</usage><enumeratedValue><name>NotInitalized</name><description>Calendar has not been initialized</description><value>0</value></enumeratedValue><enumeratedValue><name>Initalized</name><description>Calendar has been initialized</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RSF</name>
<description>Registers synchronization
flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>RSFR</name><usage>read</usage><enumeratedValue><name>NotSynced</name><description>Calendar shadow registers not yet synchronized</description><value>0</value></enumeratedValue><enumeratedValue><name>Synced</name><description>Calendar shadow registers synchronized</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>RSFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>INITF</name>
<description>Initialization flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>INITFR</name><usage>read</usage><enumeratedValue><name>NotAllowed</name><description>Calendar registers update is not allowed</description><value>0</value></enumeratedValue><enumeratedValue><name>Allowed</name><description>Calendar registers update is allowed</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>INIT</name>
<description>Initialization mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>INIT</name><usage>read-write</usage><enumeratedValue><name>FreeRunningMode</name><description>Free running mode</description><value>0</value></enumeratedValue><enumeratedValue><name>InitMode</name><description>Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ALRAF</name>
<description>Alarm A flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>ALRAFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>ALRAFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ALRBF</name>
<description>Alarm B flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>ALRBFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>ALRBFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WUTF</name>
<description>Wakeup timer flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>WUTFR</name><usage>read</usage><enumeratedValue><name>Zero</name><description>This flag is set by hardware when the wakeup auto-reload counter reaches 0</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>WUTFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TSF</name>
<description>Time-stamp flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>TSFR</name><usage>read</usage><enumeratedValue><name>TimestampEvent</name><description>This flag is set by hardware when a time-stamp event occurs</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>TSFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TSOVF</name>
<description>Time-stamp overflow flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>TSOVFR</name><usage>read</usage><enumeratedValue><name>Overflow</name><description>This flag is set by hardware when a time-stamp event occurs while TSF is already set</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>TSOVFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TAMP1F</name>
<description>Tamper detection flag</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>TAMP1FR</name><usage>read</usage><enumeratedValue><name>Tampered</name><description>This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>TAMP1FW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Flag cleared by software writing 0</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TAMP2F</name>
<description>TAMPER2 detection flag</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues derivedFrom="TAMP1FR"/>
<enumeratedValues derivedFrom="TAMP1FW"/>
</field>
<field>
<name>RECALPF</name>
<description>Recalibration pending Flag</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>RECALPFR</name><usage>read</usage><enumeratedValue><name>Pending</name><description>The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PRER</name>
<displayName>PRER</displayName>
<description>prescaler register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x007F00FF</resetValue>
<fields>
<field>
<name>PREDIV_A</name>
<description>Asynchronous prescaler
factor</description>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>127</maximum></range></writeConstraint>
</field>
<field>
<name>PREDIV_S</name>
<description>Synchronous prescaler
factor</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>32767</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>WUTR</name>
<displayName>WUTR</displayName>
<description>wakeup timer register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>WUT</name>
<description>Wakeup auto-reload value
bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CALIBR</name>
<displayName>CALIBR</displayName>
<description>calibration register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DCS</name>
<description>Digital calibration sign</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DC</name>
<description>Digital calibration</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALRMAR</name>
<displayName>ALRMAR</displayName>
<description>alarm A register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MSK4</name>
<description>Alarm A date mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MSK1"/>
</field>
<field>
<name>WDSEL</name>
<description>Week day selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WDSEL</name><usage>read-write</usage><enumeratedValue><name>DateUnits</name><description>DU[3:0] represents the date units</description><value>0</value></enumeratedValue><enumeratedValue><name>WeekDay</name><description>DU[3:0] represents the week day. DT[1:0] is don&#8217;t care.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>DU</name>
<description>Date units or day in BCD
format</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>MSK3</name>
<description>Alarm A hours mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MSK1"/>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PM</name><usage>read-write</usage><enumeratedValue><name>AM</name><description>AM or 24-hour format</description><value>0</value></enumeratedValue><enumeratedValue><name>PM</name><description>PM</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>MSK2</name>
<description>Alarm A minutes mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MSK1"/>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>MSK1</name>
<description>Alarm A seconds mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MSK1</name><usage>read-write</usage><enumeratedValue><name>Mask</name><description>Alarm set if the date/day match</description><value>0</value></enumeratedValue><enumeratedValue><name>NotMask</name><description>Date/day don&#8217;t care in Alarm comparison</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint>
</field>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ALRMBR</name>
<displayName>ALRMBR</displayName>
<description>alarm B register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MSK4</name>
<description>Alarm B date mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MSK1"/>
</field>
<field>
<name>WDSEL</name>
<description>Week day selection</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WDSEL</name><usage>read-write</usage><enumeratedValue><name>DateUnits</name><description>DU[3:0] represents the date units</description><value>0</value></enumeratedValue><enumeratedValue><name>WeekDay</name><description>DU[3:0] represents the week day. DT[1:0] is don&#8217;t care.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>DU</name>
<description>Date units or day in BCD
format</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>MSK3</name>
<description>Alarm B hours mask</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MSK1"/>
</field>
<field>
<name>PM</name>
<description>AM/PM notation</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PM</name><usage>read-write</usage><enumeratedValue><name>AM</name><description>AM or 24-hour format</description><value>0</value></enumeratedValue><enumeratedValue><name>PM</name><description>PM</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HT</name>
<description>Hour tens in BCD format</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>HU</name>
<description>Hour units in BCD format</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>MSK2</name>
<description>Alarm B minutes mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MSK1"/>
</field>
<field>
<name>MNT</name>
<description>Minute tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint>
</field>
<field>
<name>MNU</name>
<description>Minute units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>MSK1</name>
<description>Alarm B seconds mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MSK1</name><usage>read-write</usage><enumeratedValue><name>Mask</name><description>Alarm set if the date/day match</description><value>0</value></enumeratedValue><enumeratedValue><name>NotMask</name><description>Date/day don&#8217;t care in Alarm comparison</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ST</name>
<description>Second tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint>
</field>
<field>
<name>SU</name>
<description>Second units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>WPR</name>
<displayName>WPR</displayName>
<description>write protection register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>Write protection key</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>SSR</name>
<displayName>SSR</displayName>
<description>sub second register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SS</name>
<description>Sub second value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>SHIFTR</name>
<displayName>SHIFTR</displayName>
<description>shift control register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADD1S</name>
<description>Add one second</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ADD1SW</name><usage>write</usage><enumeratedValue><name>Add1</name><description>Add one second to the clock/calendar</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SUBFS</name>
<description>Subtract a fraction of a
second</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>32767</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>TSTR</name>
<displayName>TSTR</displayName>
<description>time stamp time register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALARMOUTTYPE</name>
<description>AFO_ALARM output type</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSINSEL</name>
<description>TIMESTAMP mapping</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1INSEL</name>
<description>TAMPER1 mapping</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMPIE</name>
<description>Tamper interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1TRG</name>
<description>Active level for tamper 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1E</name>
<description>Tamper 1 detection enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSDR</name>
<displayName>TSDR</displayName>
<description>time stamp date register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDU</name>
<description>Week day units</description>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MT</name>
<description>Month tens in BCD format</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MU</name>
<description>Month units in BCD format</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DT</name>
<description>Date tens in BCD format</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DU</name>
<description>Date units in BCD format</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>TSSSR</name>
<displayName>TSSSR</displayName>
<description>timestamp sub second register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SS</name>
<description>Sub second value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALR</name>
<displayName>CALR</displayName>
<description>calibration register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALP</name>
<description>Increase frequency of RTC by 488.5
ppm</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CALP</name><usage>read-write</usage><enumeratedValue><name>NoChange</name><description>No RTCCLK pulses are added</description><value>0</value></enumeratedValue><enumeratedValue><name>IncreaseFreq</name><description>One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CALW8</name>
<description>Use an 8-second calibration cycle
period</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CALW8</name><usage>read-write</usage><enumeratedValue><name>Eight_Second</name><description>When CALW8 is set to &#8216;1&#8217;, the 8-second calibration cycle period is selected</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CALW16</name>
<description>Use a 16-second calibration cycle
period</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CALW16</name><usage>read-write</usage><enumeratedValue><name>Sixteen_Second</name><description>When CALW16 is set to &#8216;1&#8217;, the 16-second calibration cycle period is selected.This bit must not be set to &#8216;1&#8217; if CALW8=1</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CALM</name>
<description>Calibration minus</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>511</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>TAFCR</name>
<displayName>TAFCR</displayName>
<description>tamper and alternate function configuration
register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALARMOUTTYPE</name>
<description>AFO_ALARM output type</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSINSEL</name>
<description>TIMESTAMP mapping</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1INSEL</name>
<description>TAMPER1 mapping</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMPPUDIS</name>
<description>TAMPER pull-up disable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMPPRCH</name>
<description>Tamper precharge duration</description>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TAMPFLT</name>
<description>Tamper filter count</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TAMPFREQ</name>
<description>Tamper sampling frequency</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TAMPTS</name>
<description>Activate timestamp on tamper detection
event</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2TRG</name>
<description>Active level for tamper 2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP2E</name>
<description>Tamper 2 detection enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMPIE</name>
<description>Tamper interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1TRG</name>
<description>Active level for tamper 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAMP1E</name>
<description>Tamper 1 detection enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ALRMASSR</name>
<displayName>ALRMASSR</displayName>
<description>alarm A sub second register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MASKSS</name>
<description>Mask the most-significant bits starting
at this bit</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>SS</name>
<description>Sub seconds value</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>32767</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ALRMBSSR</name>
<displayName>ALRMBSSR</displayName>
<description>alarm B sub second register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MASKSS</name>
<description>Mask the most-significant bits starting
at this bit</description>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>SS</name>
<description>Sub seconds value</description>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>32767</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<dim>20</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19</dimIndex><name>BKP%sR</name>
<displayName>BKP0R</displayName>
<description>backup register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BKP</name>
<description>BKP</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>UART4</name>
<description>Universal synchronous asynchronous receiver
transmitter</description>
<groupName>USART</groupName>
<baseAddress>0x40004C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UART4</name>
<description>UART4 global interrupt</description>
<value>52</value>
</interrupt>
<interrupt>
<name>UART4</name>
<description>UART4 global interrupt</description>
<value>52</value>
</interrupt>
<registers>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00C00000</resetValue>
<fields>
<field>
<name>LBD</name>
<description>LIN break detection flag</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXE</name>
<description>Transmit data register
empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TC</name>
<description>Transmission complete</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXNE</name>
<description>Read data register not
empty</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IDLE</name>
<description>IDLE line detected</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ORE</name>
<description>Overrun error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NF</name>
<description>Noise detected flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FE</name>
<description>Framing error</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PE</name>
<description>Parity error</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>Data register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DR</name>
<description>Data value</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>511</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>BRR</name>
<displayName>BRR</displayName>
<description>Baud rate register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DIV_Mantissa</name>
<description>mantissa of USARTDIV</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
<field>
<name>DIV_Fraction</name>
<description>fraction of USARTDIV</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OVER8</name>
<description>Oversampling mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OVER8</name><usage>read-write</usage><enumeratedValue><name>Oversample16</name><description>Oversampling by 16</description><value>0</value></enumeratedValue><enumeratedValue><name>Oversample8</name><description>Oversampling by 8</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UE</name>
<description>USART enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>USART prescaler and outputs disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>USART enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>M</name>
<description>Word length</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>M</name><usage>read-write</usage><enumeratedValue><name>M8</name><description>8 data bits</description><value>0</value></enumeratedValue><enumeratedValue><name>M9</name><description>9 data bits</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WAKE</name>
<description>Wakeup method</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WAKE</name><usage>read-write</usage><enumeratedValue><name>IdleLine</name><description>USART wakeup on idle line</description><value>0</value></enumeratedValue><enumeratedValue><name>AddressMark</name><description>USART wakeup on address mark</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PCE</name>
<description>Parity control enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PCE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Parity control disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Parity control enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PS</name>
<description>Parity selection</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PS</name><usage>read-write</usage><enumeratedValue><name>Even</name><description>Even parity</description><value>0</value></enumeratedValue><enumeratedValue><name>Odd</name><description>Odd parity</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PEIE</name>
<description>PE interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>PE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>PE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TXEIE</name>
<description>TXE interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TXEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TXE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TXE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TCIE</name>
<description>Transmission complete interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TCIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TC interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TC interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RXNEIE</name>
<description>RXNE interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RXNEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RXNE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RXNE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IDLEIE</name>
<description>IDLE interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IDLEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>IDLE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>IDLE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Transmitter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Transmitter enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Receiver disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Receiver enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RWU</name>
<description>Receiver wakeup</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RWU</name><usage>read-write</usage><enumeratedValue><name>Active</name><description>Receiver in active mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Mute</name><description>Receiver in mute mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SBK</name>
<description>Send break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SBK</name><usage>read-write</usage><enumeratedValue><name>NoBreak</name><description>No break character is transmitted</description><value>0</value></enumeratedValue><enumeratedValue><name>Break</name><description>Break character transmitted</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LINEN</name>
<description>LIN mode enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LINEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>LIN mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>LIN mode enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>STOP</name>
<description>STOP bits</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>STOP</name><usage>read-write</usage><enumeratedValue><name>Stop1</name><description>1 stop bit</description><value>0</value></enumeratedValue><enumeratedValue><name>Stop2</name><description>2 stop bits</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LBDIE</name>
<description>LIN break detection interrupt
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LBDIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>LIN break detection interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>LIN break detection interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LBDL</name>
<description>lin break detection length</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LBDL</name><usage>read-write</usage><enumeratedValue><name>LBDL10</name><description>10-bit break detection</description><value>0</value></enumeratedValue><enumeratedValue><name>LBDL11</name><description>11-bit break detection</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ADD</name>
<description>Address of the USART node</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CR3</name>
<displayName>CR3</displayName>
<description>Control register 3</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ONEBIT</name>
<description>One sample bit method
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ONEBIT</name><usage>read-write</usage><enumeratedValue><name>Sample3</name><description>Three sample bit method</description><value>0</value></enumeratedValue><enumeratedValue><name>Sample1</name><description>One sample bit method</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMAT</name>
<description>DMA enable transmitter</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMAT</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode is disabled for transmission</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA mode is enabled for transmission</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMAR</name>
<description>DMA enable receiver</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMAR</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode is disabled for reception</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA mode is enabled for reception</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HDSEL</name>
<description>Half-duplex selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>HDSEL</name><usage>read-write</usage><enumeratedValue><name>FullDuplex</name><description>Half duplex mode is not selected</description><value>0</value></enumeratedValue><enumeratedValue><name>HalfDuplex</name><description>Half duplex mode is selected</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IRLP</name>
<description>IrDA low-power</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IRLP</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal mode</description><value>0</value></enumeratedValue><enumeratedValue><name>LowPower</name><description>Low-power mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IREN</name>
<description>IrDA mode enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>IrDA disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>IrDA enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EIE</name>
<description>Error interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Error interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Error interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="UART4">
<name>UART5</name>
<baseAddress>0x40005000</baseAddress>
<interrupt>
<name>UART5</name>
<description>UART5 global interrupt</description>
<value>53</value>
</interrupt>
<interrupt>
<name>UART5</name>
<description>UART5 global interrupt</description>
<value>53</value>
</interrupt>
</peripheral>
<peripheral>
<name>ADC_Common</name>
<description>Common ADC registers</description>
<groupName>ADC</groupName>
<baseAddress>0x40012300</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xD</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>ADC Common status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OVR3</name>
<description>Overrun flag of ADC3</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OVR1"/>
</field>
<field>
<name>STRT3</name>
<description>Regular channel Start flag of ADC
3</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="STRT1"/>
</field>
<field>
<name>JSTRT3</name>
<description>Injected channel Start flag of ADC
3</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="JSTRT1"/>
</field>
<field>
<name>JEOC3</name>
<description>Injected channel end of conversion of
ADC 3</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="JEOC1"/>
</field>
<field>
<name>EOC3</name>
<description>End of conversion of ADC 3</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="EOC1"/>
</field>
<field>
<name>AWD3</name>
<description>Analog watchdog flag of ADC
3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="AWD1"/>
</field>
<field>
<name>OVR2</name>
<description>Overrun flag of ADC 2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="OVR1"/>
</field>
<field>
<name>STRT2</name>
<description>Regular channel Start flag of ADC
2</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="STRT1"/>
</field>
<field>
<name>JSTRT2</name>
<description>Injected channel Start flag of ADC
2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="JSTRT1"/>
</field>
<field>
<name>JEOC2</name>
<description>Injected channel end of conversion of
ADC 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="JEOC1"/>
</field>
<field>
<name>EOC2</name>
<description>End of conversion of ADC 2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="EOC1"/>
</field>
<field>
<name>AWD2</name>
<description>Analog watchdog flag of ADC
2</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="AWD1"/>
</field>
<field>
<name>OVR1</name>
<description>Overrun flag of ADC 1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OVR1</name><usage>read-write</usage><enumeratedValue><name>NoOverrun</name><description>No overrun occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Overrun occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>STRT1</name>
<description>Regular channel Start flag of ADC
1</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>STRT1</name><usage>read-write</usage><enumeratedValue><name>NotStarted</name><description>No regular channel conversion started</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Regular channel conversion has started</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>JSTRT1</name>
<description>Injected channel Start flag of ADC
1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>JSTRT1</name><usage>read-write</usage><enumeratedValue><name>NotStarted</name><description>No injected channel conversion started</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Injected channel conversion has started</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>JEOC1</name>
<description>Injected channel end of conversion of
ADC 1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>JEOC1</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>Conversion is not complete</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>Conversion complete</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EOC1</name>
<description>End of conversion of ADC 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EOC1</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>Conversion is not complete</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>Conversion complete</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AWD1</name>
<description>Analog watchdog flag of ADC
1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>AWD1</name><usage>read-write</usage><enumeratedValue><name>NoEvent</name><description>No analog watchdog event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Event</name><description>Analog watchdog event occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>ADC common control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSVREFE</name>
<description>Temperature sensor and VREFINT
enable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TSVREFE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Temperature sensor and V_REFINT channel disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Temperature sensor and V_REFINT channel enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>VBATE</name>
<description>VBAT enable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>VBATE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>V_BAT channel disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>V_BAT channel enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ADCPRE</name>
<description>ADC prescaler</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>ADCPRE</name><usage>read-write</usage><enumeratedValue><name>Div2</name><description>PCLK2 divided by 2</description><value>0</value></enumeratedValue><enumeratedValue><name>Div4</name><description>PCLK2 divided by 4</description><value>1</value></enumeratedValue><enumeratedValue><name>Div6</name><description>PCLK2 divided by 6</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>PCLK2 divided by 8</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMA</name>
<description>Direct memory access mode for multi ADC
mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>DMA</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Mode1</name><description>DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)</description><value>1</value></enumeratedValue><enumeratedValue><name>Mode2</name><description>DMA mode 2 enabled (2 / 3 half-words by pairs - 2&amp;1 then 1&amp;3 then 3&amp;2)</description><value>2</value></enumeratedValue><enumeratedValue><name>Mode3</name><description>DMA mode 3 enabled (2 / 3 half-words by pairs - 2&amp;1 then 1&amp;3 then 3&amp;2)</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DDS</name>
<description>DMA disable selection for multi-ADC
mode</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DDS</name><usage>read-write</usage><enumeratedValue><name>Single</name><description>No new DMA request is issued after the last transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>Continuous</name><description>DMA requests are issued as long as data are converted and DMA=01, 10 or 11</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DELAY</name>
<description>Delay between 2 sampling
phases</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>MULTI</name>
<description>Multi ADC mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<enumeratedValues><name>MULTI</name><usage>read-write</usage><enumeratedValue><name>Independent</name><description>All the ADCs independent: independent mode</description><value>0</value></enumeratedValue><enumeratedValue><name>DualRJ</name><description>Dual ADC1 and ADC2, combined regular and injected simultaneous mode</description><value>1</value></enumeratedValue><enumeratedValue><name>DualRA</name><description>Dual ADC1 and ADC2, combined regular and alternate trigger mode</description><value>2</value></enumeratedValue><enumeratedValue><name>DualJ</name><description>Dual ADC1 and ADC2, injected simultaneous mode only</description><value>5</value></enumeratedValue><enumeratedValue><name>DualR</name><description>Dual ADC1 and ADC2, regular simultaneous mode only</description><value>6</value></enumeratedValue><enumeratedValue><name>DualI</name><description>Dual ADC1 and ADC2, interleaved mode only</description><value>7</value></enumeratedValue><enumeratedValue><name>DualA</name><description>Dual ADC1 and ADC2, alternate trigger mode only</description><value>9</value></enumeratedValue><enumeratedValue><name>TripleRJ</name><description>Triple ADC, regular and injected simultaneous mode</description><value>17</value></enumeratedValue><enumeratedValue><name>TripleRA</name><description>Triple ADC, regular and alternate trigger mode</description><value>18</value></enumeratedValue><enumeratedValue><name>TripleJ</name><description>Triple ADC, injected simultaneous mode only</description><value>21</value></enumeratedValue><enumeratedValue><name>TripleR</name><description>Triple ADC, regular simultaneous mode only</description><value>22</value></enumeratedValue><enumeratedValue><name>TripleI</name><description>Triple ADC, interleaved mode only</description><value>23</value></enumeratedValue><enumeratedValue><name>TripleA</name><description>Triple ADC, alternate trigger mode only</description><value>24</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CDR</name>
<displayName>CDR</displayName>
<description>ADC common regular data register for dual
and triple modes</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA2</name>
<description>2nd data item of a pair of regular
conversions</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DATA1</name>
<description>1st data item of a pair of regular
conversions</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM1</name>
<description>Advanced-timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40010000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM1_BRK_TIM9</name>
<description>TIM1 Break interrupt and TIM9 global
interrupt</description>
<value>24</value>
</interrupt>
<interrupt>
<name>TIM1_BRK_TIM9</name>
<description>TIM1 Break interrupt and TIM9 global
interrupt</description>
<value>24</value>
</interrupt>
<interrupt>
<name>TIM1_UP_TIM10</name>
<description>TIM1 Update interrupt and TIM10 global
interrupt</description>
<value>25</value>
</interrupt>
<interrupt>
<name>TIM1_UP_TIM10</name>
<description>TIM1 Update interrupt and TIM10 global
interrupt</description>
<value>25</value>
</interrupt>
<interrupt>
<name>TIM1_TRG_COM_TIM11</name>
<description>TIM1 Trigger and Commutation interrupts and
TIM11 global interrupt</description>
<value>26</value>
</interrupt>
<interrupt>
<name>TIM1_TRG_COM_TIM11</name>
<description>TIM1 Trigger and Commutation interrupts and
TIM11 global interrupt</description>
<value>26</value>
</interrupt>
<interrupt>
<name>TIM1_CC</name>
<description>TIM1 Capture Compare interrupt</description>
<value>27</value>
</interrupt>
<interrupt>
<name>TIM1_CC</name>
<description>TIM1 Capture Compare interrupt</description>
<value>27</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 &#215; t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 &#215; t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CMS</name>
<description>Center-aligned mode
selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CMS</name><usage>read-write</usage><enumeratedValue><name>EdgeAligned</name><description>The counter counts up or down depending on the direction bit</description><value>0</value></enumeratedValue><enumeratedValue><name>CenterAligned1</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.</description><value>1</value></enumeratedValue><enumeratedValue><name>CenterAligned2</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.</description><value>2</value></enumeratedValue><enumeratedValue><name>CenterAligned3</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DIR</name><usage>read-write</usage><enumeratedValue><name>Up</name><description>Counter used as upcounter</description><value>0</value></enumeratedValue><enumeratedValue><name>Down</name><description>Counter used as downcounter</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>OIS4</name>
<description>Output Idle state 4</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3N</name>
<description>Output Idle state 3</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS3</name>
<description>Output Idle state 3</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2N</name>
<description>Output Idle state 2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS2</name>
<description>Output Idle state 2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1N</name>
<description>Output Idle state 1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OIS1</name>
<description>Output Idle state 1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TI1S</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>The TIMx_CH1 pin is connected to TI1 input</description><value>0</value></enumeratedValue><enumeratedValue><name>XOR</name><description>The TIMx_CH1, CH2, CH3 pins are connected to TI1 input</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>MMS</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>The UG bit from the TIMx_EGR register is used as trigger output</description><value>0</value></enumeratedValue><enumeratedValue><name>Enable</name><description>The counter enable signal, CNT_EN, is used as trigger output</description><value>1</value></enumeratedValue><enumeratedValue><name>Update</name><description>The update event is selected as trigger output</description><value>2</value></enumeratedValue><enumeratedValue><name>ComparePulse</name><description>The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred</description><value>3</value></enumeratedValue><enumeratedValue><name>CompareOC1</name><description>OC1REF signal is used as trigger output</description><value>4</value></enumeratedValue><enumeratedValue><name>CompareOC2</name><description>OC2REF signal is used as trigger output</description><value>5</value></enumeratedValue><enumeratedValue><name>CompareOC3</name><description>OC3REF signal is used as trigger output</description><value>6</value></enumeratedValue><enumeratedValue><name>CompareOC4</name><description>OC4REF signal is used as trigger output</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CCDS</name><usage>read-write</usage><enumeratedValue><name>OnCompare</name><description>CCx DMA request sent when CCx event occurs</description><value>0</value></enumeratedValue><enumeratedValue><name>OnUpdate</name><description>CCx DMA request sent when update event occurs</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CCUS</name>
<description>Capture/compare control update
selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCPC</name>
<description>Capture/compare preloaded
control</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ETP</name>
<description>External trigger polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ETP</name><usage>read-write</usage><enumeratedValue><name>NotInverted</name><description>ETR is noninverted, active at high level or rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Inverted</name><description>ETR is inverted, active at low level or falling edge</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ECE</name>
<description>External clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ECE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>External clock mode 2 disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ETPS</name>
<description>External trigger prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>ETPS</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>Prescaler OFF</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>ETRP frequency divided by 2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>ETRP frequency divided by 4</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>ETRP frequency divided by 8</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ETF</name>
<description>External trigger filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>ETF</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MSM</name><usage>read-write</usage><enumeratedValue><name>NoSync</name><description>No action</description><value>0</value></enumeratedValue><enumeratedValue><name>Sync</name><description>The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>TS</name><usage>read-write</usage><enumeratedValue><name>ITR0</name><description>Internal Trigger 0 (ITR0)</description><value>0</value></enumeratedValue><enumeratedValue><name>ITR1</name><description>Internal Trigger 1 (ITR1)</description><value>1</value></enumeratedValue><enumeratedValue><name>ITR2</name><description>Internal Trigger 2 (ITR2)</description><value>2</value></enumeratedValue><enumeratedValue><name>TI1F_ED</name><description>TI1 Edge Detector (TI1F_ED)</description><value>4</value></enumeratedValue><enumeratedValue><name>TI1FP1</name><description>Filtered Timer Input 1 (TI1FP1)</description><value>5</value></enumeratedValue><enumeratedValue><name>TI2FP2</name><description>Filtered Timer Input 2 (TI2FP2)</description><value>6</value></enumeratedValue><enumeratedValue><name>ETRF</name><description>External Trigger input (ETRF)</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>SMS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Slave mode disabled - if CEN = &#8216;1 then the prescaler is clocked directly by the internal clock.</description><value>0</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_1</name><description>Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.</description><value>1</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_2</name><description>Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.</description><value>2</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_3</name><description>Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.</description><value>3</value></enumeratedValue><enumeratedValue><name>Reset_Mode</name><description>Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.</description><value>4</value></enumeratedValue><enumeratedValue><name>Gated_Mode</name><description>Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.</description><value>5</value></enumeratedValue><enumeratedValue><name>Trigger_Mode</name><description>Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.</description><value>6</value></enumeratedValue><enumeratedValue><name>Ext_Clock_Mode</name><description>External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>COMDE</name>
<description>COM DMA request enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4DE</name>
<description>Capture/Compare 4 DMA request
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC3DE</name>
<description>Capture/Compare 3 DMA request
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1DE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4IE</name>
<description>Capture/Compare 4 interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC3IE</name>
<description>Capture/Compare 3 interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1IE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BIE</name>
<description>Break interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMIE</name>
<description>COM interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC4OF</name>
<description>Capture/Compare 4 overcapture
flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC3OF</name>
<description>Capture/Compare 3 overcapture
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture
flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1OFR</name><usage>read</usage><enumeratedValue><name>Overcapture</name><description>The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>CC1OFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BIF</name>
<description>Break interrupt flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIFR</name><usage>read</usage><enumeratedValue><name>NoTrigger</name><description>No trigger event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Trigger</name><description>Trigger interrupt pending</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>TIFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>COMIF</name>
<description>COM interrupt flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4IF</name>
<description>Capture/Compare 4 interrupt
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC3IF</name>
<description>Capture/Compare 3 interrupt
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1IFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>CC1IFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>BG</name>
<description>Break generation</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TGW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>COMG</name>
<description>Capture/Compare control update
generation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4G</name>
<description>Capture/compare 4
generation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC3G</name>
<description>Capture/compare 3
generation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2
generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1GW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC2CE</name>
<description>Output Compare 2 clear
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>Output Compare 2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="OC1M"/>
</field>
<field>
<name>OC2PE</name>
<description>Output Compare 2 preload
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC2PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR2 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC2FE</name>
<description>Output Compare 2 fast
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC2 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1CE</name>
<description>Output Compare 1 clear
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT&lt;TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT&gt;TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC1PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR1 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC1 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC2PSC</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>TI2</name><description>CC2 channel is configured as input, IC2 is mapped on TI2</description><value>1</value></enumeratedValue><enumeratedValue><name>TI1</name><description>CC2 channel is configured as input, IC2 is mapped on TI1</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC2 channel is configured as input, IC2 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>IC1F</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>TI1</name><description>CC1 channel is configured as input, IC1 is mapped on TI1</description><value>1</value></enumeratedValue><enumeratedValue><name>TI2</name><description>CC1 channel is configured as input, IC1 is mapped on TI2</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC1 channel is configured as input, IC1 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR2_Output</name>
<displayName>CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output
mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC4CE</name>
<description>Output compare 4 clear
enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M</name>
<description>Output compare 4 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="OC3M"/>
</field>
<field>
<name>OC4PE</name>
<description>Output compare 4 preload
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC4PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR4 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC4FE</name>
<description>Output compare 4 fast
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC4 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3CE</name>
<description>Output compare 3 clear
enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>Output compare 3 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>OC3M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT&lt;TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT&gt;TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3PE</name>
<description>Output compare 3 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC3PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR3 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3FE</name>
<description>Output compare 3 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>Capture/Compare 3
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC3 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR2_Input</name>
<displayName>CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input
mode)</description>
<alternateRegister>CCMR2_Output</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC4F</name>
<description>Input capture 4 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC4PSC</name>
<description>Input capture 4 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>TI4</name><description>CC4 channel is configured as input, IC4 is mapped on TI4</description><value>1</value></enumeratedValue><enumeratedValue><name>TI3</name><description>CC4 channel is configured as input, IC4 is mapped on TI3</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC4 channel is configured as input, IC4 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC3F</name>
<description>Input capture 3 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC3PSC</name>
<description>Input capture 3 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>CC3S</name>
<description>Capture/compare 3
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>TI3</name><description>CC3 channel is configured as input, IC3 is mapped on TI3</description><value>1</value></enumeratedValue><enumeratedValue><name>TI4</name><description>CC3 channel is configured as input, IC3 is mapped on TI4</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC3 channel is configured as input, IC3 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC4P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>Capture/Compare 4 output
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NP</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NE</name>
<description>Capture/Compare 3 complementary output
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>Capture/Compare 3 output
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NE</name>
<description>Capture/Compare 2 complementary output
enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NE</name>
<description>Capture/Compare 1 complementary output
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>CCR%s</name>
<displayName>CCR1</displayName>
<description>capture/compare register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst
accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>RCR</name>
<displayName>RCR</displayName>
<description>repetition counter register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>REP</name>
<description>Repetition counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BDTR</name>
<displayName>BDTR</displayName>
<description>break and dead-time register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>MOE</name>
<description>Main output enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MOE</name><usage>read-write</usage><enumeratedValue><name>DisabledIdle</name><description>OC/OCN are disabled or forced idle depending on OSSI</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>OC/OCN are enabled if CCxE/CCxNE are set</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AOE</name>
<description>Automatic output enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKP</name>
<description>Break polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BKE</name>
<description>Break enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OSSR</name>
<description>Off-state selection for Run
mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OSSR</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>When inactive, OC/OCN outputs are disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>IdleLevel</name><description>When inactive, OC/OCN outputs are enabled with their inactive level</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OSSI</name>
<description>Off-state selection for Idle
mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OSSI</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>When inactive, OC/OCN outputs are disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>IdleLevel</name><description>When inactive, OC/OCN outputs are forced to idle level</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LOCK</name>
<description>Lock configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DTG</name>
<description>Dead-time generator setup</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM1">
<name>TIM8</name>
<baseAddress>0x40010400</baseAddress>
<interrupt>
<name>TIM8_BRK_TIM12</name>
<description>TIM8 Break interrupt and TIM12 global
interrupt</description>
<value>43</value>
</interrupt>
<interrupt>
<name>TIM8_BRK_TIM12</name>
<description>TIM8 Break interrupt and TIM12 global
interrupt</description>
<value>43</value>
</interrupt>
<interrupt>
<name>TIM8_CC</name>
<description>TIM8 Capture Compare interrupt</description>
<value>46</value>
</interrupt>
<interrupt>
<name>TIM8_CC</name>
<description>TIM8 Capture Compare interrupt</description>
<value>46</value>
</interrupt>
</peripheral>
<peripheral>
<name>TIM2</name>
<description>General purpose timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM2</name>
<description>TIM2 global interrupt</description>
<value>28</value>
</interrupt>
<interrupt>
<name>TIM2</name>
<description>TIM2 global interrupt</description>
<value>28</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 &#215; t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 &#215; t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CMS</name>
<description>Center-aligned mode
selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CMS</name><usage>read-write</usage><enumeratedValue><name>EdgeAligned</name><description>The counter counts up or down depending on the direction bit</description><value>0</value></enumeratedValue><enumeratedValue><name>CenterAligned1</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.</description><value>1</value></enumeratedValue><enumeratedValue><name>CenterAligned2</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.</description><value>2</value></enumeratedValue><enumeratedValue><name>CenterAligned3</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DIR</name><usage>read-write</usage><enumeratedValue><name>Up</name><description>Counter used as upcounter</description><value>0</value></enumeratedValue><enumeratedValue><name>Down</name><description>Counter used as downcounter</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TI1S</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>The TIMx_CH1 pin is connected to TI1 input</description><value>0</value></enumeratedValue><enumeratedValue><name>XOR</name><description>The TIMx_CH1, CH2, CH3 pins are connected to TI1 input</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>MMS</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>The UG bit from the TIMx_EGR register is used as trigger output</description><value>0</value></enumeratedValue><enumeratedValue><name>Enable</name><description>The counter enable signal, CNT_EN, is used as trigger output</description><value>1</value></enumeratedValue><enumeratedValue><name>Update</name><description>The update event is selected as trigger output</description><value>2</value></enumeratedValue><enumeratedValue><name>ComparePulse</name><description>The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred</description><value>3</value></enumeratedValue><enumeratedValue><name>CompareOC1</name><description>OC1REF signal is used as trigger output</description><value>4</value></enumeratedValue><enumeratedValue><name>CompareOC2</name><description>OC2REF signal is used as trigger output</description><value>5</value></enumeratedValue><enumeratedValue><name>CompareOC3</name><description>OC3REF signal is used as trigger output</description><value>6</value></enumeratedValue><enumeratedValue><name>CompareOC4</name><description>OC4REF signal is used as trigger output</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CCDS</name><usage>read-write</usage><enumeratedValue><name>OnCompare</name><description>CCx DMA request sent when CCx event occurs</description><value>0</value></enumeratedValue><enumeratedValue><name>OnUpdate</name><description>CCx DMA request sent when update event occurs</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ETP</name>
<description>External trigger polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ETP</name><usage>read-write</usage><enumeratedValue><name>NotInverted</name><description>ETR is noninverted, active at high level or rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Inverted</name><description>ETR is inverted, active at low level or falling edge</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ECE</name>
<description>External clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ECE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>External clock mode 2 disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ETPS</name>
<description>External trigger prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>ETPS</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>Prescaler OFF</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>ETRP frequency divided by 2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>ETRP frequency divided by 4</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>ETRP frequency divided by 8</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ETF</name>
<description>External trigger filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>ETF</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MSM</name><usage>read-write</usage><enumeratedValue><name>NoSync</name><description>No action</description><value>0</value></enumeratedValue><enumeratedValue><name>Sync</name><description>The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>TS</name><usage>read-write</usage><enumeratedValue><name>ITR0</name><description>Internal Trigger 0 (ITR0)</description><value>0</value></enumeratedValue><enumeratedValue><name>ITR1</name><description>Internal Trigger 1 (ITR1)</description><value>1</value></enumeratedValue><enumeratedValue><name>ITR2</name><description>Internal Trigger 2 (ITR2)</description><value>2</value></enumeratedValue><enumeratedValue><name>TI1F_ED</name><description>TI1 Edge Detector (TI1F_ED)</description><value>4</value></enumeratedValue><enumeratedValue><name>TI1FP1</name><description>Filtered Timer Input 1 (TI1FP1)</description><value>5</value></enumeratedValue><enumeratedValue><name>TI2FP2</name><description>Filtered Timer Input 2 (TI2FP2)</description><value>6</value></enumeratedValue><enumeratedValue><name>ETRF</name><description>External Trigger input (ETRF)</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>SMS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Slave mode disabled - if CEN = &#8216;1 then the prescaler is clocked directly by the internal clock.</description><value>0</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_1</name><description>Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.</description><value>1</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_2</name><description>Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.</description><value>2</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_3</name><description>Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.</description><value>3</value></enumeratedValue><enumeratedValue><name>Reset_Mode</name><description>Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.</description><value>4</value></enumeratedValue><enumeratedValue><name>Gated_Mode</name><description>Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.</description><value>5</value></enumeratedValue><enumeratedValue><name>Trigger_Mode</name><description>Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.</description><value>6</value></enumeratedValue><enumeratedValue><name>Ext_Clock_Mode</name><description>External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4DE</name>
<description>Capture/Compare 4 DMA request
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC3DE</name>
<description>Capture/Compare 3 DMA request
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1DE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4IE</name>
<description>Capture/Compare 4 interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC3IE</name>
<description>Capture/Compare 3 interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1IE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC4OF</name>
<description>Capture/Compare 4 overcapture
flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC3OF</name>
<description>Capture/Compare 3 overcapture
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture
flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1OFR</name><usage>read</usage><enumeratedValue><name>Overcapture</name><description>The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>CC1OFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIFR</name><usage>read</usage><enumeratedValue><name>NoTrigger</name><description>No trigger event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Trigger</name><description>Trigger interrupt pending</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>TIFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4IF</name>
<description>Capture/Compare 4 interrupt
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC3IF</name>
<description>Capture/Compare 3 interrupt
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1IFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>CC1IFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TGW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4G</name>
<description>Capture/compare 4
generation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC3G</name>
<description>Capture/compare 3
generation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2
generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1GW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC2CE</name>
<description>OC2CE</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>OC2M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="OC1M"/>
</field>
<field>
<name>OC2PE</name>
<description>OC2PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC2PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR2 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC2FE</name>
<description>OC2FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>CC2S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC2 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1CE</name>
<description>OC1CE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>OC1M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT&lt;TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT&gt;TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1PE</name>
<description>OC1PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC1PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR1 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1FE</name>
<description>OC1FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>CC1S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC1 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC2PSC</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>TI2</name><description>CC2 channel is configured as input, IC2 is mapped on TI2</description><value>1</value></enumeratedValue><enumeratedValue><name>TI1</name><description>CC2 channel is configured as input, IC2 is mapped on TI1</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC2 channel is configured as input, IC2 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>IC1F</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>TI1</name><description>CC1 channel is configured as input, IC1 is mapped on TI1</description><value>1</value></enumeratedValue><enumeratedValue><name>TI2</name><description>CC1 channel is configured as input, IC1 is mapped on TI2</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC1 channel is configured as input, IC1 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR2_Output</name>
<displayName>CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output
mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC4CE</name>
<description>O24CE</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M</name>
<description>OC4M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="OC3M"/>
</field>
<field>
<name>OC4PE</name>
<description>OC4PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC4PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR4 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC4FE</name>
<description>OC4FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>CC4S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC4 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3CE</name>
<description>OC3CE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>OC3M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>OC3M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT&lt;TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT&gt;TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3PE</name>
<description>OC3PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC3PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR3 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3FE</name>
<description>OC3FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>CC3S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC3 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR2_Input</name>
<displayName>CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input
mode)</description>
<alternateRegister>CCMR2_Output</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC4F</name>
<description>Input capture 4 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC4PSC</name>
<description>Input capture 4 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>TI4</name><description>CC4 channel is configured as input, IC4 is mapped on TI4</description><value>1</value></enumeratedValue><enumeratedValue><name>TI3</name><description>CC4 channel is configured as input, IC4 is mapped on TI3</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC4 channel is configured as input, IC4 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC3F</name>
<description>Input capture 3 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC3PSC</name>
<description>Input capture 3 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>CC3S</name>
<description>Capture/compare 3
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>TI3</name><description>CC3 channel is configured as input, IC3 is mapped on TI3</description><value>1</value></enumeratedValue><enumeratedValue><name>TI4</name><description>CC3 channel is configured as input, IC3 is mapped on TI4</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC3 channel is configured as input, IC3 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC4NP</name>
<description>Capture/Compare 4 output
Polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>Capture/Compare 4 output
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NP</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>Capture/Compare 3 output
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>CNT</name><description>Counter value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field></fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>ARR</name><description>Auto-reload value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field></fields>
</register>
<register>
<dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>CCR%s</name>
<displayName>CCR1</displayName>
<description>capture/compare register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>CCR</name><description>Capture/Compare value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field></fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst
accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR</name>
<displayName>OR</displayName>
<description>TIM5 option register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ITR1_RMP</name>
<description>Timer Input 4 remap</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM3</name>
<description>General purpose timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40000400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM3</name>
<description>TIM3 global interrupt</description>
<value>29</value>
</interrupt>
<interrupt>
<name>TIM3</name>
<description>TIM3 global interrupt</description>
<value>29</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 &#215; t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 &#215; t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CMS</name>
<description>Center-aligned mode
selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CMS</name><usage>read-write</usage><enumeratedValue><name>EdgeAligned</name><description>The counter counts up or down depending on the direction bit</description><value>0</value></enumeratedValue><enumeratedValue><name>CenterAligned1</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.</description><value>1</value></enumeratedValue><enumeratedValue><name>CenterAligned2</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.</description><value>2</value></enumeratedValue><enumeratedValue><name>CenterAligned3</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DIR</name><usage>read-write</usage><enumeratedValue><name>Up</name><description>Counter used as upcounter</description><value>0</value></enumeratedValue><enumeratedValue><name>Down</name><description>Counter used as downcounter</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TI1S</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>The TIMx_CH1 pin is connected to TI1 input</description><value>0</value></enumeratedValue><enumeratedValue><name>XOR</name><description>The TIMx_CH1, CH2, CH3 pins are connected to TI1 input</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>MMS</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>The UG bit from the TIMx_EGR register is used as trigger output</description><value>0</value></enumeratedValue><enumeratedValue><name>Enable</name><description>The counter enable signal, CNT_EN, is used as trigger output</description><value>1</value></enumeratedValue><enumeratedValue><name>Update</name><description>The update event is selected as trigger output</description><value>2</value></enumeratedValue><enumeratedValue><name>ComparePulse</name><description>The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred</description><value>3</value></enumeratedValue><enumeratedValue><name>CompareOC1</name><description>OC1REF signal is used as trigger output</description><value>4</value></enumeratedValue><enumeratedValue><name>CompareOC2</name><description>OC2REF signal is used as trigger output</description><value>5</value></enumeratedValue><enumeratedValue><name>CompareOC3</name><description>OC3REF signal is used as trigger output</description><value>6</value></enumeratedValue><enumeratedValue><name>CompareOC4</name><description>OC4REF signal is used as trigger output</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CCDS</name><usage>read-write</usage><enumeratedValue><name>OnCompare</name><description>CCx DMA request sent when CCx event occurs</description><value>0</value></enumeratedValue><enumeratedValue><name>OnUpdate</name><description>CCx DMA request sent when update event occurs</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ETP</name>
<description>External trigger polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ETP</name><usage>read-write</usage><enumeratedValue><name>NotInverted</name><description>ETR is noninverted, active at high level or rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Inverted</name><description>ETR is inverted, active at low level or falling edge</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ECE</name>
<description>External clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ECE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>External clock mode 2 disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ETPS</name>
<description>External trigger prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>ETPS</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>Prescaler OFF</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>ETRP frequency divided by 2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>ETRP frequency divided by 4</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>ETRP frequency divided by 8</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ETF</name>
<description>External trigger filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>ETF</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MSM</name><usage>read-write</usage><enumeratedValue><name>NoSync</name><description>No action</description><value>0</value></enumeratedValue><enumeratedValue><name>Sync</name><description>The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>TS</name><usage>read-write</usage><enumeratedValue><name>ITR0</name><description>Internal Trigger 0 (ITR0)</description><value>0</value></enumeratedValue><enumeratedValue><name>ITR1</name><description>Internal Trigger 1 (ITR1)</description><value>1</value></enumeratedValue><enumeratedValue><name>ITR2</name><description>Internal Trigger 2 (ITR2)</description><value>2</value></enumeratedValue><enumeratedValue><name>TI1F_ED</name><description>TI1 Edge Detector (TI1F_ED)</description><value>4</value></enumeratedValue><enumeratedValue><name>TI1FP1</name><description>Filtered Timer Input 1 (TI1FP1)</description><value>5</value></enumeratedValue><enumeratedValue><name>TI2FP2</name><description>Filtered Timer Input 2 (TI2FP2)</description><value>6</value></enumeratedValue><enumeratedValue><name>ETRF</name><description>External Trigger input (ETRF)</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>SMS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Slave mode disabled - if CEN = &#8216;1 then the prescaler is clocked directly by the internal clock.</description><value>0</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_1</name><description>Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.</description><value>1</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_2</name><description>Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.</description><value>2</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_3</name><description>Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.</description><value>3</value></enumeratedValue><enumeratedValue><name>Reset_Mode</name><description>Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.</description><value>4</value></enumeratedValue><enumeratedValue><name>Gated_Mode</name><description>Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.</description><value>5</value></enumeratedValue><enumeratedValue><name>Trigger_Mode</name><description>Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.</description><value>6</value></enumeratedValue><enumeratedValue><name>Ext_Clock_Mode</name><description>External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4DE</name>
<description>Capture/Compare 4 DMA request
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC3DE</name>
<description>Capture/Compare 3 DMA request
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1DE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4IE</name>
<description>Capture/Compare 4 interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC3IE</name>
<description>Capture/Compare 3 interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1IE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC4OF</name>
<description>Capture/Compare 4 overcapture
flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC3OF</name>
<description>Capture/Compare 3 overcapture
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture
flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1OFR</name><usage>read</usage><enumeratedValue><name>Overcapture</name><description>The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>CC1OFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIFR</name><usage>read</usage><enumeratedValue><name>NoTrigger</name><description>No trigger event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Trigger</name><description>Trigger interrupt pending</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>TIFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4IF</name>
<description>Capture/Compare 4 interrupt
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC3IF</name>
<description>Capture/Compare 3 interrupt
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1IFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>CC1IFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TGW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4G</name>
<description>Capture/compare 4
generation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC3G</name>
<description>Capture/compare 3
generation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2
generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1GW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC2CE</name>
<description>OC2CE</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>OC2M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="OC1M"/>
</field>
<field>
<name>OC2PE</name>
<description>OC2PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC2PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR2 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC2FE</name>
<description>OC2FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>CC2S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC2 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1CE</name>
<description>OC1CE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>OC1M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT&lt;TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT&gt;TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1PE</name>
<description>OC1PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC1PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR1 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1FE</name>
<description>OC1FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>CC1S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC1 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC2PSC</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>TI2</name><description>CC2 channel is configured as input, IC2 is mapped on TI2</description><value>1</value></enumeratedValue><enumeratedValue><name>TI1</name><description>CC2 channel is configured as input, IC2 is mapped on TI1</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC2 channel is configured as input, IC2 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>IC1F</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>TI1</name><description>CC1 channel is configured as input, IC1 is mapped on TI1</description><value>1</value></enumeratedValue><enumeratedValue><name>TI2</name><description>CC1 channel is configured as input, IC1 is mapped on TI2</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC1 channel is configured as input, IC1 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR2_Output</name>
<displayName>CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output
mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC4CE</name>
<description>O24CE</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M</name>
<description>OC4M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="OC3M"/>
</field>
<field>
<name>OC4PE</name>
<description>OC4PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC4PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR4 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC4FE</name>
<description>OC4FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>CC4S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC4 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3CE</name>
<description>OC3CE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>OC3M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>OC3M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT&lt;TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT&gt;TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3PE</name>
<description>OC3PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC3PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR3 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3FE</name>
<description>OC3FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>CC3S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC3 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR2_Input</name>
<displayName>CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input
mode)</description>
<alternateRegister>CCMR2_Output</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC4F</name>
<description>Input capture 4 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC4PSC</name>
<description>Input capture 4 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>TI4</name><description>CC4 channel is configured as input, IC4 is mapped on TI4</description><value>1</value></enumeratedValue><enumeratedValue><name>TI3</name><description>CC4 channel is configured as input, IC4 is mapped on TI3</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC4 channel is configured as input, IC4 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC3F</name>
<description>Input capture 3 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC3PSC</name>
<description>Input capture 3 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>CC3S</name>
<description>Capture/compare 3
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>TI3</name><description>CC3 channel is configured as input, IC3 is mapped on TI3</description><value>1</value></enumeratedValue><enumeratedValue><name>TI4</name><description>CC3 channel is configured as input, IC3 is mapped on TI4</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC3 channel is configured as input, IC3 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC4NP</name>
<description>Capture/Compare 4 output
Polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>Capture/Compare 4 output
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NP</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>Capture/Compare 3 output
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_H</name>
<description>High counter value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT</name>
<description>Counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR_H</name>
<description>High Auto-reload value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>CCR%s</name>
<displayName>CCR1</displayName>
<description>capture/compare register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR1_H</name>
<description>High Capture/Compare 1
value</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CCR</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst
accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM3">
<name>TIM4</name>
<baseAddress>0x40000800</baseAddress>
<interrupt>
<name>TIM4</name>
<description>TIM4 global interrupt</description>
<value>30</value>
</interrupt>
<interrupt>
<name>TIM4</name>
<description>TIM4 global interrupt</description>
<value>30</value>
</interrupt>
</peripheral>
<peripheral>
<name>TIM5</name>
<description>General-purpose-timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40000C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIM5</name>
<description>TIM5 global interrupt</description>
<value>50</value>
</interrupt>
<interrupt>
<name>TIM5</name>
<description>TIM5 global interrupt</description>
<value>50</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 &#215; t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 &#215; t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CMS</name>
<description>Center-aligned mode
selection</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CMS</name><usage>read-write</usage><enumeratedValue><name>EdgeAligned</name><description>The counter counts up or down depending on the direction bit</description><value>0</value></enumeratedValue><enumeratedValue><name>CenterAligned1</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.</description><value>1</value></enumeratedValue><enumeratedValue><name>CenterAligned2</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.</description><value>2</value></enumeratedValue><enumeratedValue><name>CenterAligned3</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DIR</name>
<description>Direction</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DIR</name><usage>read-write</usage><enumeratedValue><name>Up</name><description>Counter used as upcounter</description><value>0</value></enumeratedValue><enumeratedValue><name>Down</name><description>Counter used as downcounter</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TI1S</name>
<description>TI1 selection</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TI1S</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>The TIMx_CH1 pin is connected to TI1 input</description><value>0</value></enumeratedValue><enumeratedValue><name>XOR</name><description>The TIMx_CH1, CH2, CH3 pins are connected to TI1 input</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>MMS</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>The UG bit from the TIMx_EGR register is used as trigger output</description><value>0</value></enumeratedValue><enumeratedValue><name>Enable</name><description>The counter enable signal, CNT_EN, is used as trigger output</description><value>1</value></enumeratedValue><enumeratedValue><name>Update</name><description>The update event is selected as trigger output</description><value>2</value></enumeratedValue><enumeratedValue><name>ComparePulse</name><description>The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred</description><value>3</value></enumeratedValue><enumeratedValue><name>CompareOC1</name><description>OC1REF signal is used as trigger output</description><value>4</value></enumeratedValue><enumeratedValue><name>CompareOC2</name><description>OC2REF signal is used as trigger output</description><value>5</value></enumeratedValue><enumeratedValue><name>CompareOC3</name><description>OC3REF signal is used as trigger output</description><value>6</value></enumeratedValue><enumeratedValue><name>CompareOC4</name><description>OC4REF signal is used as trigger output</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CCDS</name>
<description>Capture/compare DMA
selection</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CCDS</name><usage>read-write</usage><enumeratedValue><name>OnCompare</name><description>CCx DMA request sent when CCx event occurs</description><value>0</value></enumeratedValue><enumeratedValue><name>OnUpdate</name><description>CCx DMA request sent when update event occurs</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ETP</name>
<description>External trigger polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ETP</name><usage>read-write</usage><enumeratedValue><name>NotInverted</name><description>ETR is noninverted, active at high level or rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Inverted</name><description>ETR is inverted, active at low level or falling edge</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ECE</name>
<description>External clock enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ECE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>External clock mode 2 disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ETPS</name>
<description>External trigger prescaler</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>ETPS</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>Prescaler OFF</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>ETRP frequency divided by 2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>ETRP frequency divided by 4</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>ETRP frequency divided by 8</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ETF</name>
<description>External trigger filter</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>ETF</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MSM</name><usage>read-write</usage><enumeratedValue><name>NoSync</name><description>No action</description><value>0</value></enumeratedValue><enumeratedValue><name>Sync</name><description>The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>TS</name><usage>read-write</usage><enumeratedValue><name>ITR0</name><description>Internal Trigger 0 (ITR0)</description><value>0</value></enumeratedValue><enumeratedValue><name>ITR1</name><description>Internal Trigger 1 (ITR1)</description><value>1</value></enumeratedValue><enumeratedValue><name>ITR2</name><description>Internal Trigger 2 (ITR2)</description><value>2</value></enumeratedValue><enumeratedValue><name>TI1F_ED</name><description>TI1 Edge Detector (TI1F_ED)</description><value>4</value></enumeratedValue><enumeratedValue><name>TI1FP1</name><description>Filtered Timer Input 1 (TI1FP1)</description><value>5</value></enumeratedValue><enumeratedValue><name>TI2FP2</name><description>Filtered Timer Input 2 (TI2FP2)</description><value>6</value></enumeratedValue><enumeratedValue><name>ETRF</name><description>External Trigger input (ETRF)</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>SMS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Slave mode disabled - if CEN = &#8216;1 then the prescaler is clocked directly by the internal clock.</description><value>0</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_1</name><description>Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.</description><value>1</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_2</name><description>Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.</description><value>2</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_3</name><description>Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.</description><value>3</value></enumeratedValue><enumeratedValue><name>Reset_Mode</name><description>Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.</description><value>4</value></enumeratedValue><enumeratedValue><name>Gated_Mode</name><description>Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.</description><value>5</value></enumeratedValue><enumeratedValue><name>Trigger_Mode</name><description>Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.</description><value>6</value></enumeratedValue><enumeratedValue><name>Ext_Clock_Mode</name><description>External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TDE</name>
<description>Trigger DMA request enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4DE</name>
<description>Capture/Compare 4 DMA request
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC3DE</name>
<description>Capture/Compare 3 DMA request
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC2DE</name>
<description>Capture/Compare 2 DMA request
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1DE"/>
</field>
<field>
<name>CC1DE</name>
<description>Capture/Compare 1 DMA request
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1DE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4IE</name>
<description>Capture/Compare 4 interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC3IE</name>
<description>Capture/Compare 3 interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IE"/>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1IE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC4OF</name>
<description>Capture/Compare 4 overcapture
flag</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC3OF</name>
<description>Capture/Compare 3 overcapture
flag</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture
flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1OFR"/>
<enumeratedValues derivedFrom="CC1OFW"/>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1OFR</name><usage>read</usage><enumeratedValue><name>Overcapture</name><description>The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>CC1OFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TIFR</name><usage>read</usage><enumeratedValue><name>NoTrigger</name><description>No trigger event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Trigger</name><description>Trigger interrupt pending</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>TIFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4IF</name>
<description>Capture/Compare 4 interrupt
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC3IF</name>
<description>Capture/Compare 3 interrupt
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1IFR"/>
<enumeratedValues derivedFrom="CC1IFW"/>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1IFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>CC1IFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TGW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CC4G</name>
<description>Capture/compare 4
generation</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC3G</name>
<description>Capture/compare 3
generation</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2
generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="CC1GW"/>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CC1GW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC2CE</name>
<description>OC2CE</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2M</name>
<description>OC2M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="OC1M"/>
</field>
<field>
<name>OC2PE</name>
<description>OC2PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC2PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR2 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC2FE</name>
<description>OC2FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>CC2S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC2 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1CE</name>
<description>OC1CE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>OC1M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT&lt;TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT&gt;TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1PE</name>
<description>OC1PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC1PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR1 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1FE</name>
<description>OC1FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>CC1S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC1 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC2PSC</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>TI2</name><description>CC2 channel is configured as input, IC2 is mapped on TI2</description><value>1</value></enumeratedValue><enumeratedValue><name>TI1</name><description>CC2 channel is configured as input, IC2 is mapped on TI1</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC2 channel is configured as input, IC2 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>IC1F</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>TI1</name><description>CC1 channel is configured as input, IC1 is mapped on TI1</description><value>1</value></enumeratedValue><enumeratedValue><name>TI2</name><description>CC1 channel is configured as input, IC1 is mapped on TI2</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC1 channel is configured as input, IC1 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR2_Output</name>
<displayName>CCMR2_Output</displayName>
<description>capture/compare mode register 2 (output
mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC4CE</name>
<description>O24CE</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC4M</name>
<description>OC4M</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="OC3M"/>
</field>
<field>
<name>OC4PE</name>
<description>OC4PE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC4PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR4 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC4FE</name>
<description>OC4FE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4S</name>
<description>CC4S</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC4 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3CE</name>
<description>OC3CE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC3M</name>
<description>OC3M</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>OC3M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT&lt;TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT&gt;TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3PE</name>
<description>OC3PE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OC3PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR3 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC3FE</name>
<description>OC3FE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3S</name>
<description>CC3S</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC3 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR2_Input</name>
<displayName>CCMR2_Input</displayName>
<description>capture/compare mode register 2 (input
mode)</description>
<alternateRegister>CCMR2_Output</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC4F</name>
<description>Input capture 4 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC4PSC</name>
<description>Input capture 4 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>CC4S</name>
<description>Capture/Compare 4
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>TI4</name><description>CC4 channel is configured as input, IC4 is mapped on TI4</description><value>1</value></enumeratedValue><enumeratedValue><name>TI3</name><description>CC4 channel is configured as input, IC4 is mapped on TI3</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC4 channel is configured as input, IC4 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IC3F</name>
<description>Input capture 3 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint>
</field>
<field>
<name>IC3PSC</name>
<description>Input capture 3 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint>
</field>
<field>
<name>CC3S</name>
<description>Capture/compare 3
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>TI3</name><description>CC3 channel is configured as input, IC3 is mapped on TI3</description><value>1</value></enumeratedValue><enumeratedValue><name>TI4</name><description>CC3 channel is configured as input, IC3 is mapped on TI4</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC3 channel is configured as input, IC3 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC4NP</name>
<description>Capture/Compare 4 output
Polarity</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC4E</name>
<description>Capture/Compare 4 output
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3NP</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3P</name>
<description>Capture/Compare 3 output
Polarity</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC3E</name>
<description>Capture/Compare 3 output
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>CNT</name><description>Counter value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field></fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>ARR</name><description>Auto-reload value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field></fields>
</register>
<register>
<dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>CCR%s</name>
<displayName>CCR1</displayName>
<description>capture/compare register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>CCR</name><description>Capture/Compare value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field></fields>
</register>
<register>
<name>DCR</name>
<displayName>DCR</displayName>
<description>DMA control register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DBL</name>
<description>DMA burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint>
</field>
<field>
<name>DBA</name>
<description>DMA base address</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DMAR</name>
<displayName>DMAR</displayName>
<description>DMA address for full transfer</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DMAB</name>
<description>DMA register for burst
accesses</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR</name>
<displayName>OR</displayName>
<description>TIM5 option register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>IT4_RMP</name>
<description>Timer Input 4 remap</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM9</name>
<description>General purpose timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40014000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 &#215; t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 &#215; t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SMCR</name>
<displayName>SMCR</displayName>
<description>slave mode control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>MSM</name>
<description>Master/Slave mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TS</name>
<description>Trigger selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SMS</name>
<description>Slave mode selection</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TIE</name>
<description>Trigger interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IE</name>
<description>Capture/Compare 2 interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC2OF</name>
<description>Capture/compare 2 overcapture
flag</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIF</name>
<description>Trigger interrupt flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2IF</name>
<description>Capture/Compare 2 interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>TG</name>
<description>Trigger generation</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2G</name>
<description>Capture/compare 2
generation</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC2M</name>
<description>Output Compare 2 mode</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="OC1M"/>
</field>
<field>
<name>OC2PE</name>
<description>Output Compare 2 preload
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC2FE</name>
<description>Output Compare 2 fast
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT&lt;TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT&gt;TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC2F</name>
<description>Input capture 2 filter</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>IC2PSC</name>
<description>Input capture 2 prescaler</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC2S</name>
<description>Capture/Compare 2
selection</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC2NP</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2P</name>
<description>Capture/Compare 2 output
Polarity</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC2E</name>
<description>Capture/Compare 2 output
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<dim>2</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2</dimIndex><name>CCR%s</name>
<displayName>CCR1</displayName>
<description>capture/compare register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM9">
<name>TIM12</name>
<baseAddress>0x40001800</baseAddress>
</peripheral>
<peripheral>
<name>TIM10</name>
<description>General-purpose-timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40014400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 &#215; t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 &#215; t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT&lt;TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT&gt;TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<dim>1</dim><dimIncrement>0x0</dimIncrement><dimIndex>1-1</dimIndex><name>CCR%s</name>
<displayName>CCR1</displayName>
<description>capture/compare register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM10">
<name>TIM13</name>
<baseAddress>0x40001C00</baseAddress>
<interrupt>
<name>TIM8_UP_TIM13</name>
<description>TIM8 Update interrupt and TIM13 global
interrupt</description>
<value>44</value>
</interrupt>
<interrupt>
<name>TIM8_UP_TIM13</name>
<description>TIM8 Update interrupt and TIM13 global
interrupt</description>
<value>44</value>
</interrupt>
<interrupt>
<name>TIM8_UP_TIM13</name>
<description>TIM8 Update interrupt and TIM13 global
interrupt</description>
<value>44</value>
</interrupt>
<interrupt>
<name>TIM8_UP_TIM13</name>
<description>TIM8 Update interrupt and TIM13 global
interrupt</description>
<value>44</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="TIM10">
<name>TIM14</name>
<baseAddress>0x40002000</baseAddress>
<interrupt>
<name>TIM8_TRG_COM_TIM14</name>
<description>TIM8 Trigger and Commutation interrupts and
TIM14 global interrupt</description>
<value>45</value>
</interrupt>
<interrupt>
<name>TIM8_TRG_COM_TIM14</name>
<description>TIM8 Trigger and Commutation interrupts and
TIM14 global interrupt</description>
<value>45</value>
</interrupt>
</peripheral>
<peripheral>
<name>TIM11</name>
<description>General-purpose-timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40014800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CKD</name>
<description>Clock division</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 &#215; t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 &#215; t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1IE</name>
<description>Capture/Compare 1 interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1OF</name>
<description>Capture/Compare 1 overcapture
flag</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1IF</name>
<description>Capture/compare 1 interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1G</name>
<description>Capture/compare 1
generation</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CCMR1_Output</name>
<displayName>CCMR1_Output</displayName>
<description>capture/compare mode register 1 (output
mode)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OC1M</name>
<description>Output Compare 1 mode</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT&lt;TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT&gt;TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OC1PE</name>
<description>Output Compare 1 preload
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OC1FE</name>
<description>Output Compare 1 fast
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCMR1_Input</name>
<displayName>CCMR1_Input</displayName>
<description>capture/compare mode register 1 (input
mode)</description>
<alternateRegister>CCMR1_Output</alternateRegister>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IC1F</name>
<description>Input capture 1 filter</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IC1PSC</name>
<description>Input capture 1 prescaler</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CC1S</name>
<description>Capture/Compare 1
selection</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCER</name>
<displayName>CCER</displayName>
<description>capture/compare enable
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>CC1NP</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1P</name>
<description>Capture/Compare 1 output
Polarity</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CC1E</name>
<description>Capture/Compare 1 output
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<dim>1</dim><dimIncrement>0x0</dimIncrement><dimIndex>1-1</dimIndex><name>CCR%s</name>
<displayName>CCR1</displayName>
<description>capture/compare register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCR</name>
<description>Capture/Compare value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>OR</name>
<displayName>OR</displayName>
<description>option register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RMP</name>
<description>Input 1 remapping
capability</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>TIM6</name>
<description>Basic timers</description>
<groupName>TIM</groupName>
<baseAddress>0x40001000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ARPE</name>
<description>Auto-reload preload enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OPM</name>
<description>One-pulse mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>URS</name>
<description>Update request source</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UDIS</name>
<description>Update disable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CEN</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>MMS</name>
<description>Master mode selection</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>MMS</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Use UG bit from TIMx_EGR register</description><value>0</value></enumeratedValue><enumeratedValue><name>Enable</name><description>Use CNT bit from TIMx_CEN register</description><value>1</value></enumeratedValue><enumeratedValue><name>Update</name><description>Use the update event</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DIER</name>
<displayName>DIER</displayName>
<description>DMA/Interrupt enable register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UDE</name>
<description>Update DMA request enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UIE</name>
<description>Update interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>status register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UIF</name>
<description>Update interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>EGR</name>
<displayName>EGR</displayName>
<description>event generation register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>UG</name>
<description>Update generation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CNT</name>
<displayName>CNT</displayName>
<description>counter</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT</name>
<description>Low counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PSC</name>
<displayName>PSC</displayName>
<description>prescaler</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PSC</name>
<description>Prescaler value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>ARR</name>
<displayName>ARR</displayName>
<description>auto-reload register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ARR</name>
<description>Low Auto-reload value</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIM6">
<name>TIM7</name>
<baseAddress>0x40001400</baseAddress>
<interrupt>
<name>TIM7</name>
<description>TIM7 global interrupt</description>
<value>55</value>
</interrupt>
<interrupt>
<name>TIM7</name>
<description>TIM7 global interrupt</description>
<value>55</value>
</interrupt>
</peripheral>
<peripheral>
<name>Ethernet_MAC</name>
<description>Ethernet: media access control
(MAC)</description>
<groupName>Ethernet</groupName>
<baseAddress>0x40028000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x61</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>ETH</name>
<description>Ethernet global interrupt</description>
<value>61</value>
</interrupt>
<interrupt>
<name>ETH</name>
<description>Ethernet global interrupt</description>
<value>61</value>
</interrupt>
<interrupt>
<name>ETH_WKUP</name>
<description>Ethernet Wakeup through EXTI line
interrupt</description>
<value>62</value>
</interrupt>
<interrupt>
<name>ETH_WKUP</name>
<description>Ethernet Wakeup through EXTI line
interrupt</description>
<value>62</value>
</interrupt>
<registers>
<register>
<name>MACCR</name>
<displayName>MACCR</displayName>
<description>Ethernet MAC configuration
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0008000</resetValue>
<fields>
<field>
<name>RE</name>
<description>Receiver enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC receive state machine is disabled after the completion of the reception of the current frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC receive state machine is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TE</name>
<description>Transmitter enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC transmit state machine is disabled after completion of the transmission of the current frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC transmit state machine is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DC</name>
<description>Deferral check</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DC</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC defers until CRS signal goes inactive</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Deferral check function enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BL</name>
<description>Back-off limit</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>BL</name><usage>read-write</usage><enumeratedValue><name>BL10</name><description>For retransmission n, wait up to 2^min(n, 10) time slots</description><value>0</value></enumeratedValue><enumeratedValue><name>BL8</name><description>For retransmission n, wait up to 2^min(n, 8) time slots</description><value>1</value></enumeratedValue><enumeratedValue><name>BL4</name><description>For retransmission n, wait up to 2^min(n, 4) time slots</description><value>2</value></enumeratedValue><enumeratedValue><name>BL1</name><description>For retransmission n, wait up to 2^min(n, 1) time slots</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>APCS</name>
<description>Automatic pad/CRC stripping</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>APCS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC passes all incoming frames unmodified</description><value>0</value></enumeratedValue><enumeratedValue><name>Strip</name><description>MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RD</name>
<description>Retry disable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>MAC attempts retries based on the settings of BL</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>MAC attempts only 1 transmission</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IPCO</name>
<description>IPv4 checksum offload</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IPCO</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>IPv4 checksum offload disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Offload</name><description>IPv4 checksums are checked in received frames</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DM</name>
<description>Duplex mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DM</name><usage>read-write</usage><enumeratedValue><name>HalfDuplex</name><description>MAC operates in half-duplex mode</description><value>0</value></enumeratedValue><enumeratedValue><name>FullDuplex</name><description>MAC operates in full-duplex mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LM</name>
<description>Loopback mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LM</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Loopback</name><description>MAC operates in loopback mode at the MII</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ROD</name>
<description>Receive own disable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ROD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>MAC receives all packets from PHY while transmitting</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>MAC disables reception of frames in half-duplex mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FES</name>
<description>Fast Ethernet speed</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FES</name><usage>read-write</usage><enumeratedValue><name>FES10</name><description>10 Mbit/s</description><value>0</value></enumeratedValue><enumeratedValue><name>FES100</name><description>100 Mbit/s</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CSD</name>
<description>Carrier sense disable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CSD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Errors generated due to loss of carrier</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>No error generated due to loss of carrier</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IFG</name>
<description>Interframe gap</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>IFG</name><usage>read-write</usage><enumeratedValue><name>IFG96</name><description>96 bit times</description><value>0</value></enumeratedValue><enumeratedValue><name>IFG88</name><description>88 bit times</description><value>1</value></enumeratedValue><enumeratedValue><name>IFG80</name><description>80 bit times</description><value>2</value></enumeratedValue><enumeratedValue><name>IFG72</name><description>72 bit times</description><value>3</value></enumeratedValue><enumeratedValue><name>IFG64</name><description>64 bit times</description><value>4</value></enumeratedValue><enumeratedValue><name>IFG56</name><description>56 bit times</description><value>5</value></enumeratedValue><enumeratedValue><name>IFG48</name><description>48 bit times</description><value>6</value></enumeratedValue><enumeratedValue><name>IFG40</name><description>40 bit times</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>JD</name>
<description>Jabber disable</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>JD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Jabber enabled, transmit frames up to 2048 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Jabber disabled, transmit frames up to 16384 bytes</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WD</name>
<description>Watchdog disable</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Watchdog enabled, receive frames limited to 2048 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Watchdog disabled, receive frames may be up to to 16384 bytes</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CSTF</name>
<description>CRC stripping for type frames</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CSTF</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CRC not stripped</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CRC stripped</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MACFFR</name>
<displayName>MACFFR</displayName>
<description>Ethernet MAC frame filter
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PM</name>
<description>Promiscuous mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Normal address filtering</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address filters pass all incoming frames regardless of their destination or source address</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HU</name>
<description>Hash unicast</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>HU</name><usage>read-write</usage><enumeratedValue><name>Perfect</name><description>MAC performs a perfect destination address filtering for unicast frames</description><value>0</value></enumeratedValue><enumeratedValue><name>Hash</name><description>MAC performs destination address filtering of received unicast frames according to the hash table</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HM</name>
<description>Hash multicast</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>HM</name><usage>read-write</usage><enumeratedValue><name>Perfect</name><description>MAC performs a perfect destination address filtering for multicast frames</description><value>0</value></enumeratedValue><enumeratedValue><name>Hash</name><description>MAC performs destination address filtering of received multicast frames according to the hash table</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DAIF</name>
<description>Destination address unique filtering</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DAIF</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal filtering of frames</description><value>0</value></enumeratedValue><enumeratedValue><name>Invert</name><description>Address check block operates in inverse filtering mode for the DA address comparison</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PAM</name>
<description>Pass all multicast</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PAM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Filtering of multicast frames depends on HM</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>All received frames with a multicast destination address are passed</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BFD</name>
<description>Broadcast frames disable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BFD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Address filters pass all received broadcast frames</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Address filters filter all incoming broadcast frames</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PCF</name>
<description>Pass control frames</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PCF</name><usage>read-write</usage><enumeratedValue><name>PreventAll</name><description>MAC prevents all control frames from reaching the application</description><value>0</value></enumeratedValue><enumeratedValue><name>ForwardAllExceptPause</name><description>MAC forwards all control frames to application except Pause</description><value>1</value></enumeratedValue><enumeratedValue><name>ForwardAll</name><description>MAC forwards all control frames to application even if they fail the address filter</description><value>2</value></enumeratedValue><enumeratedValue><name>ForwardAllFiltered</name><description>MAC forwards control frames that pass the address filter</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SAIF</name>
<description>Source address inverse filtering</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SAIF</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Source address filter operates normally</description><value>0</value></enumeratedValue><enumeratedValue><name>Invert</name><description>Source address filter operation inverted</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SAF</name>
<description>Source address filter</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SAF</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Source address ignored</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC drops frames that fail the source address filter</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HPF</name>
<description>Hash or perfect filter</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>HPF</name><usage>read-write</usage><enumeratedValue><name>HashOnly</name><description>If HM or HU is set, only frames that match the Hash filter are passed</description><value>0</value></enumeratedValue><enumeratedValue><name>HashOrPerfect</name><description>If HM or HU is set, frames that match either the perfect filter or the hash filter are passed</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RA</name>
<description>Receive all</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RA</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC receiver passes on to the application only those frames that have passed the SA/DA address file</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC receiver passes oll received frames on to the application</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MACHTHR</name>
<displayName>MACHTHR</displayName>
<description>Ethernet MAC hash table high
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HTH</name>
<description>Upper 32 bits of hash table</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>MACHTLR</name>
<displayName>MACHTLR</displayName>
<description>Ethernet MAC hash table low
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HTL</name>
<description>Lower 32 bits of hash table</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>MACMIIAR</name>
<displayName>MACMIIAR</displayName>
<description>Ethernet MAC MII address
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MB</name>
<description>MII busy</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MB</name><usage>read-write</usage><enumeratedValue><name>Busy</name><description>This bit is set to 1 by the application to indicate that a read or write access is in progress</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MW</name>
<description>MII write</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MW</name><usage>read-write</usage><enumeratedValue><name>Read</name><description>Read operation</description><value>0</value></enumeratedValue><enumeratedValue><name>Write</name><description>Write operation</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CR</name>
<description>Clock range</description>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>CR</name><usage>read-write</usage><enumeratedValue><name>CR_60_100</name><description>60-100MHz HCLK/42</description><value>0</value></enumeratedValue><enumeratedValue><name>CR_100_150</name><description>100-150 MHz HCLK/62</description><value>1</value></enumeratedValue><enumeratedValue><name>CR_20_35</name><description>20-35MHz HCLK/16</description><value>2</value></enumeratedValue><enumeratedValue><name>CR_35_60</name><description>35-60MHz HCLK/16</description><value>3</value></enumeratedValue><enumeratedValue><name>CR_150_168</name><description>150-168MHz HCLK/102</description><value>4</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MR</name>
<description>MII register - select the desired MII register in the PHY device</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
<field>
<name>PA</name>
<description>PHY address - select which of possible 32 PHYs is being accessed</description>
<bitOffset>11</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>MACMIIDR</name>
<displayName>MACMIIDR</displayName>
<description>Ethernet MAC MII data register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MD</name>
<description>MII data read from/written to the PHY</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>MACFCR</name>
<displayName>MACFCR</displayName>
<description>Ethernet MAC flow control
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FCB</name>
<description>Flow control busy/back pressure activate</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FCB</name><usage>read-write</usage><enumeratedValue><name>PauseOrBackPressure</name><description>In full duplex, initiate a Pause control frame. In half duplex, assert back pressure</description><value>1</value></enumeratedValue><enumeratedValue><name>DisableBackPressure</name><description>In half duplex only, deasserts back pressure</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TFCE</name>
<description>Transmit flow control enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TFCE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>In full duplex, flow control is disabled. In half duplex, back pressure is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>In full duplex, flow control is enabled. In half duplex, back pressure is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RFCE</name>
<description>Receive flow control enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RFCE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Pause frames are not decoded</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC decodes received Pause frames and disables its transmitted for a specified time</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>UPFD</name>
<description>Unicast pause frame detect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>UPFD</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC detects only a Pause frame with the multicast address specified in the 802.3x standard</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC additionally detects Pause frames with the station's unicast address</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PLT</name>
<description>Pause low threshold</description>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PLT</name><usage>read-write</usage><enumeratedValue><name>PLT4</name><description>Pause time minus 4 slot times</description><value>0</value></enumeratedValue><enumeratedValue><name>PLT28</name><description>Pause time minus 28 slot times</description><value>1</value></enumeratedValue><enumeratedValue><name>PLT144</name><description>Pause time minus 144 slot times</description><value>2</value></enumeratedValue><enumeratedValue><name>PLT256</name><description>Pause time minus 256 slot times</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ZQPD</name>
<description>Zero-quanta pause disable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ZQPD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Normal operation with automatic zero-quanta pause control frame generation</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Automatic generation of zero-quanta pause control frames is disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PT</name>
<description>Pause time</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>MACVLANTR</name>
<displayName>MACVLANTR</displayName>
<description>Ethernet MAC VLAN tag register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VLANTI</name>
<description>VLAN tag identifier (for receive frames)</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
<field>
<name>VLANTC</name>
<description>12-bit VLAN tag comparison</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>VLANTC</name><usage>read-write</usage><enumeratedValue><name>VLANTC16</name><description>Full 16 bit VLAN identifiers are used for comparison and filtering</description><value>0</value></enumeratedValue><enumeratedValue><name>VLANTC12</name><description>12 bit VLAN identifies are used for comparison and filtering</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MACPMTCSR</name>
<displayName>MACPMTCSR</displayName>
<description>Ethernet MAC PMT control and status
register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PD</name>
<description>Power down</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MPE</name>
<description>Magic packet enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No power management event generated due to Magic Packet reception</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enable generation of a power management event due to Magic Packet reception</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WFE</name>
<description>Wakeup frame enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WFE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No power management event generated due to wakeup frame reception</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enable generation of a power management event due to wakeup frame reception</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MPR</name>
<description>Magic packet received</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WFR</name>
<description>Wakeup frame received</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GU</name>
<description>Global unicast</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>GU</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Normal operation</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Any unicast packet filtered by the MAC address recognition may be a wakeup frame</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WFFRPR</name>
<description>Wakeup frame filter register pointer reset</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WFFRPR</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset wakeup frame filter register point to 0b000. Automatically cleared</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MACDBGR</name>
<displayName>MACDBGR</displayName>
<description>Ethernet MAC debug register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>TFF</name><description>Tx FIFO full</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field>
<field><name>TFNE</name><description>Tx FIFO not empty</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field>
<field><name>TFWA</name><description>Tx FIFO write active</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field>
<field><name>TFRS</name><description>Tx FIFO read status</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field>
<field><name>MTP</name><description>MAC transmitter in pause</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field>
<field><name>MTFCS</name><description>MAC transmit frame controller status</description><bitOffset>17</bitOffset><bitWidth>2</bitWidth></field>
<field><name>MMTEA</name><description>MAC MII transmit engine active</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field>
<field><name>RFFL</name><description>Rx FIFO fill level</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field>
<field><name>RFRCS</name><description>Rx FIFO read controller status</description><bitOffset>5</bitOffset><bitWidth>2</bitWidth></field>
<field><name>RFWRA</name><description>Rx FIFO write controller active</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field>
<field><name>MSFRWCS</name><description>MAC small FIFO read/write controllers status</description><bitOffset>1</bitOffset><bitWidth>2</bitWidth></field>
<field><name>MMRPEA</name><description>MAC MII receive protocol engine active</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field>
</fields>
</register>
<register>
<name>MACSR</name>
<displayName>MACSR</displayName>
<description>Ethernet MAC interrupt status
register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PMTS</name>
<description>PMT status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MMCS</name>
<description>MMC status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MMCRS</name>
<description>MMC receive status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MMCTS</name>
<description>MMC transmit status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TSTS</name>
<description>Time stamp trigger status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MACIMR</name>
<displayName>MACIMR</displayName>
<description>Ethernet MAC interrupt mask
register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PMTIM</name>
<description>PMT interrupt mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PMTIM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>PMT Status interrupt generation enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>PMT Status interrupt generation disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TSTIM</name>
<description>Time stamp trigger interrupt mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TSTIM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Time stamp interrupt generation enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Time stamp interrupt generation disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MACA0HR</name>
<displayName>MACA0HR</displayName>
<description>Ethernet MAC address 0 high
register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<resetValue>0x0010FFFF</resetValue>
<fields>
<field>
<name>MACA0H</name>
<description>MAC address0 high</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
<field>
<name>MO</name>
<description>Always 1</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MACA0LR</name>
<displayName>MACA0LR</displayName>
<description>Ethernet MAC address 0 low
register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>MACA0L</name>
<description>0</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>MACA1HR</name>
<displayName>MACA1HR</displayName>
<description>Ethernet MAC address 1 high
register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>MACA1H</name>
<description>MACA1H</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
<field>
<name>MBC</name>
<description>MBC</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint>
</field>
<field>
<name>SA</name>
<description>SA</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SA</name><usage>read-write</usage><enumeratedValue><name>Destination</name><description>This address is used for comparison with DA fields of the received frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Source</name><description>This address is used for comparison with SA fields of received frames</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AE</name>
<description>AE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>AE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Address filters ignore this address</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address filters use this address</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MACA1LR</name>
<displayName>MACA1LR</displayName>
<description>Ethernet MAC address1 low
register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>MACA1L</name>
<description>MACA1LR</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>MACA2HR</name>
<displayName>MACA2HR</displayName>
<description>Ethernet MAC address 2 high
register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>MACA2H</name>
<description>MAC2AH</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
<field>
<name>MBC</name>
<description>MBC</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint>
</field>
<field>
<name>SA</name>
<description>SA</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SA</name><usage>read-write</usage><enumeratedValue><name>Destination</name><description>This address is used for comparison with DA fields of the received frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Source</name><description>This address is used for comparison with SA fields of received frames</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AE</name>
<description>AE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>AE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Address filters ignore this address</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address filters use this address</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MACA2LR</name>
<displayName>MACA2LR</displayName>
<description>Ethernet MAC address 2 low
register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>MACA2L</name>
<description>MACA2L</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>MACA3HR</name>
<displayName>MACA3HR</displayName>
<description>Ethernet MAC address 3 high
register</description>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000FFFF</resetValue>
<fields>
<field>
<name>MACA3H</name>
<description>MACA3H</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint>
</field>
<field>
<name>MBC</name>
<description>MBC</description>
<bitOffset>24</bitOffset>
<bitWidth>6</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint>
</field>
<field>
<name>SA</name>
<description>SA</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SA</name><usage>read-write</usage><enumeratedValue><name>Destination</name><description>This address is used for comparison with DA fields of the received frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Source</name><description>This address is used for comparison with SA fields of received frames</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AE</name>
<description>AE</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>AE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Address filters ignore this address</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address filters use this address</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MACA3LR</name>
<displayName>MACA3LR</displayName>
<description>Ethernet MAC address 3 low
register</description>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>MACA3L</name>
<description>MBCA3L</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>Ethernet_MMC</name>
<description>Ethernet: MAC management counters</description>
<groupName>Ethernet</groupName>
<baseAddress>0x40028100</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>MMCCR</name>
<displayName>MMCCR</displayName>
<description>Ethernet MMC control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CR</name>
<description>Counter reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CR</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset all counters. Cleared automatically</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CSR</name>
<description>Counter stop rollover</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CSR</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counters roll over to zero after reaching the maximum value</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counters do not roll over to zero after reaching the maximum value</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ROR</name>
<description>Reset on read</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ROR</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MMC counters do not reset on read</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MMC counters reset to zero after read</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MCF</name>
<description>MMC counter freeze</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MCF</name><usage>read-write</usage><enumeratedValue><name>Unfrozen</name><description>All MMC counters update normally</description><value>0</value></enumeratedValue><enumeratedValue><name>Frozen</name><description>All MMC counters frozen to their current value</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MCP</name>
<description>MMC counter preset</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MCP</name><usage>read-write</usage><enumeratedValue><name>Preset</name><description>MMC counters will be preset to almost full or almost half. Cleared automatically</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MCFHP</name>
<description>MMC counter Full-Half preset</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MCFHP</name><usage>read-write</usage><enumeratedValue><name>AlmostHalf</name><description>When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AlmostFull</name><description>When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MMCRIR</name>
<displayName>MMCRIR</displayName>
<description>Ethernet MMC receive interrupt
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RFCES</name>
<description>Received frames CRC error status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RFAES</name>
<description>Received frames alignment error status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RGUFS</name>
<description>Received good Unicast frames status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMCTIR</name>
<displayName>MMCTIR</displayName>
<description>Ethernet MMC transmit interrupt
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TGFSCS</name>
<description>Transmitted good frames single collision status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TGFMSCS</name>
<description>Transmitted good frames more than single collision status</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TGFS</name>
<description>Transmitted good frames status</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMCRIMR</name>
<displayName>MMCRIMR</displayName>
<description>Ethernet MMC receive interrupt mask
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RFCEM</name>
<description>Received frame CRC error mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RFCEM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Received-crc-error counter half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Received-crc-error counter half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RFAEM</name>
<description>Received frames alignment error mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RFAEM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Received-alignment-error counter half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Received-alignment-error counter half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RGUFM</name>
<description>Received good Unicast frames mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RGUFM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Received-good-unicast counter half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Received-good-unicast counter half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MMCTIMR</name>
<displayName>MMCTIMR</displayName>
<description>Ethernet MMC transmit interrupt mask
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TGFSCM</name>
<description>Transmitted good frames single collision mask</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TGFSCM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Transmitted-good-single-collision half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Transmitted-good-single-collision half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TGFMSCM</name>
<description>Transmitted good frames more than single collision mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TGFMSCM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Transmitted-good-multiple-collision half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Transmitted-good-multiple-collision half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TGFM</name>
<description>Transmitted good frames mask</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TGFM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Transmitted-good counter half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Transmitted-good counter half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>MMCTGFSCCR</name>
<displayName>MMCTGFSCCR</displayName>
<description>Ethernet MMC transmitted good frames after a
single collision counter</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TGFSCC</name>
<description>Transmitted good frames single collision counter</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMCTGFMSCCR</name>
<displayName>MMCTGFMSCCR</displayName>
<description>Ethernet MMC transmitted good frames after
more than a single collision</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TGFMSCC</name>
<description>TGFMSCC</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMCTGFCR</name>
<displayName>MMCTGFCR</displayName>
<description>Ethernet MMC transmitted good frames counter
register</description>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TGFC</name>
<description>HTL</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMCRFCECR</name>
<displayName>MMCRFCECR</displayName>
<description>Ethernet MMC received frames with CRC error
counter register</description>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RFCFC</name>
<description>RFCFC</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMCRFAECR</name>
<displayName>MMCRFAECR</displayName>
<description>Ethernet MMC received frames with alignment
error counter register</description>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RFAEC</name>
<description>RFAEC</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMCRGUFCR</name>
<displayName>MMCRGUFCR</displayName>
<description>MMC received good unicast frames counter
register</description>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RGUFC</name>
<description>RGUFC</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>Ethernet_PTP</name>
<description>Ethernet: Precision time protocol</description>
<groupName>Ethernet</groupName>
<baseAddress>0x40028700</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PTPTSCR</name>
<displayName>PTPTSCR</displayName>
<description>Ethernet PTP time stamp control
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00002000</resetValue>
<fields>
<field>
<name>TSE</name>
<description>TSE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSFCU</name>
<description>TSFCU</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSPTPPSV2E</name>
<description>TSPTPPSV2E</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSSPTPOEFE</name>
<description>TSSPTPOEFE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSSIPV6FE</name>
<description>TSSIPV6FE</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSSIPV4FE</name>
<description>TSSIPV4FE</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSSEME</name>
<description>TSSEME</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSSMRME</name>
<description>TSSMRME</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSCNT</name>
<description>TSCNT</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TSPFFMAE</name>
<description>TSPFFMAE</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSSTI</name>
<description>TSSTI</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSSTU</name>
<description>TSSTU</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSITE</name>
<description>TSITE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TTSARU</name>
<description>TTSARU</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSSARFE</name>
<description>TSSARFE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSSSR</name>
<description>TSSSR</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PTPSSIR</name>
<displayName>PTPSSIR</displayName>
<description>Ethernet PTP subsecond increment
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STSSI</name>
<description>STSSI</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PTPTSHR</name>
<displayName>PTPTSHR</displayName>
<description>Ethernet PTP time stamp high
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STS</name>
<description>STS</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PTPTSLR</name>
<displayName>PTPTSLR</displayName>
<description>Ethernet PTP time stamp low
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STSS</name>
<description>STSS</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
</field>
<field>
<name>STPNS</name>
<description>STPNS</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PTPTSHUR</name>
<displayName>PTPTSHUR</displayName>
<description>Ethernet PTP time stamp high update
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSUS</name>
<description>TSUS</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PTPTSLUR</name>
<displayName>PTPTSLUR</displayName>
<description>Ethernet PTP time stamp low update
register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSUSS</name>
<description>TSUSS</description>
<bitOffset>0</bitOffset>
<bitWidth>31</bitWidth>
</field>
<field>
<name>TSUPNS</name>
<description>TSUSS</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PTPTSAR</name>
<displayName>PTPTSAR</displayName>
<description>Ethernet PTP time stamp addend
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSA</name>
<description>TSA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PTPTTHR</name>
<displayName>PTPTTHR</displayName>
<description>Ethernet PTP target time high
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TTSH</name>
<description>0</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PTPTTLR</name>
<displayName>PTPTTLR</displayName>
<description>Ethernet PTP target time low
register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TTSL</name>
<description>TTSL</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PTPTSSR</name>
<displayName>PTPTSSR</displayName>
<description>Ethernet PTP time stamp status
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSSO</name>
<description>TSSO</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSTTR</name>
<description>TSTTR</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PTPPPSCR</name>
<displayName>PTPPPSCR</displayName>
<description>Ethernet PTP PPS control
register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSSO</name>
<description>TSSO</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSTTR</name>
<description>TSTTR</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>Ethernet_DMA</name>
<description>Ethernet: DMA controller operation</description>
<groupName>Ethernet</groupName>
<baseAddress>0x40029000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DMABMR</name>
<displayName>DMABMR</displayName>
<description>Ethernet DMA bus mode register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00002101</resetValue>
<fields>
<field>
<name>SR</name>
<description>Software reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SR</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset all MAC subsystem internal registers and logic. Cleared automatically</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DA</name>
<description>DMA arbitration</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DA</name><usage>read-write</usage><enumeratedValue><name>RoundRobin</name><description>Round-robin with Rx:Tx priority given by PM</description><value>0</value></enumeratedValue><enumeratedValue><name>RxPriority</name><description>Rx has priority over Tx</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DSL</name>
<description>Descriptor skip length</description>
<bitOffset>2</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint>
</field>
<field>
<name>EDFE</name>
<description>Enhanced descriptor format enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EDFE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Normal descriptor format</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PBL</name>
<description>Programmable burst length</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
<enumeratedValues><name>PBL</name><usage>read-write</usage><enumeratedValue><name>PBL1</name><description>Maximum of 1 beat per DMA transaction</description><value>1</value></enumeratedValue><enumeratedValue><name>PBL2</name><description>Maximum of 2 beats per DMA transaction</description><value>2</value></enumeratedValue><enumeratedValue><name>PBL4</name><description>Maximum of 4 beats per DMA transaction</description><value>4</value></enumeratedValue><enumeratedValue><name>PBL8</name><description>Maximum of 8 beats per DMA transaction</description><value>8</value></enumeratedValue><enumeratedValue><name>PBL16</name><description>Maximum of 16 beats per DMA transaction</description><value>16</value></enumeratedValue><enumeratedValue><name>PBL32</name><description>Maximum of 32 beats per DMA transaction</description><value>32</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PM</name>
<description>Rx-Tx priority ratio</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PM</name><usage>read-write</usage><enumeratedValue><name>OneToOne</name><description>RxDMA priority over TxDMA is 1:1</description><value>0</value></enumeratedValue><enumeratedValue><name>TwoToOne</name><description>RxDMA priority over TxDMA is 2:1</description><value>1</value></enumeratedValue><enumeratedValue><name>ThreeToOne</name><description>RxDMA priority over TxDMA is 3:1</description><value>2</value></enumeratedValue><enumeratedValue><name>FourToOne</name><description>RxDMA priority over TxDMA is 4:1</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FB</name>
<description>Fixed burst</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FB</name><usage>read-write</usage><enumeratedValue><name>Variable</name><description>AHB uses SINGLE and INCR burst transfers</description><value>0</value></enumeratedValue><enumeratedValue><name>Fixed</name><description>AHB uses only fixed burst transfers</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RDP</name>
<description>Rx DMA PBL</description>
<bitOffset>17</bitOffset>
<bitWidth>6</bitWidth>
<enumeratedValues><name>RDP</name><usage>read-write</usage><enumeratedValue><name>RDP1</name><description>1 beat per RxDMA transaction</description><value>1</value></enumeratedValue><enumeratedValue><name>RDP2</name><description>2 beats per RxDMA transaction</description><value>2</value></enumeratedValue><enumeratedValue><name>RDP4</name><description>4 beats per RxDMA transaction</description><value>4</value></enumeratedValue><enumeratedValue><name>RDP8</name><description>8 beats per RxDMA transaction</description><value>8</value></enumeratedValue><enumeratedValue><name>RDP16</name><description>16 beats per RxDMA transaction</description><value>16</value></enumeratedValue><enumeratedValue><name>RDP32</name><description>32 beats per RxDMA transaction</description><value>32</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>USP</name>
<description>Use separate PBL</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>USP</name><usage>read-write</usage><enumeratedValue><name>Combined</name><description>PBL value used for both Rx and Tx DMA</description><value>0</value></enumeratedValue><enumeratedValue><name>Separate</name><description>RxDMA uses RDP value, TxDMA uses PBL value</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FPM</name>
<description>4xPBL mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FPM</name><usage>read-write</usage><enumeratedValue><name>x1</name><description>PBL values used as-is</description><value>0</value></enumeratedValue><enumeratedValue><name>x4</name><description>PBL values multiplied by 4</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AAB</name>
<description>Address-aligned beats</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>AAB</name><usage>read-write</usage><enumeratedValue><name>Unaligned</name><description>Bursts are not aligned</description><value>0</value></enumeratedValue><enumeratedValue><name>Aligned</name><description>Align bursts to start address LS bits. First burst alignment depends on FB bit</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MB</name>
<description>Mixed burst</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MB</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below</description><value>0</value></enumeratedValue><enumeratedValue><name>Mixed</name><description>If FB is low, start all bursts greater than 16 with INCR (undefined burst)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DMATPDR</name>
<displayName>DMATPDR</displayName>
<description>Ethernet DMA transmit poll demand
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TPD</name>
<description>Transmit poll demand</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<enumeratedValues><name>TPD</name><usage>read-write</usage><enumeratedValue><name>Poll</name><description>Poll the transmit descriptor list</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DMARPDR</name>
<displayName>DMARPDR</displayName>
<description>EHERNET DMA receive poll demand
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RPD</name>
<description>Receive poll demand</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<enumeratedValues><name>RPD</name><usage>read-write</usage><enumeratedValue><name>Poll</name><description>Poll the receive descriptor list</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DMARDLAR</name>
<displayName>DMARDLAR</displayName>
<description>Ethernet DMA receive descriptor list address
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SRL</name>
<description>Start of receive list</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMATDLAR</name>
<displayName>DMATDLAR</displayName>
<description>Ethernet DMA transmit descriptor list
address register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STL</name>
<description>Start of transmit list</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMASR</name>
<displayName>DMASR</displayName>
<description>Ethernet DMA status register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TS</name>
<description>Transmit status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TPSS</name>
<description>Transmit process stopped status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TBUS</name>
<description>Transmit buffer unavailable status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TJTS</name>
<description>Transmit jabber timeout status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ROS</name>
<description>Receive overflow status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TUS</name>
<description>Transmit underflow status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RS</name>
<description>Receive status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RBUS</name>
<description>Receive buffer unavailable status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RPSS</name>
<description>Receive process stopped status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWTS</name>
<description>PWTS</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ETS</name>
<description>Early transmit status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FBES</name>
<description>Fatal bus error status</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ERS</name>
<description>Early receive status</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AIS</name>
<description>Abnormal interrupt summary</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NIS</name>
<description>Normal interrupt summary</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RPS</name>
<description>Receive process state</description>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues><name>RPS</name><usage>read-write</usage><enumeratedValue><name>Stopped</name><description>Stopped, reset or Stop Receive command issued</description><value>0</value></enumeratedValue><enumeratedValue><name>RunningFetching</name><description>Running, fetching receive transfer descriptor</description><value>1</value></enumeratedValue><enumeratedValue><name>RunningWaiting</name><description>Running, waiting for receive packet</description><value>3</value></enumeratedValue><enumeratedValue><name>Suspended</name><description>Suspended, receive descriptor unavailable</description><value>4</value></enumeratedValue><enumeratedValue><name>RunningWriting</name><description>Running, writing data to host memory buffer</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TPS</name>
<description>Transmit process state</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
<enumeratedValues><name>TPS</name><usage>read-write</usage><enumeratedValue><name>Stopped</name><description>Stopped, Reset or Stop Transmit command issued</description><value>0</value></enumeratedValue><enumeratedValue><name>RunningFetching</name><description>Running, fetching transmit transfer descriptor</description><value>1</value></enumeratedValue><enumeratedValue><name>RunningWaiting</name><description>Running, waiting for status</description><value>2</value></enumeratedValue><enumeratedValue><name>RunningReading</name><description>Running, reading data from host memory buffer</description><value>3</value></enumeratedValue><enumeratedValue><name>Suspended</name><description>Suspended, transmit descriptor unavailable or transmit buffer underflow</description><value>6</value></enumeratedValue><enumeratedValue><name>Running</name><description>Running, closing transmit descriptor</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EBS</name>
<description>Error bits status</description>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MMCS</name>
<description>MMC status</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PMTS</name>
<description>PMT status</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TSTS</name>
<description>Time stamp trigger status</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>DMAOMR</name>
<displayName>DMAOMR</displayName>
<description>Ethernet DMA operation mode
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SR</name>
<description>Start/stop receive</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SR</name><usage>read-write</usage><enumeratedValue><name>Stopped</name><description>Reception is stopped after transfer of the current frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Reception is placed in the Running state</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OSF</name>
<description>Operate on second frame</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTC</name>
<description>Receive threshold control</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>RTC</name><usage>read-write</usage><enumeratedValue><name>RTC64</name><description>64 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>RTC32</name><description>32 bytes</description><value>1</value></enumeratedValue><enumeratedValue><name>RTC96</name><description>96 bytes</description><value>2</value></enumeratedValue><enumeratedValue><name>RTC128</name><description>128 bytes</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FUGF</name>
<description>Forward undersized good frames</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FUGF</name><usage>read-write</usage><enumeratedValue><name>Drop</name><description>Rx FIFO drops all frames of less than 64 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>Forward</name><description>Rx FIFO forwards undersized frames</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FEF</name>
<description>Forward error frames</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FEF</name><usage>read-write</usage><enumeratedValue><name>Drop</name><description>Rx FIFO drops frames with error status</description><value>0</value></enumeratedValue><enumeratedValue><name>Forward</name><description>All frames except runt error frames are forwarded to the DMA</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ST</name>
<description>Start/stop transmission</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ST</name><usage>read-write</usage><enumeratedValue><name>Stopped</name><description>Transmission is placed in the Stopped state</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Transmission is placed in Running state</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TTC</name>
<description>Transmit threshold control</description>
<bitOffset>14</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>TTC</name><usage>read-write</usage><enumeratedValue><name>TTC64</name><description>64 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>TTC128</name><description>128 bytes</description><value>1</value></enumeratedValue><enumeratedValue><name>TTC192</name><description>192 bytes</description><value>2</value></enumeratedValue><enumeratedValue><name>TTC256</name><description>256 bytes</description><value>3</value></enumeratedValue><enumeratedValue><name>TTC40</name><description>40 bytes</description><value>4</value></enumeratedValue><enumeratedValue><name>TTC32</name><description>32 bytes</description><value>5</value></enumeratedValue><enumeratedValue><name>TTC24</name><description>24 bytes</description><value>6</value></enumeratedValue><enumeratedValue><name>TTC16</name><description>16 bytes</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FTF</name>
<description>Flush transmit FIFO</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FTF</name><usage>read-write</usage><enumeratedValue><name>Flush</name><description>Transmit FIFO controller logic is reset to its default values. Cleared automatically</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TSF</name>
<description>Transmit store and forward</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TSF</name><usage>read-write</usage><enumeratedValue><name>CutThrough</name><description>Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold</description><value>0</value></enumeratedValue><enumeratedValue><name>StoreForward</name><description>Transmission starts when a full frame is in the Tx FIFO</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DFRF</name>
<description>Disable flushing of received frames</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSF</name>
<description>Receive store and forward</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RSF</name><usage>read-write</usage><enumeratedValue><name>CutThrough</name><description>Rx FIFO operates in cut-through mode, subject to RTC bits</description><value>0</value></enumeratedValue><enumeratedValue><name>StoreForward</name><description>Frames are read from Rx FIFO after complete frame has been written</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DTCEFD</name>
<description>Dropping of TCP/IP checksum error frames disable</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DTCEFD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Drop frames with errors only in the receive checksum offload engine</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Do not drop frames that only have errors in the receive checksum offload engine</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DMAIER</name>
<displayName>DMAIER</displayName>
<description>Ethernet DMA interrupt enable
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIE</name>
<description>Transmit interrupt enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TPSIE</name>
<description>Transmit process stopped interrupt enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TBUIE</name>
<description>Transmit buffer unavailable interrupt enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TJTIE</name>
<description>Transmit jabber timeout interrupt enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROIE</name>
<description>Receive overflow interrupt enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TUIE</name>
<description>Transmit underflow interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RIE</name>
<description>Receive interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RBUIE</name>
<description>Receive buffer unavailable interrupt enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RPSIE</name>
<description>Receive process stopped interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RWTIE</name>
<description>Receive watchdog timeout interrupt enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ETIE</name>
<description>Early transmit interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBEIE</name>
<description>Fatal bus error interrupt enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERIE</name>
<description>Early receive interrupt enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AISE</name>
<description>Abnormal interrupt summary enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NISE</name>
<description>Normal interrupt summary enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMAMFBOCR</name>
<displayName>DMAMFBOCR</displayName>
<description>Ethernet DMA missed frame and buffer
overflow counter register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MFC</name>
<description>Missed frames by the controller</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>OMFC</name>
<description>Overflow bit for missed frame counter</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MFA</name>
<description>Missed frames by the application</description>
<bitOffset>17</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>OFOC</name>
<description>Overflow bit for FIFO overflow counter</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMARSWTR</name>
<displayName>DMARSWTR</displayName>
<description>Ethernet DMA receive status watchdog timer
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RSWTC</name>
<description>Receive status watchdog timer count</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DMACHTDR</name>
<displayName>DMACHTDR</displayName>
<description>Ethernet DMA current host transmit
descriptor register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HTDAP</name>
<description>Host transmit descriptor address pointer</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMACHRDR</name>
<displayName>DMACHRDR</displayName>
<description>Ethernet DMA current host receive descriptor
register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HRDAP</name>
<description>Host receive descriptor address pointer</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMACHTBAR</name>
<displayName>DMACHTBAR</displayName>
<description>Ethernet DMA current host transmit buffer
address register</description>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HTBAP</name>
<description>Host transmit buffer address pointer</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMACHRBAR</name>
<displayName>DMACHRBAR</displayName>
<description>Ethernet DMA current host receive buffer
address register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HRBAP</name>
<description>Host receive buffer address pointer</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CRC</name>
<description>Cryptographic processor</description>
<groupName>CRC</groupName>
<baseAddress>0x40023000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>Data register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>DR</name>
<description>Data Register</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>IDR</name>
<displayName>IDR</displayName>
<description>Independent Data register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDR</name>
<description>Independent Data register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RESET</name>
<description>Control regidter</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RESETW</name><usage>write</usage><enumeratedValue><name>Reset</name><description>Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OTG_FS_GLOBAL</name>
<description>USB on the go full speed</description>
<groupName>USB_OTG_FS</groupName>
<baseAddress>0x50000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>OTG_FS_WKUP</name>
<description>USB On-The-Go FS Wakeup through EXTI line
interrupt</description>
<value>42</value>
</interrupt>
<interrupt>
<name>OTG_FS_WKUP</name>
<description>USB On-The-Go FS Wakeup through EXTI line
interrupt</description>
<value>42</value>
</interrupt>
<interrupt>
<name>OTG_FS</name>
<description>USB On The Go FS global
interrupt</description>
<value>67</value>
</interrupt>
<interrupt>
<name>OTG_FS</name>
<description>USB On The Go FS global
interrupt</description>
<value>67</value>
</interrupt>
<registers>
<register>
<name>GOTGCTL</name>
<displayName>GOTGCTL</displayName>
<description>OTG_FS control and status register
(OTG_FS_GOTGCTL)</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000800</resetValue>
<fields>
<field>
<name>SRQSCS</name>
<description>Session request success</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SRQ</name>
<description>Session request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HNGSCS</name>
<description>Host negotiation success</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HNPRQ</name>
<description>HNP request</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSHNPEN</name>
<description>Host set HNP enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DHNPEN</name>
<description>Device HNP enabled</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CIDSTS</name>
<description>Connector ID status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DBCT</name>
<description>Long/short debounce time</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ASVLD</name>
<description>A-session valid</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BSVLD</name>
<description>B-session valid</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GOTGINT</name>
<displayName>GOTGINT</displayName>
<description>OTG_FS interrupt register
(OTG_FS_GOTGINT)</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEDET</name>
<description>Session end detected</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRSSCHG</name>
<description>Session request success status
change</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HNSSCHG</name>
<description>Host negotiation success status
change</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HNGDET</name>
<description>Host negotiation detected</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADTOCHG</name>
<description>A-device timeout change</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBCDNE</name>
<description>Debounce done</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GAHBCFG</name>
<displayName>GAHBCFG</displayName>
<description>OTG_FS AHB configuration register
(OTG_FS_GAHBCFG)</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GINT</name>
<description>Global interrupt mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFELVL</name>
<description>TxFIFO empty level</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTXFELVL</name>
<description>Periodic TxFIFO empty
level</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GUSBCFG</name>
<displayName>GUSBCFG</displayName>
<description>OTG_FS USB configuration register
(OTG_FS_GUSBCFG)</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000A00</resetValue>
<fields>
<field>
<name>TOCAL</name>
<description>FS timeout calibration</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PHYSEL</name>
<description>Full Speed serial transceiver
select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SRPCAP</name>
<description>SRP-capable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HNPCAP</name>
<description>HNP-capable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRDT</name>
<description>USB turnaround time</description>
<bitOffset>10</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FHMOD</name>
<description>Force host mode</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FDMOD</name>
<description>Force device mode</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTXPKT</name>
<description>Corrupt Tx packet</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GRSTCTL</name>
<displayName>GRSTCTL</displayName>
<description>OTG_FS reset register
(OTG_FS_GRSTCTL)</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>CSRST</name>
<description>Core soft reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSRST</name>
<description>HCLK soft reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FCRST</name>
<description>Host frame counter reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXFFLSH</name>
<description>RxFIFO flush</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFFLSH</name>
<description>TxFIFO flush</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AHBIDL</name>
<description>AHB master idle</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GINTSTS</name>
<displayName>GINTSTS</displayName>
<description>OTG_FS core interrupt register
(OTG_FS_GINTSTS)</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<resetValue>0x04000020</resetValue>
<fields>
<field>
<name>CMOD</name>
<description>Current mode of operation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MMIS</name>
<description>Mode mismatch interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OTGINT</name>
<description>OTG interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SOF</name>
<description>Start of frame</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXFLVL</name>
<description>RxFIFO non-empty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NPTXFE</name>
<description>Non-periodic TxFIFO empty</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>GINAKEFF</name>
<description>Global IN non-periodic NAK
effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>GOUTNAKEFF</name>
<description>Global OUT NAK effective</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ESUSP</name>
<description>Early suspend</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBSUSP</name>
<description>USB suspend</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBRST</name>
<description>USB reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ENUMDNE</name>
<description>Enumeration done</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ISOODRP</name>
<description>Isochronous OUT packet dropped
interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EOPF</name>
<description>End of periodic frame
interrupt</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEPINT</name>
<description>IN endpoint interrupt</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OEPINT</name>
<description>OUT endpoint interrupt</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IISOIXFR</name>
<description>Incomplete isochronous IN
transfer</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IPXFR_INCOMPISOOUT</name>
<description>Incomplete periodic transfer(Host
mode)/Incomplete isochronous OUT transfer(Device
mode)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HPRTINT</name>
<description>Host port interrupt</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HCINT</name>
<description>Host channels interrupt</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PTXFE</name>
<description>Periodic TxFIFO empty</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CIDSCHG</name>
<description>Connector ID status change</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DISCINT</name>
<description>Disconnect detected
interrupt</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SRQINT</name>
<description>Session request/new session detected
interrupt</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WKUPINT</name>
<description>Resume/remote wakeup detected
interrupt</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GINTMSK</name>
<displayName>GINTMSK</displayName>
<description>OTG_FS interrupt mask register
(OTG_FS_GINTMSK)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MMISM</name>
<description>Mode mismatch interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OTGINT</name>
<description>OTG interrupt mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SOFM</name>
<description>Start of frame mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXFLVLM</name>
<description>Receive FIFO non-empty
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NPTXFEM</name>
<description>Non-periodic TxFIFO empty
mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GINAKEFFM</name>
<description>Global non-periodic IN NAK effective
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GONAKEFFM</name>
<description>Global OUT NAK effective
mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ESUSPM</name>
<description>Early suspend mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBSUSPM</name>
<description>USB suspend mask</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBRST</name>
<description>USB reset mask</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ENUMDNEM</name>
<description>Enumeration done mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ISOODRPM</name>
<description>Isochronous OUT packet dropped interrupt
mask</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EOPFM</name>
<description>End of periodic frame interrupt
mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPMISM</name>
<description>Endpoint mismatch interrupt
mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEPINT</name>
<description>IN endpoints interrupt
mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OEPINT</name>
<description>OUT endpoints interrupt
mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IISOIXFRM</name>
<description>Incomplete isochronous IN transfer
mask</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IPXFRM_IISOOXFRM</name>
<description>Incomplete periodic transfer mask(Host
mode)/Incomplete isochronous OUT transfer mask(Device
mode)</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRTIM</name>
<description>Host port interrupt mask</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HCIM</name>
<description>Host channels interrupt
mask</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTXFEM</name>
<description>Periodic TxFIFO empty mask</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CIDSCHGM</name>
<description>Connector ID status change
mask</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DISCINT</name>
<description>Disconnect detected interrupt
mask</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SRQIM</name>
<description>Session request/new session detected
interrupt mask</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WUIM</name>
<description>Resume/remote wakeup detected interrupt
mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GRXSTSR_Device</name>
<displayName>GRXSTSR_Device</displayName>
<description>OTG_FS Receive status debug read(Device
mode)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BCNT</name>
<description>Byte count</description>
<bitOffset>4</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTSTS</name>
<description>Packet status</description>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FRMNUM</name>
<description>Frame number</description>
<bitOffset>21</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GRXSTSR_Host</name>
<displayName>GRXSTSR_Host</displayName>
<description>OTG_FS Receive status debug
read(Hostmode)</description>
<alternateRegister>FS_GRXSTSR_Device</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BCNT</name>
<description>Byte count</description>
<bitOffset>4</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTSTS</name>
<description>Packet status</description>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FRMNUM</name>
<description>Frame number</description>
<bitOffset>21</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GRXFSIZ</name>
<displayName>GRXFSIZ</displayName>
<description>OTG_FS Receive FIFO size register
(OTG_FS_GRXFSIZ)</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>RXFD</name>
<description>RxFIFO depth</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPTXF0</name>
<displayName>DIEPTXF0</displayName>
<description>OTG_FS non-periodic transmit FIFO size
register (Device mode)</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>TX0FSA</name>
<description>Endpoint 0 transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TX0FD</name>
<description>Endpoint 0 TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>HNPTXFSIZ</name>
<displayName>HNPTXFSIZ</displayName>
<description>OTG_FS non-periodic transmit FIFO size
register (Host mode)</description>
<alternateRegister>DIEPTXF0</alternateRegister>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>NPTXFSA</name>
<description>Non-periodic transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>NPTXFD</name>
<description>Non-periodic TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>GNPTXSTS</name>
<displayName>GNPTXSTS</displayName>
<description>OTG_FS non-periodic transmit FIFO/queue
status register (OTG_FS_GNPTXSTS)</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00080200</resetValue>
<fields>
<field>
<name>NPTXFSAV</name>
<description>Non-periodic TxFIFO space
available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>NPTQXSAV</name>
<description>Non-periodic transmit request queue
space available</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>NPTXQTOP</name>
<description>Top of the non-periodic transmit request
queue</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>GCCFG</name>
<displayName>GCCFG</displayName>
<description>OTG_FS general core configuration register
(OTG_FS_GCCFG)</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PWRDWN</name>
<description>Power down</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBUSASEN</name>
<description>Enable the VBUS sensing
device</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBUSBSEN</name>
<description>Enable the VBUS sensing
device</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOFOUTEN</name>
<description>SOF output enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CID</name>
<displayName>CID</displayName>
<description>core ID register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00001000</resetValue>
<fields>
<field>
<name>PRODUCT_ID</name>
<description>Product ID field</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HPTXFSIZ</name>
<displayName>HPTXFSIZ</displayName>
<description>OTG_FS Host periodic transmit FIFO size
register (OTG_FS_HPTXFSIZ)</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x02000600</resetValue>
<fields>
<field>
<name>PTXSA</name>
<description>Host periodic TxFIFO start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>PTXFSIZ</name>
<description>Host periodic TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<dim>3</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3</dimIndex><name>DIEPTXF%s</name>
<displayName>DIEPTXF1</displayName>
<description>OTG_FS device IN endpoint transmit FIFO size
register (OTG_FS_DIEPTXF2)</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x02000400</resetValue>
<fields>
<field>
<name>INEPTXSA</name>
<description>IN endpoint FIFO2 transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>INEPTXFD</name>
<description>IN endpoint TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register><name>GRXSTSP_Device</name><description>OTG status read and pop (device mode)</description><addressOffset>32</addressOffset><size>32</size><access>read-only</access><resetValue>0</resetValue><fields><field><name>STSPHST</name><description>Status phase start</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field>
<field><name>FRMNUM</name><description>Frame number</description><bitOffset>21</bitOffset><bitWidth>4</bitWidth></field>
<field><name>PKTSTS</name><description>Packet status</description><bitOffset>17</bitOffset><bitWidth>4</bitWidth></field>
<field><name>DPID</name><description>Data PID</description><bitOffset>15</bitOffset><bitWidth>2</bitWidth></field>
<field><name>BCNT</name><description>Byte count</description><bitOffset>4</bitOffset><bitWidth>11</bitWidth></field>
<field><name>EPNUM</name><description>Endpoint number</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field>
</fields></register>
<register><name>GRXSTSP_Host</name><description>OTG status read and pop (host mode)</description><alternateRegister>GRXSTSP_Device</alternateRegister><addressOffset>32</addressOffset><size>32</size><access>read-only</access><resetValue>0</resetValue><fields><field><name>PKTSTS</name><description>Packet status</description><bitOffset>17</bitOffset><bitWidth>4</bitWidth></field>
<field><name>DPID</name><description>Data PID</description><bitOffset>15</bitOffset><bitWidth>2</bitWidth></field>
<field><name>BCNT</name><description>Byte count</description><bitOffset>4</bitOffset><bitWidth>11</bitWidth></field>
<field><name>CHNUM</name><description>Channel number</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field>
</fields></register>
</registers>
</peripheral>
<peripheral>
<name>OTG_FS_HOST</name>
<description>USB on the go full speed</description>
<groupName>USB_OTG_FS</groupName>
<baseAddress>0x50000400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>HCFG</name>
<displayName>HCFG</displayName>
<description>OTG_FS host configuration register
(OTG_FS_HCFG)</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FSLSPCS</name>
<description>FS/LS PHY clock select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FSLSS</name>
<description>FS- and LS-only support</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HFIR</name>
<displayName>HFIR</displayName>
<description>OTG_FS Host frame interval
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000EA60</resetValue>
<fields>
<field>
<name>FRIVL</name>
<description>Frame interval</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>HFNUM</name>
<displayName>HFNUM</displayName>
<description>OTG_FS host frame number/frame time
remaining register (OTG_FS_HFNUM)</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00003FFF</resetValue>
<fields>
<field>
<name>FRNUM</name>
<description>Frame number</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>FTREM</name>
<description>Frame time remaining</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>HPTXSTS</name>
<displayName>HPTXSTS</displayName>
<description>OTG_FS_Host periodic transmit FIFO/queue
status register (OTG_FS_HPTXSTS)</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x00080100</resetValue>
<fields>
<field>
<name>PTXFSAVL</name>
<description>Periodic transmit data FIFO space
available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTXQSAV</name>
<description>Periodic transmit request queue space
available</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PTXQTOP</name>
<description>Top of the periodic transmit request
queue</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HAINT</name>
<displayName>HAINT</displayName>
<description>OTG_FS Host all channels interrupt
register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HAINT</name>
<description>Channel interrupts</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>HAINTMSK</name>
<displayName>HAINTMSK</displayName>
<description>OTG_FS host all channels interrupt mask
register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HAINTM</name>
<description>Channel interrupt mask</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>HPRT</name>
<displayName>HPRT</displayName>
<description>OTG_FS host port control and status register
(OTG_FS_HPRT)</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCSTS</name>
<description>Port connect status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PCDET</name>
<description>Port connect detected</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PENA</name>
<description>Port enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PENCHNG</name>
<description>Port enable/disable change</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POCA</name>
<description>Port overcurrent active</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>POCCHNG</name>
<description>Port overcurrent change</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRES</name>
<description>Port resume</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PSUSP</name>
<description>Port suspend</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRST</name>
<description>Port reset</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLSTS</name>
<description>Port line status</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PPWR</name>
<description>Port power</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTCTL</name>
<description>Port test control</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PSPD</name>
<description>Port speed</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HCCHAR0</name>
<displayName>HCCHAR0</displayName>
<description>OTG_FS host channel-0 characteristics
register (OTG_FS_HCCHAR0)</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multicount</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR1</name>
<displayName>HCCHAR1</displayName>
<description>OTG_FS host channel-1 characteristics
register (OTG_FS_HCCHAR1)</description>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multicount</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR2</name>
<displayName>HCCHAR2</displayName>
<description>OTG_FS host channel-2 characteristics
register (OTG_FS_HCCHAR2)</description>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multicount</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR3</name>
<displayName>HCCHAR3</displayName>
<description>OTG_FS host channel-3 characteristics
register (OTG_FS_HCCHAR3)</description>
<addressOffset>0x160</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multicount</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR4</name>
<displayName>HCCHAR4</displayName>
<description>OTG_FS host channel-4 characteristics
register (OTG_FS_HCCHAR4)</description>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multicount</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR5</name>
<displayName>HCCHAR5</displayName>
<description>OTG_FS host channel-5 characteristics
register (OTG_FS_HCCHAR5)</description>
<addressOffset>0x1A0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multicount</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR6</name>
<displayName>HCCHAR6</displayName>
<description>OTG_FS host channel-6 characteristics
register (OTG_FS_HCCHAR6)</description>
<addressOffset>0x1C0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multicount</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR7</name>
<displayName>HCCHAR7</displayName>
<description>OTG_FS host channel-7 characteristics
register (OTG_FS_HCCHAR7)</description>
<addressOffset>0x1E0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multicount</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT0</name>
<displayName>HCINT0</displayName>
<description>OTG_FS host channel-0 interrupt register
(OTG_FS_HCINT0)</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT1</name>
<displayName>HCINT1</displayName>
<description>OTG_FS host channel-1 interrupt register
(OTG_FS_HCINT1)</description>
<addressOffset>0x128</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT2</name>
<displayName>HCINT2</displayName>
<description>OTG_FS host channel-2 interrupt register
(OTG_FS_HCINT2)</description>
<addressOffset>0x148</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT3</name>
<displayName>HCINT3</displayName>
<description>OTG_FS host channel-3 interrupt register
(OTG_FS_HCINT3)</description>
<addressOffset>0x168</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT4</name>
<displayName>HCINT4</displayName>
<description>OTG_FS host channel-4 interrupt register
(OTG_FS_HCINT4)</description>
<addressOffset>0x188</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT5</name>
<displayName>HCINT5</displayName>
<description>OTG_FS host channel-5 interrupt register
(OTG_FS_HCINT5)</description>
<addressOffset>0x1A8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT6</name>
<displayName>HCINT6</displayName>
<description>OTG_FS host channel-6 interrupt register
(OTG_FS_HCINT6)</description>
<addressOffset>0x1C8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT7</name>
<displayName>HCINT7</displayName>
<description>OTG_FS host channel-7 interrupt register
(OTG_FS_HCINT7)</description>
<addressOffset>0x1E8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK0</name>
<displayName>HCINTMSK0</displayName>
<description>OTG_FS host channel-0 mask register
(OTG_FS_HCINTMSK0)</description>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK1</name>
<displayName>HCINTMSK1</displayName>
<description>OTG_FS host channel-1 mask register
(OTG_FS_HCINTMSK1)</description>
<addressOffset>0x12C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK2</name>
<displayName>HCINTMSK2</displayName>
<description>OTG_FS host channel-2 mask register
(OTG_FS_HCINTMSK2)</description>
<addressOffset>0x14C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK3</name>
<displayName>HCINTMSK3</displayName>
<description>OTG_FS host channel-3 mask register
(OTG_FS_HCINTMSK3)</description>
<addressOffset>0x16C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK4</name>
<displayName>HCINTMSK4</displayName>
<description>OTG_FS host channel-4 mask register
(OTG_FS_HCINTMSK4)</description>
<addressOffset>0x18C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK5</name>
<displayName>HCINTMSK5</displayName>
<description>OTG_FS host channel-5 mask register
(OTG_FS_HCINTMSK5)</description>
<addressOffset>0x1AC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK6</name>
<displayName>HCINTMSK6</displayName>
<description>OTG_FS host channel-6 mask register
(OTG_FS_HCINTMSK6)</description>
<addressOffset>0x1CC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK7</name>
<displayName>HCINTMSK7</displayName>
<description>OTG_FS host channel-7 mask register
(OTG_FS_HCINTMSK7)</description>
<addressOffset>0x1EC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ0</name>
<displayName>HCTSIZ0</displayName>
<description>OTG_FS host channel-0 transfer size
register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ1</name>
<displayName>HCTSIZ1</displayName>
<description>OTG_FS host channel-1 transfer size
register</description>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ2</name>
<displayName>HCTSIZ2</displayName>
<description>OTG_FS host channel-2 transfer size
register</description>
<addressOffset>0x150</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ3</name>
<displayName>HCTSIZ3</displayName>
<description>OTG_FS host channel-3 transfer size
register</description>
<addressOffset>0x170</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ4</name>
<displayName>HCTSIZ4</displayName>
<description>OTG_FS host channel-x transfer size
register</description>
<addressOffset>0x190</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ5</name>
<displayName>HCTSIZ5</displayName>
<description>OTG_FS host channel-5 transfer size
register</description>
<addressOffset>0x1B0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ6</name>
<displayName>HCTSIZ6</displayName>
<description>OTG_FS host channel-6 transfer size
register</description>
<addressOffset>0x1D0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ7</name>
<displayName>HCTSIZ7</displayName>
<description>OTG_FS host channel-7 transfer size
register</description>
<addressOffset>0x1F0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OTG_FS_DEVICE</name>
<description>USB on the go full speed</description>
<groupName>USB_OTG_FS</groupName>
<baseAddress>0x50000800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DCFG</name>
<displayName>DCFG</displayName>
<description>OTG_FS device configuration register
(OTG_FS_DCFG)</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x02200000</resetValue>
<fields>
<field>
<name>DSPD</name>
<description>Device speed</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NZLSOHSK</name>
<description>Non-zero-length status OUT
handshake</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>4</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PFIVL</name>
<description>Periodic frame interval</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCTL</name>
<displayName>DCTL</displayName>
<description>OTG_FS device control register
(OTG_FS_DCTL)</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RWUSIG</name>
<description>Remote wakeup signaling</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SDIS</name>
<description>Soft disconnect</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GINSTS</name>
<description>Global IN NAK status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>GONSTS</name>
<description>Global OUT NAK status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TCTL</name>
<description>Test control</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SGINAK</name>
<description>Set global IN NAK</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CGINAK</name>
<description>Clear global IN NAK</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SGONAK</name>
<description>Set global OUT NAK</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CGONAK</name>
<description>Clear global OUT NAK</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POPRGDNE</name>
<description>Power-on programming done</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DSTS</name>
<displayName>DSTS</displayName>
<description>OTG_FS device status register
(OTG_FS_DSTS)</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>SUSPSTS</name>
<description>Suspend status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENUMSPD</name>
<description>Enumerated speed</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EERR</name>
<description>Erratic error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FNSOF</name>
<description>Frame number of the received
SOF</description>
<bitOffset>8</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPMSK</name>
<displayName>DIEPMSK</displayName>
<description>OTG_FS device IN endpoint common interrupt
mask register (OTG_FS_DIEPMSK)</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed interrupt
mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDM</name>
<description>Endpoint disabled interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOM</name>
<description>Timeout condition mask (Non-isochronous
endpoints)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITTXFEMSK</name>
<description>IN token received when TxFIFO empty
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INEPNMM</name>
<description>IN token received with EP mismatch
mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INEPNEM</name>
<description>IN endpoint NAK effective
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPMSK</name>
<displayName>DOEPMSK</displayName>
<description>OTG_FS device OUT endpoint common interrupt
mask register (OTG_FS_DOEPMSK)</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed interrupt
mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDM</name>
<description>Endpoint disabled interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUPM</name>
<description>SETUP phase done mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDM</name>
<description>OUT token received when endpoint
disabled mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAINT</name>
<displayName>DAINT</displayName>
<description>OTG_FS device all endpoints interrupt
register (OTG_FS_DAINT)</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IEPINT</name>
<description>IN endpoint interrupt bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>OEPINT</name>
<description>OUT endpoint interrupt
bits</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAINTMSK</name>
<displayName>DAINTMSK</displayName>
<description>OTG_FS all endpoints interrupt mask register
(OTG_FS_DAINTMSK)</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IEPM</name>
<description>IN EP interrupt mask bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>OEPM</name>
<description>OUT EP interrupt mask bits</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DVBUSDIS</name>
<displayName>DVBUSDIS</displayName>
<description>OTG_FS device VBUS discharge time
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000017D7</resetValue>
<fields>
<field>
<name>VBUSDT</name>
<description>Device VBUS discharge time</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DVBUSPULSE</name>
<displayName>DVBUSPULSE</displayName>
<description>OTG_FS device VBUS pulsing time
register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x000005B8</resetValue>
<fields>
<field>
<name>DVBUSP</name>
<description>Device VBUS pulsing time</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPEMPMSK</name>
<displayName>DIEPEMPMSK</displayName>
<description>OTG_FS device IN endpoint FIFO empty
interrupt mask register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INEPTXFEM</name>
<description>IN EP Tx FIFO empty interrupt mask
bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPCTL0</name>
<displayName>DIEPCTL0</displayName>
<description>OTG_FS device control IN endpoint 0 control
register (OTG_FS_DIEPCTL0)</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>STALL</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>3</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3</dimIndex><name>DIEPCTL%s</name>
<displayName>DIEPCTL1</displayName>
<description>OTG device endpoint-1 control
register</description>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EPENA</name>
<description>EPENA</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDIS</name>
<description>EPDIS</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SODDFRM_SD1PID</name>
<description>SODDFRM/SD1PID</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>SD0PID/SEVNFRM</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>SNAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CNAK</name>
<description>CNAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXFNUM</name>
<description>TXFNUM</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>STALL</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPTYP</name>
<description>EPTYP</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAKSTS</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>EONUM/DPID</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>USBAEP</name>
<description>USBAEP</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MPSIZ</name>
<description>MPSIZ</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DOEPCTL0</name>
<displayName>DOEPCTL0</displayName>
<description>device endpoint-0 control
register</description>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<resetValue>0x00008000</resetValue>
<fields>
<field>
<name>EPENA</name>
<description>EPENA</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>EPDIS</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SNAK</name>
<description>SNAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CNAK</name>
<description>CNAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>STALL</name>
<description>STALL</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SNPM</name>
<description>SNPM</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPTYP</name>
<description>EPTYP</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAKSTS</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>USBAEP</name>
<description>USBAEP</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MPSIZ</name>
<description>MPSIZ</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<dim>3</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3</dimIndex><name>DOEPCTL%s</name>
<displayName>DOEPCTL1</displayName>
<description>device endpoint-1 control
register</description>
<addressOffset>0x320</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EPENA</name>
<description>EPENA</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDIS</name>
<description>EPDIS</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SODDFRM</name>
<description>SODDFRM</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>SD0PID/SEVNFRM</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>SNAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CNAK</name>
<description>CNAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>STALL</name>
<description>STALL</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SNPM</name>
<description>SNPM</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPTYP</name>
<description>EPTYP</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAKSTS</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>EONUM/DPID</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>USBAEP</name>
<description>USBAEP</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MPSIZ</name>
<description>MPSIZ</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIEPINT0</name>
<displayName>DIEPINT0</displayName>
<description>device endpoint-x interrupt
register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>TXFE</name>
<description>TXFE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INEPNE</name>
<description>INEPNE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>ITTXFE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>TOC</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>EPDISD</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>XFRC</name>
<description>XFRC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIEPINT1</name>
<displayName>DIEPINT1</displayName>
<description>device endpoint-1 interrupt
register</description>
<addressOffset>0x128</addressOffset>
<size>0x20</size>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>TXFE</name>
<description>TXFE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INEPNE</name>
<description>INEPNE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>ITTXFE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>TOC</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>EPDISD</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>XFRC</name>
<description>XFRC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIEPINT2</name>
<displayName>DIEPINT2</displayName>
<description>device endpoint-2 interrupt
register</description>
<addressOffset>0x148</addressOffset>
<size>0x20</size>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>TXFE</name>
<description>TXFE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INEPNE</name>
<description>INEPNE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>ITTXFE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>TOC</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>EPDISD</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>XFRC</name>
<description>XFRC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIEPINT3</name>
<displayName>DIEPINT3</displayName>
<description>device endpoint-3 interrupt
register</description>
<addressOffset>0x168</addressOffset>
<size>0x20</size>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>TXFE</name>
<description>TXFE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INEPNE</name>
<description>INEPNE</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>ITTXFE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>TOC</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>EPDISD</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>XFRC</name>
<description>XFRC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DOEPINT0</name>
<displayName>DOEPINT0</displayName>
<description>device endpoint-0 interrupt
register</description>
<addressOffset>0x308</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>B2BSTUP</name>
<description>B2BSTUP</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OTEPDIS</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>STUP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>EPDISD</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XFRC</name>
<description>XFRC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPINT1</name>
<displayName>DOEPINT1</displayName>
<description>device endpoint-1 interrupt
register</description>
<addressOffset>0x328</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>B2BSTUP</name>
<description>B2BSTUP</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OTEPDIS</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>STUP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>EPDISD</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XFRC</name>
<description>XFRC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPINT2</name>
<displayName>DOEPINT2</displayName>
<description>device endpoint-2 interrupt
register</description>
<addressOffset>0x348</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>B2BSTUP</name>
<description>B2BSTUP</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OTEPDIS</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>STUP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>EPDISD</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XFRC</name>
<description>XFRC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPINT3</name>
<displayName>DOEPINT3</displayName>
<description>device endpoint-3 interrupt
register</description>
<addressOffset>0x368</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>B2BSTUP</name>
<description>B2BSTUP</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OTEPDIS</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>STUP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>EPDISD</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XFRC</name>
<description>XFRC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPTSIZ0</name>
<displayName>DIEPTSIZ0</displayName>
<description>device endpoint-0 transfer size
register</description>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPTSIZ0</name>
<displayName>DOEPTSIZ0</displayName>
<description>device OUT endpoint-0 transfer size
register</description>
<addressOffset>0x310</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STUPCNT</name>
<description>SETUP packet count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPTSIZ1</name>
<displayName>DIEPTSIZ1</displayName>
<description>device endpoint-1 transfer size
register</description>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCNT</name>
<description>Multi count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPTSIZ2</name>
<displayName>DIEPTSIZ2</displayName>
<description>device endpoint-2 transfer size
register</description>
<addressOffset>0x150</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCNT</name>
<description>Multi count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPTSIZ3</name>
<displayName>DIEPTSIZ3</displayName>
<description>device endpoint-3 transfer size
register</description>
<addressOffset>0x170</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MCNT</name>
<description>Multi count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTXFSTS0</name>
<displayName>DTXFSTS0</displayName>
<description>OTG_FS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTXFSTS1</name>
<displayName>DTXFSTS1</displayName>
<description>OTG_FS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x138</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTXFSTS2</name>
<displayName>DTXFSTS2</displayName>
<description>OTG_FS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x158</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTXFSTS3</name>
<displayName>DTXFSTS3</displayName>
<description>OTG_FS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x178</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPTSIZ1</name>
<displayName>DOEPTSIZ1</displayName>
<description>device OUT endpoint-1 transfer size
register</description>
<addressOffset>0x330</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXDPID_STUPCNT</name>
<description>Received data PID/SETUP packet
count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPTSIZ2</name>
<displayName>DOEPTSIZ2</displayName>
<description>device OUT endpoint-2 transfer size
register</description>
<addressOffset>0x350</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXDPID_STUPCNT</name>
<description>Received data PID/SETUP packet
count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPTSIZ3</name>
<displayName>DOEPTSIZ3</displayName>
<description>device OUT endpoint-3 transfer size
register</description>
<addressOffset>0x370</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXDPID_STUPCNT</name>
<description>Received data PID/SETUP packet
count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OTG_FS_PWRCLK</name>
<description>USB on the go full speed</description>
<groupName>USB_OTG_FS</groupName>
<baseAddress>0x50000E00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PCGCCTL</name>
<displayName>PCGCCTL</displayName>
<description>OTG_FS power and clock gating control
register (OTG_FS_PCGCCTL)</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STPPCLK</name>
<description>Stop PHY clock</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GATEHCLK</name>
<description>Gate HCLK</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PHYSUSP</name>
<description>PHY Suspended</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CAN1</name>
<description>Controller area network</description>
<groupName>CAN</groupName>
<baseAddress>0x40006400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CAN1_TX</name>
<description>CAN1 TX interrupts</description>
<value>19</value>
</interrupt>
<interrupt>
<name>CAN1_TX</name>
<description>CAN1 TX interrupts</description>
<value>19</value>
</interrupt>
<interrupt>
<name>CAN1_RX0</name>
<description>CAN1 RX0 interrupts</description>
<value>20</value>
</interrupt>
<interrupt>
<name>CAN1_RX0</name>
<description>CAN1 RX0 interrupts</description>
<value>20</value>
</interrupt>
<interrupt>
<name>CAN1_RX1</name>
<description>CAN1 RX1 interrupts</description>
<value>21</value>
</interrupt>
<interrupt>
<name>CAN1_RX1</name>
<description>CAN1 RX1 interrupts</description>
<value>21</value>
</interrupt>
<interrupt>
<name>CAN1_SCE</name>
<description>CAN1 SCE interrupt</description>
<value>22</value>
</interrupt>
<interrupt>
<name>CAN1_SCE</name>
<description>CAN1 SCE interrupt</description>
<value>22</value>
</interrupt>
<registers>
<cluster><dim>3</dim><dimIncrement>0x10</dimIncrement><dimIndex>0,1,2</dimIndex><name>TX%s</name><description>CAN Transmit cluster</description><addressOffset>0x180</addressOffset><register>
<name>TIR</name>
<displayName>TI0R</displayName>
<description>TX mailbox identifier register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STID</name>
<description>STID</description>
<bitOffset>21</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EXID</name>
<description>EXID</description>
<bitOffset>3</bitOffset>
<bitWidth>18</bitWidth>
</field>
<field>
<name>IDE</name>
<description>IDE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IDE</name><usage>read-write</usage><enumeratedValue><name>Standard</name><description>Standard identifier</description><value>0</value></enumeratedValue><enumeratedValue><name>Extended</name><description>Extended identifier</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RTR</name>
<description>RTR</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RTR</name><usage>read-write</usage><enumeratedValue><name>Data</name><description>Data frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Remote</name><description>Remote frame</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TXRQ</name>
<description>TXRQ</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDTR</name>
<displayName>TDT0R</displayName>
<description>mailbox data length control and time stamp
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME</name>
<description>TIME</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TGT</name>
<description>TGT</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DLC</name>
<description>DLC</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>8</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>TDLR</name>
<displayName>TDL0R</displayName>
<description>mailbox data low register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA3</name>
<description>DATA3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA2</name>
<description>DATA2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA1</name>
<description>DATA1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA0</name>
<description>DATA0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TDHR</name>
<displayName>TDH0R</displayName>
<description>mailbox data high register</description>
<addressOffset>0xc</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA7</name>
<description>DATA7</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA6</name>
<description>DATA6</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA5</name>
<description>DATA5</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA4</name>
<description>DATA4</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</cluster><cluster><dim>2</dim><dimIncrement>0x10</dimIncrement><dimIndex>0,1</dimIndex><name>RX%s</name><description>CAN Receive cluster</description><addressOffset>0x1b0</addressOffset><register>
<name>RIR</name>
<displayName>RI0R</displayName>
<description>receive FIFO mailbox identifier
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STID</name>
<description>STID</description>
<bitOffset>21</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EXID</name>
<description>EXID</description>
<bitOffset>3</bitOffset>
<bitWidth>18</bitWidth>
</field>
<field>
<name>IDE</name>
<description>IDE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IDE</name><usage>read-write</usage><enumeratedValue><name>Standard</name><description>Standard identifier</description><value>0</value></enumeratedValue><enumeratedValue><name>Extended</name><description>Extended identifier</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RTR</name>
<description>RTR</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RTR</name><usage>read-write</usage><enumeratedValue><name>Data</name><description>Data frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Remote</name><description>Remote frame</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RDTR</name>
<displayName>RDT0R</displayName>
<description>mailbox data high register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME</name>
<description>TIME</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>FMI</name>
<description>FMI</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DLC</name>
<description>DLC</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>8</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>RDLR</name>
<displayName>RDL0R</displayName>
<description>mailbox data high register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA3</name>
<description>DATA3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA2</name>
<description>DATA2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA1</name>
<description>DATA1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA0</name>
<description>DATA0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RDHR</name>
<displayName>RDH0R</displayName>
<description>receive FIFO mailbox data high
register</description>
<addressOffset>0xc</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA7</name>
<description>DATA7</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA6</name>
<description>DATA6</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA5</name>
<description>DATA5</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA4</name>
<description>DATA4</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</cluster><cluster><dim>28</dim><dimIncrement>0x8</dimIncrement><dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27</dimIndex><name>FB%s</name><description>CAN Filter Bank cluster</description><addressOffset>0x240</addressOffset><register>
<name>FR1</name>
<displayName>F0R1</displayName>
<description>Filter bank 0 register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>FB</name><description>Filter bits</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields>
</register>
<register>
<name>FR2</name>
<displayName>F0R2</displayName>
<description>Filter bank 0 register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>FB</name><description>Filter bits</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields>
</register>
</cluster><register>
<name>MCR</name>
<displayName>MCR</displayName>
<description>master control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00010002</resetValue>
<fields>
<field>
<name>DBF</name>
<description>DBF</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESET</name>
<description>RESET</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TTCM</name>
<description>TTCM</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABOM</name>
<description>ABOM</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AWUM</name>
<description>AWUM</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NART</name>
<description>NART</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RFLM</name>
<description>RFLM</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFP</name>
<description>TXFP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLEEP</name>
<description>SLEEP</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INRQ</name>
<description>INRQ</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MSR</name>
<displayName>MSR</displayName>
<description>master status register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000C02</resetValue>
<fields>
<field>
<name>RX</name>
<description>RX</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SAMP</name>
<description>SAMP</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXM</name>
<description>RXM</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXM</name>
<description>TXM</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SLAKI</name>
<description>SLAKI</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WKUI</name>
<description>WKUI</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ERRI</name>
<description>ERRI</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SLAK</name>
<description>SLAK</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>INAK</name>
<description>INAK</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>TSR</name>
<displayName>TSR</displayName>
<description>transmit status register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x1C000000</resetValue>
<fields>
<field>
<name>LOW2</name>
<description>Lowest priority flag for mailbox
2</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LOW1</name>
<description>Lowest priority flag for mailbox
1</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LOW0</name>
<description>Lowest priority flag for mailbox
0</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TME2</name>
<description>Lowest priority flag for mailbox
2</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TME1</name>
<description>Lowest priority flag for mailbox
1</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TME0</name>
<description>Lowest priority flag for mailbox
0</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CODE</name>
<description>CODE</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ABRQ2</name>
<description>ABRQ2</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TERR2</name>
<description>TERR2</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALST2</name>
<description>ALST2</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXOK2</name>
<description>TXOK2</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RQCP2</name>
<description>RQCP2</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ABRQ1</name>
<description>ABRQ1</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TERR1</name>
<description>TERR1</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALST1</name>
<description>ALST1</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXOK1</name>
<description>TXOK1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RQCP1</name>
<description>RQCP1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ABRQ0</name>
<description>ABRQ0</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TERR0</name>
<description>TERR0</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ALST0</name>
<description>ALST0</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXOK0</name>
<description>TXOK0</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RQCP0</name>
<description>RQCP0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>2</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1</dimIndex><name>RF%sR</name>
<displayName>RF0R</displayName>
<description>receive FIFO %s register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RFOM</name>
<description>RFOM0</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>RFOM0W</name><usage>write</usage><enumeratedValue><name>Release</name><description>Set by software to release the output mailbox of the FIFO</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FOVR</name>
<description>FOVR0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>FOVR0R</name><usage>read</usage><enumeratedValue><name>NoOverrun</name><description>No FIFO x overrun</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>FIFO x overrun</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>FOVR0W</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FULL</name>
<description>FULL0</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>FULL0R</name><usage>read</usage><enumeratedValue><name>NotFull</name><description>FIFO x is not full</description><value>0</value></enumeratedValue><enumeratedValue><name>Full</name><description>FIFO x is full</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>FULL0W</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FMP</name>
<description>FMP0</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>interrupt enable register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLKIE</name>
<description>SLKIE</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SLKIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when SLAKI bit is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when SLAKI bit is set</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WKUIE</name>
<description>WKUIE</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WKUIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when WKUI is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when WKUI bit is set</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ERRIE</name>
<description>ERRIE</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ERRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt will be generated when an error condition is pending in the CAN_ESR</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>An interrupt will be generation when an error condition is pending in the CAN_ESR</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LECIE</name>
<description>LECIE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LECIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BOFIE</name>
<description>BOFIE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>BOFIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ERRI bit will not be set when BOFF is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ERRI bit will be set when BOFF is set</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EPVIE</name>
<description>EPVIE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EPVIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ERRI bit will not be set when EPVF is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ERRI bit will be set when EPVF is set</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EWGIE</name>
<description>EWGIE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EWGIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ERRI bit will not be set when EWGF is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ERRI bit will be set when EWGF is set</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FOVIE1</name>
<description>FOVIE1</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FOVIE1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when FOVR is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generation when FOVR is set</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FFIE1</name>
<description>FFIE1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FFIE1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when FULL bit is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when FULL bit is set</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FMPIE1</name>
<description>FMPIE1</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FMPIE1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt generated when state of FMP[1:0] bits are not 00b</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when state of FMP[1:0] bits are not 00b</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FOVIE0</name>
<description>FOVIE0</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FOVIE0</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when FOVR bit is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when FOVR bit is set</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FFIE0</name>
<description>FFIE0</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FFIE0</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when FULL bit is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when FULL bit is set</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FMPIE0</name>
<description>FMPIE0</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FMPIE0</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt generated when state of FMP[1:0] bits are not 00</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when state of FMP[1:0] bits are not 00b</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TMEIE</name>
<description>TMEIE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TMEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when RQCPx bit is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when RQCPx bit is set</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ESR</name>
<displayName>ESR</displayName>
<description>interrupt enable register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REC</name>
<description>REC</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TEC</name>
<description>TEC</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LEC</name>
<description>LEC</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
<enumeratedValues><name>LEC</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No Error</description><value>0</value></enumeratedValue><enumeratedValue><name>Stuff</name><description>Stuff Error</description><value>1</value></enumeratedValue><enumeratedValue><name>Form</name><description>Form Error</description><value>2</value></enumeratedValue><enumeratedValue><name>Ack</name><description>Acknowledgment Error</description><value>3</value></enumeratedValue><enumeratedValue><name>BitRecessive</name><description>Bit recessive Error</description><value>4</value></enumeratedValue><enumeratedValue><name>BitDominant</name><description>Bit dominant Error</description><value>5</value></enumeratedValue><enumeratedValue><name>Crc</name><description>CRC Error</description><value>6</value></enumeratedValue><enumeratedValue><name>Custom</name><description>Set by software</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BOFF</name>
<description>BOFF</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPVF</name>
<description>EPVF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EWGF</name>
<description>EWGF</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>BTR</name>
<displayName>BTR</displayName>
<description>bit timing register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SILM</name>
<description>SILM</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SILM</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal operation</description><value>0</value></enumeratedValue><enumeratedValue><name>Silent</name><description>Silent Mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LBKM</name>
<description>LBKM</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LBKM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Loop Back Mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Loop Back Mode enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SJW</name>
<description>SJW</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TS2</name>
<description>TS2</description>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TS1</name>
<description>TS1</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BRP</name>
<description>BRP</description>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>FMR</name>
<displayName>FMR</displayName>
<description>filter master register</description>
<addressOffset>0x200</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x2A1C0E01</resetValue>
<fields>
<field>
<name>CAN2SB</name>
<description>CAN2SB</description>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>FINIT</name>
<description>FINIT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FM1R</name>
<displayName>FM1R</displayName>
<description>filter mode register</description>
<addressOffset>0x204</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FBM0</name>
<description>Filter mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM1</name>
<description>Filter mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM2</name>
<description>Filter mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM3</name>
<description>Filter mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM4</name>
<description>Filter mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM5</name>
<description>Filter mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM6</name>
<description>Filter mode</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM7</name>
<description>Filter mode</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM8</name>
<description>Filter mode</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM9</name>
<description>Filter mode</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM10</name>
<description>Filter mode</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM11</name>
<description>Filter mode</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM12</name>
<description>Filter mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM13</name>
<description>Filter mode</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM14</name>
<description>Filter mode</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM15</name>
<description>Filter mode</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM16</name>
<description>Filter mode</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM17</name>
<description>Filter mode</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM18</name>
<description>Filter mode</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM19</name>
<description>Filter mode</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM20</name>
<description>Filter mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM21</name>
<description>Filter mode</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM22</name>
<description>Filter mode</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM23</name>
<description>Filter mode</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM24</name>
<description>Filter mode</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM25</name>
<description>Filter mode</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM26</name>
<description>Filter mode</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FBM27</name>
<description>Filter mode</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FS1R</name>
<displayName>FS1R</displayName>
<description>filter scale register</description>
<addressOffset>0x20C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FSC0</name>
<description>Filter scale configuration</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC1</name>
<description>Filter scale configuration</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC2</name>
<description>Filter scale configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC3</name>
<description>Filter scale configuration</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC4</name>
<description>Filter scale configuration</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC5</name>
<description>Filter scale configuration</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC6</name>
<description>Filter scale configuration</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC7</name>
<description>Filter scale configuration</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC8</name>
<description>Filter scale configuration</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC9</name>
<description>Filter scale configuration</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC10</name>
<description>Filter scale configuration</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC11</name>
<description>Filter scale configuration</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC12</name>
<description>Filter scale configuration</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC13</name>
<description>Filter scale configuration</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC14</name>
<description>Filter scale configuration</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC15</name>
<description>Filter scale configuration</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC16</name>
<description>Filter scale configuration</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC17</name>
<description>Filter scale configuration</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC18</name>
<description>Filter scale configuration</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC19</name>
<description>Filter scale configuration</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC20</name>
<description>Filter scale configuration</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC21</name>
<description>Filter scale configuration</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC22</name>
<description>Filter scale configuration</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC23</name>
<description>Filter scale configuration</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC24</name>
<description>Filter scale configuration</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC25</name>
<description>Filter scale configuration</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC26</name>
<description>Filter scale configuration</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSC27</name>
<description>Filter scale configuration</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FFA1R</name>
<displayName>FFA1R</displayName>
<description>filter FIFO assignment
register</description>
<addressOffset>0x214</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FFA0</name>
<description>Filter FIFO assignment for filter
0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA1</name>
<description>Filter FIFO assignment for filter
1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA2</name>
<description>Filter FIFO assignment for filter
2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA3</name>
<description>Filter FIFO assignment for filter
3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA4</name>
<description>Filter FIFO assignment for filter
4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA5</name>
<description>Filter FIFO assignment for filter
5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA6</name>
<description>Filter FIFO assignment for filter
6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA7</name>
<description>Filter FIFO assignment for filter
7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA8</name>
<description>Filter FIFO assignment for filter
8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA9</name>
<description>Filter FIFO assignment for filter
9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA10</name>
<description>Filter FIFO assignment for filter
10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA11</name>
<description>Filter FIFO assignment for filter
11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA12</name>
<description>Filter FIFO assignment for filter
12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA13</name>
<description>Filter FIFO assignment for filter
13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA14</name>
<description>Filter FIFO assignment for filter
14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA15</name>
<description>Filter FIFO assignment for filter
15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA16</name>
<description>Filter FIFO assignment for filter
16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA17</name>
<description>Filter FIFO assignment for filter
17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA18</name>
<description>Filter FIFO assignment for filter
18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA19</name>
<description>Filter FIFO assignment for filter
19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA20</name>
<description>Filter FIFO assignment for filter
20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA21</name>
<description>Filter FIFO assignment for filter
21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA22</name>
<description>Filter FIFO assignment for filter
22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA23</name>
<description>Filter FIFO assignment for filter
23</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA24</name>
<description>Filter FIFO assignment for filter
24</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA25</name>
<description>Filter FIFO assignment for filter
25</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA26</name>
<description>Filter FIFO assignment for filter
26</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFA27</name>
<description>Filter FIFO assignment for filter
27</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FA1R</name>
<displayName>FA1R</displayName>
<description>filter activation register</description>
<addressOffset>0x21C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FACT0</name>
<description>Filter active</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT1</name>
<description>Filter active</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT2</name>
<description>Filter active</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT3</name>
<description>Filter active</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT4</name>
<description>Filter active</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT5</name>
<description>Filter active</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT6</name>
<description>Filter active</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT7</name>
<description>Filter active</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT8</name>
<description>Filter active</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT9</name>
<description>Filter active</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT10</name>
<description>Filter active</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT11</name>
<description>Filter active</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT12</name>
<description>Filter active</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT13</name>
<description>Filter active</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT14</name>
<description>Filter active</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT15</name>
<description>Filter active</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT16</name>
<description>Filter active</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT17</name>
<description>Filter active</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT18</name>
<description>Filter active</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT19</name>
<description>Filter active</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT20</name>
<description>Filter active</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT21</name>
<description>Filter active</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT22</name>
<description>Filter active</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT23</name>
<description>Filter active</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT24</name>
<description>Filter active</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT25</name>
<description>Filter active</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT26</name>
<description>Filter active</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FACT27</name>
<description>Filter active</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="CAN1">
<name>CAN2</name>
<baseAddress>0x40006800</baseAddress>
<interrupt>
<name>CAN2_TX</name>
<description>CAN2 TX interrupts</description>
<value>63</value>
</interrupt>
<interrupt>
<name>CAN2_TX</name>
<description>CAN2 TX interrupts</description>
<value>63</value>
</interrupt>
<interrupt>
<name>CAN2_RX0</name>
<description>CAN2 RX0 interrupts</description>
<value>64</value>
</interrupt>
<interrupt>
<name>CAN2_RX0</name>
<description>CAN2 RX0 interrupts</description>
<value>64</value>
</interrupt>
<interrupt>
<name>CAN2_RX1</name>
<description>CAN2 RX1 interrupts</description>
<value>65</value>
</interrupt>
<interrupt>
<name>CAN2_RX1</name>
<description>CAN2 RX1 interrupts</description>
<value>65</value>
</interrupt>
<interrupt>
<name>CAN2_SCE</name>
<description>CAN2 SCE interrupt</description>
<value>66</value>
</interrupt>
<interrupt>
<name>CAN2_SCE</name>
<description>CAN2 SCE interrupt</description>
<value>66</value>
</interrupt>
</peripheral>
<peripheral>
<name>NVIC</name>
<description>Nested Vectored Interrupt
Controller</description>
<groupName>NVIC</groupName>
<baseAddress>0xE000E100</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x355</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ISER0</name>
<displayName>ISER0</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER1</name>
<displayName>ISER1</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISER2</name>
<displayName>ISER2</displayName>
<description>Interrupt Set-Enable Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETENA</name>
<description>SETENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER0</name>
<displayName>ICER0</displayName>
<description>Interrupt Clear-Enable
Register</description>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER1</name>
<displayName>ICER1</displayName>
<description>Interrupt Clear-Enable
Register</description>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICER2</name>
<displayName>ICER2</displayName>
<description>Interrupt Clear-Enable
Register</description>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRENA</name>
<description>CLRENA</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR0</name>
<displayName>ISPR0</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR1</name>
<displayName>ISPR1</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISPR2</name>
<displayName>ISPR2</displayName>
<description>Interrupt Set-Pending Register</description>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SETPEND</name>
<description>SETPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR0</name>
<displayName>ICPR0</displayName>
<description>Interrupt Clear-Pending
Register</description>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR1</name>
<displayName>ICPR1</displayName>
<description>Interrupt Clear-Pending
Register</description>
<addressOffset>0x184</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICPR2</name>
<displayName>ICPR2</displayName>
<description>Interrupt Clear-Pending
Register</description>
<addressOffset>0x188</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLRPEND</name>
<description>CLRPEND</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR0</name>
<displayName>IABR0</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x200</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR1</name>
<displayName>IABR1</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x204</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IABR2</name>
<displayName>IABR2</displayName>
<description>Interrupt Active Bit Register</description>
<addressOffset>0x208</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE</name>
<description>ACTIVE</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR0</name>
<displayName>IPR0</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x300</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR1</name>
<displayName>IPR1</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x304</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR2</name>
<displayName>IPR2</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x308</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR3</name>
<displayName>IPR3</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x30C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR4</name>
<displayName>IPR4</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x310</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR5</name>
<displayName>IPR5</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x314</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR6</name>
<displayName>IPR6</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x318</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR7</name>
<displayName>IPR7</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x31C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR8</name>
<displayName>IPR8</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x320</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR9</name>
<displayName>IPR9</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x324</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR10</name>
<displayName>IPR10</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x328</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR11</name>
<displayName>IPR11</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x32C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR12</name>
<displayName>IPR12</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x330</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR13</name>
<displayName>IPR13</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x334</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR14</name>
<displayName>IPR14</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x338</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR15</name>
<displayName>IPR15</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x33C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR16</name>
<displayName>IPR16</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x340</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR17</name>
<displayName>IPR17</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x344</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR18</name>
<displayName>IPR18</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x348</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR19</name>
<displayName>IPR19</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x34C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IPR20</name>
<displayName>IPR20</displayName>
<description>Interrupt Priority Register</description>
<addressOffset>0x350</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IPR_N0</name>
<description>IPR_N0</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N1</name>
<description>IPR_N1</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N2</name>
<description>IPR_N2</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IPR_N3</name>
<description>IPR_N3</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FLASH</name>
<description>FLASH</description>
<groupName>FLASH</groupName>
<baseAddress>0x40023C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FLASH</name>
<description>Flash global interrupt</description>
<value>4</value>
</interrupt>
<interrupt>
<name>FLASH</name>
<description>Flash global interrupt</description>
<value>4</value>
</interrupt>
<registers>
<register>
<name>ACR</name>
<displayName>ACR</displayName>
<description>Flash access control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LATENCY</name>
<description>Latency</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
<enumeratedValues><name>LATENCY</name><usage>read-write</usage><enumeratedValue><name>WS0</name><description>0 wait states</description><value>0</value></enumeratedValue><enumeratedValue><name>WS1</name><description>1 wait states</description><value>1</value></enumeratedValue><enumeratedValue><name>WS2</name><description>2 wait states</description><value>2</value></enumeratedValue><enumeratedValue><name>WS3</name><description>3 wait states</description><value>3</value></enumeratedValue><enumeratedValue><name>WS4</name><description>4 wait states</description><value>4</value></enumeratedValue><enumeratedValue><name>WS5</name><description>5 wait states</description><value>5</value></enumeratedValue><enumeratedValue><name>WS6</name><description>6 wait states</description><value>6</value></enumeratedValue><enumeratedValue><name>WS7</name><description>7 wait states</description><value>7</value></enumeratedValue><enumeratedValue><name>WS8</name><description>8 wait states</description><value>8</value></enumeratedValue><enumeratedValue><name>WS9</name><description>9 wait states</description><value>9</value></enumeratedValue><enumeratedValue><name>WS10</name><description>10 wait states</description><value>10</value></enumeratedValue><enumeratedValue><name>WS11</name><description>11 wait states</description><value>11</value></enumeratedValue><enumeratedValue><name>WS12</name><description>12 wait states</description><value>12</value></enumeratedValue><enumeratedValue><name>WS13</name><description>13 wait states</description><value>13</value></enumeratedValue><enumeratedValue><name>WS14</name><description>14 wait states</description><value>14</value></enumeratedValue><enumeratedValue><name>WS15</name><description>15 wait states</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PRFTEN</name>
<description>Prefetch enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>PRFTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Prefetch is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Prefetch is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ICEN</name>
<description>Instruction cache enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>ICEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Instruction cache is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Instruction cache is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DCEN</name>
<description>Data cache enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>DCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Data cache is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Data cache is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ICRST</name>
<description>Instruction cache reset</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues><name>ICRST</name><usage>read-write</usage><enumeratedValue><name>NotReset</name><description>Instruction cache is not reset</description><value>0</value></enumeratedValue><enumeratedValue><name>Reset</name><description>Instruction cache is reset</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DCRST</name>
<description>Data cache reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>DCRST</name><usage>read-write</usage><enumeratedValue><name>NotReset</name><description>Data cache is not reset</description><value>0</value></enumeratedValue><enumeratedValue><name>Reset</name><description>Data cache is reset</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>KEYR</name>
<displayName>KEYR</displayName>
<description>Flash key register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY</name>
<description>FPEC key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>OPTKEYR</name>
<displayName>OPTKEYR</displayName>
<description>Flash option key register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPTKEY</name>
<description>Option byte key</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>SR</displayName>
<description>Status register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EOP</name>
<description>End of operation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OPERR</name>
<description>Operation error</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WRPERR</name>
<description>Write protection error</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PGAERR</name>
<description>Programming alignment
error</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PGPERR</name>
<description>Programming parallelism
error</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PGSERR</name>
<description>Programming sequence error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BSY</name>
<description>Busy</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>Control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x80000000</resetValue>
<fields>
<field>
<name>PG</name>
<description>Programming</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PG</name><usage>read-write</usage><enumeratedValue><name>Program</name><description>Flash programming activated</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SER</name>
<description>Sector Erase</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SER</name><usage>read-write</usage><enumeratedValue><name>SectorErase</name><description>Erase activated for selected sector</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MER</name>
<description>Mass Erase of sectors 0 to
11</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MER</name><usage>read-write</usage><enumeratedValue><name>MassErase</name><description>Erase activated for all user sectors</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SNB</name>
<description>Sector number</description>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>11</maximum></range></writeConstraint>
</field>
<field>
<name>PSIZE</name>
<description>Program size</description>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PSIZE</name><usage>read-write</usage><enumeratedValue><name>PSIZE8</name><description>Program x8</description><value>0</value></enumeratedValue><enumeratedValue><name>PSIZE16</name><description>Program x16</description><value>1</value></enumeratedValue><enumeratedValue><name>PSIZE32</name><description>Program x32</description><value>2</value></enumeratedValue><enumeratedValue><name>PSIZE64</name><description>Program x64</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MER1</name>
<description>Mass Erase of sectors 12 to
23</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRT</name>
<description>Start</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>STRT</name><usage>read-write</usage><enumeratedValue><name>Start</name><description>Trigger an erase operation</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>EOPIE</name>
<description>End of operation interrupt
enable</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>EOPIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>End of operation interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>End of operation interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ERRIE</name>
<description>Error interrupt enable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ERRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Error interrupt generation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Error interrupt generation enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LOCK</name>
<description>Lock</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LOCK</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>FLASH_CR register is unlocked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>FLASH_CR register is locked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>OPTCR</name>
<displayName>OPTCR</displayName>
<description>Flash option control register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFFAAED</resetValue>
<fields>
<field>
<name>OPTLOCK</name>
<description>Option lock</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPTSTRT</name>
<description>Option start</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOR_LEV</name>
<description>BOR reset Level</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>WDG_SW</name>
<description>WDG_SW User option bytes</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STOP</name>
<description>nRST_STOP User option
bytes</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>nRST_STDBY</name>
<description>nRST_STDBY User option
bytes</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RDP</name>
<description>Read protect</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>nWRP</name>
<description>Not write protect</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPTCR1</name>
<displayName>OPTCR1</displayName>
<description>Flash option control register
1</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0FFF0000</resetValue>
<fields>
<field>
<name>nWRP</name>
<description>Not write protect</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>EXTI</name>
<description>External interrupt/event
controller</description>
<groupName>EXTI</groupName>
<baseAddress>0x40013C00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TAMP_STAMP</name>
<description>Tamper and TimeStamp interrupts through the
EXTI line</description>
<value>2</value>
</interrupt>
<interrupt>
<name>TAMP_STAMP</name>
<description>Tamper and TimeStamp interrupts through the
EXTI line</description>
<value>2</value>
</interrupt>
<interrupt>
<name>EXTI0</name>
<description>EXTI Line0 interrupt</description>
<value>6</value>
</interrupt>
<interrupt>
<name>EXTI0</name>
<description>EXTI Line0 interrupt</description>
<value>6</value>
</interrupt>
<interrupt>
<name>EXTI1</name>
<description>EXTI Line1 interrupt</description>
<value>7</value>
</interrupt>
<interrupt>
<name>EXTI1</name>
<description>EXTI Line1 interrupt</description>
<value>7</value>
</interrupt>
<interrupt>
<name>EXTI2</name>
<description>EXTI Line2 interrupt</description>
<value>8</value>
</interrupt>
<interrupt>
<name>EXTI2</name>
<description>EXTI Line2 interrupt</description>
<value>8</value>
</interrupt>
<interrupt>
<name>EXTI3</name>
<description>EXTI Line3 interrupt</description>
<value>9</value>
</interrupt>
<interrupt>
<name>EXTI3</name>
<description>EXTI Line3 interrupt</description>
<value>9</value>
</interrupt>
<interrupt>
<name>EXTI4</name>
<description>EXTI Line4 interrupt</description>
<value>10</value>
</interrupt>
<interrupt>
<name>EXTI4</name>
<description>EXTI Line4 interrupt</description>
<value>10</value>
</interrupt>
<interrupt>
<name>EXTI9_5</name>
<description>EXTI Line[9:5] interrupts</description>
<value>23</value>
</interrupt>
<interrupt>
<name>EXTI9_5</name>
<description>EXTI Line[9:5] interrupts</description>
<value>23</value>
</interrupt>
<interrupt>
<name>EXTI15_10</name>
<description>EXTI Line[15:10] interrupts</description>
<value>40</value>
</interrupt>
<interrupt>
<name>EXTI15_10</name>
<description>EXTI Line[15:10] interrupts</description>
<value>40</value>
</interrupt>
<registers>
<register>
<name>IMR</name>
<displayName>IMR</displayName>
<description>Interrupt mask register
(EXTI_IMR)</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MR0</name>
<description>Interrupt Mask on line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MR0</name><usage>read-write</usage><enumeratedValue><name>Masked</name><description>Interrupt request line is masked</description><value>0</value></enumeratedValue><enumeratedValue><name>Unmasked</name><description>Interrupt request line is unmasked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MR1</name>
<description>Interrupt Mask on line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR2</name>
<description>Interrupt Mask on line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR3</name>
<description>Interrupt Mask on line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR4</name>
<description>Interrupt Mask on line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR5</name>
<description>Interrupt Mask on line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR6</name>
<description>Interrupt Mask on line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR7</name>
<description>Interrupt Mask on line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR8</name>
<description>Interrupt Mask on line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR9</name>
<description>Interrupt Mask on line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR10</name>
<description>Interrupt Mask on line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR11</name>
<description>Interrupt Mask on line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR12</name>
<description>Interrupt Mask on line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR13</name>
<description>Interrupt Mask on line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR14</name>
<description>Interrupt Mask on line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR15</name>
<description>Interrupt Mask on line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR16</name>
<description>Interrupt Mask on line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR17</name>
<description>Interrupt Mask on line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR18</name>
<description>Interrupt Mask on line 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR19</name>
<description>Interrupt Mask on line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR20</name>
<description>Interrupt Mask on line 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR21</name>
<description>Interrupt Mask on line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR22</name>
<description>Interrupt Mask on line 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
</fields>
</register>
<register>
<name>EMR</name>
<displayName>EMR</displayName>
<description>Event mask register (EXTI_EMR)</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MR0</name>
<description>Event Mask on line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MR0</name><usage>read-write</usage><enumeratedValue><name>Masked</name><description>Interrupt request line is masked</description><value>0</value></enumeratedValue><enumeratedValue><name>Unmasked</name><description>Interrupt request line is unmasked</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MR1</name>
<description>Event Mask on line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR2</name>
<description>Event Mask on line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR3</name>
<description>Event Mask on line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR4</name>
<description>Event Mask on line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR5</name>
<description>Event Mask on line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR6</name>
<description>Event Mask on line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR7</name>
<description>Event Mask on line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR8</name>
<description>Event Mask on line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR9</name>
<description>Event Mask on line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR10</name>
<description>Event Mask on line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR11</name>
<description>Event Mask on line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR12</name>
<description>Event Mask on line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR13</name>
<description>Event Mask on line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR14</name>
<description>Event Mask on line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR15</name>
<description>Event Mask on line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR16</name>
<description>Event Mask on line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR17</name>
<description>Event Mask on line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR18</name>
<description>Event Mask on line 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR19</name>
<description>Event Mask on line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR20</name>
<description>Event Mask on line 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR21</name>
<description>Event Mask on line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
<field>
<name>MR22</name>
<description>Event Mask on line 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="MR0"/>
</field>
</fields>
</register>
<register>
<name>RTSR</name>
<displayName>RTSR</displayName>
<description>Rising Trigger selection register
(EXTI_RTSR)</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TR0</name>
<description>Rising trigger event configuration of
line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TR0</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Rising edge trigger is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Rising edge trigger is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TR1</name>
<description>Rising trigger event configuration of
line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR2</name>
<description>Rising trigger event configuration of
line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR3</name>
<description>Rising trigger event configuration of
line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR4</name>
<description>Rising trigger event configuration of
line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR5</name>
<description>Rising trigger event configuration of
line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR6</name>
<description>Rising trigger event configuration of
line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR7</name>
<description>Rising trigger event configuration of
line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR8</name>
<description>Rising trigger event configuration of
line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR9</name>
<description>Rising trigger event configuration of
line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR10</name>
<description>Rising trigger event configuration of
line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR11</name>
<description>Rising trigger event configuration of
line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR12</name>
<description>Rising trigger event configuration of
line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR13</name>
<description>Rising trigger event configuration of
line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR14</name>
<description>Rising trigger event configuration of
line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR15</name>
<description>Rising trigger event configuration of
line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR16</name>
<description>Rising trigger event configuration of
line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR17</name>
<description>Rising trigger event configuration of
line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR18</name>
<description>Rising trigger event configuration of
line 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR19</name>
<description>Rising trigger event configuration of
line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR20</name>
<description>Rising trigger event configuration of
line 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR21</name>
<description>Rising trigger event configuration of
line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR22</name>
<description>Rising trigger event configuration of
line 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
</fields>
</register>
<register>
<name>FTSR</name>
<displayName>FTSR</displayName>
<description>Falling Trigger selection register
(EXTI_FTSR)</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TR0</name>
<description>Falling trigger event configuration of
line 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TR0</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Falling edge trigger is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Falling edge trigger is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TR1</name>
<description>Falling trigger event configuration of
line 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR2</name>
<description>Falling trigger event configuration of
line 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR3</name>
<description>Falling trigger event configuration of
line 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR4</name>
<description>Falling trigger event configuration of
line 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR5</name>
<description>Falling trigger event configuration of
line 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR6</name>
<description>Falling trigger event configuration of
line 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR7</name>
<description>Falling trigger event configuration of
line 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR8</name>
<description>Falling trigger event configuration of
line 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR9</name>
<description>Falling trigger event configuration of
line 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR10</name>
<description>Falling trigger event configuration of
line 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR11</name>
<description>Falling trigger event configuration of
line 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR12</name>
<description>Falling trigger event configuration of
line 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR13</name>
<description>Falling trigger event configuration of
line 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR14</name>
<description>Falling trigger event configuration of
line 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR15</name>
<description>Falling trigger event configuration of
line 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR16</name>
<description>Falling trigger event configuration of
line 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR17</name>
<description>Falling trigger event configuration of
line 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR18</name>
<description>Falling trigger event configuration of
line 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR19</name>
<description>Falling trigger event configuration of
line 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR20</name>
<description>Falling trigger event configuration of
line 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR21</name>
<description>Falling trigger event configuration of
line 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
<field>
<name>TR22</name>
<description>Falling trigger event configuration of
line 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="TR0"/>
</field>
</fields>
</register>
<register>
<name>SWIER</name>
<displayName>SWIER</displayName>
<description>Software interrupt event register
(EXTI_SWIER)</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SWIER0</name>
<description>Software Interrupt on line
0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SWIER0W</name><usage>write</usage><enumeratedValue><name>Pend</name><description>Generates an interrupt request</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SWIER1</name>
<description>Software Interrupt on line
1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER2</name>
<description>Software Interrupt on line
2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER3</name>
<description>Software Interrupt on line
3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER4</name>
<description>Software Interrupt on line
4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER5</name>
<description>Software Interrupt on line
5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER6</name>
<description>Software Interrupt on line
6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER7</name>
<description>Software Interrupt on line
7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER8</name>
<description>Software Interrupt on line
8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER9</name>
<description>Software Interrupt on line
9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER10</name>
<description>Software Interrupt on line
10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER11</name>
<description>Software Interrupt on line
11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER12</name>
<description>Software Interrupt on line
12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER13</name>
<description>Software Interrupt on line
13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER14</name>
<description>Software Interrupt on line
14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER15</name>
<description>Software Interrupt on line
15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER16</name>
<description>Software Interrupt on line
16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER17</name>
<description>Software Interrupt on line
17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER18</name>
<description>Software Interrupt on line
18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER19</name>
<description>Software Interrupt on line
19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER20</name>
<description>Software Interrupt on line
20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER21</name>
<description>Software Interrupt on line
21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
<field>
<name>SWIER22</name>
<description>Software Interrupt on line
22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="SWIER0W"/>
</field>
</fields>
</register>
<register>
<name>PR</name>
<displayName>PR</displayName>
<description>Pending register (EXTI_PR)</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PR0</name>
<description>Pending bit 0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PR0R</name><usage>read</usage><enumeratedValue><name>NotPending</name><description>No trigger request occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Pending</name><description>Selected trigger request occurred</description><value>1</value></enumeratedValue></enumeratedValues>
<enumeratedValues><name>PR0W</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears pending bit</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PR1</name>
<description>Pending bit 1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR2</name>
<description>Pending bit 2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR3</name>
<description>Pending bit 3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR4</name>
<description>Pending bit 4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR5</name>
<description>Pending bit 5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR6</name>
<description>Pending bit 6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR7</name>
<description>Pending bit 7</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR8</name>
<description>Pending bit 8</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR9</name>
<description>Pending bit 9</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR10</name>
<description>Pending bit 10</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR11</name>
<description>Pending bit 11</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR12</name>
<description>Pending bit 12</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR13</name>
<description>Pending bit 13</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR14</name>
<description>Pending bit 14</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR15</name>
<description>Pending bit 15</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR16</name>
<description>Pending bit 16</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR17</name>
<description>Pending bit 17</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR18</name>
<description>Pending bit 18</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR19</name>
<description>Pending bit 19</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR20</name>
<description>Pending bit 20</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR21</name>
<description>Pending bit 21</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
<field>
<name>PR22</name>
<description>Pending bit 22</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues derivedFrom="PR0R"/>
<enumeratedValues derivedFrom="PR0W"/>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OTG_HS_GLOBAL</name>
<description>USB on the go high speed</description>
<groupName>USB_OTG_HS</groupName>
<baseAddress>0x40040000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>OTG_HS_EP1_OUT</name>
<description>USB On The Go HS End Point 1 Out global
interrupt</description>
<value>74</value>
</interrupt>
<interrupt>
<name>OTG_HS_EP1_OUT</name>
<description>USB On The Go HS End Point 1 Out global
interrupt</description>
<value>74</value>
</interrupt>
<interrupt>
<name>OTG_HS_EP1_IN</name>
<description>USB On The Go HS End Point 1 In global
interrupt</description>
<value>75</value>
</interrupt>
<interrupt>
<name>OTG_HS_EP1_IN</name>
<description>USB On The Go HS End Point 1 In global
interrupt</description>
<value>75</value>
</interrupt>
<interrupt>
<name>OTG_HS_WKUP</name>
<description>USB On The Go HS Wakeup through EXTI
interrupt</description>
<value>76</value>
</interrupt>
<interrupt>
<name>OTG_HS_WKUP</name>
<description>USB On The Go HS Wakeup through EXTI
interrupt</description>
<value>76</value>
</interrupt>
<interrupt>
<name>OTG_HS</name>
<description>USB On The Go HS global
interrupt</description>
<value>77</value>
</interrupt>
<interrupt>
<name>OTG_HS</name>
<description>USB On The Go HS global
interrupt</description>
<value>77</value>
</interrupt>
<registers>
<register>
<name>GOTGCTL</name>
<displayName>GOTGCTL</displayName>
<description>OTG_HS control and status
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000800</resetValue>
<fields>
<field>
<name>SRQSCS</name>
<description>Session request success</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SRQ</name>
<description>Session request</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HNGSCS</name>
<description>Host negotiation success</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HNPRQ</name>
<description>HNP request</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSHNPEN</name>
<description>Host set HNP enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DHNPEN</name>
<description>Device HNP enabled</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CIDSTS</name>
<description>Connector ID status</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DBCT</name>
<description>Long/short debounce time</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ASVLD</name>
<description>A-session valid</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BSVLD</name>
<description>B-session valid</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GOTGINT</name>
<displayName>GOTGINT</displayName>
<description>OTG_HS interrupt register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>SEDET</name>
<description>Session end detected</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRSSCHG</name>
<description>Session request success status
change</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HNSSCHG</name>
<description>Host negotiation success status
change</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HNGDET</name>
<description>Host negotiation detected</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADTOCHG</name>
<description>A-device timeout change</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBCDNE</name>
<description>Debounce done</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GAHBCFG</name>
<displayName>GAHBCFG</displayName>
<description>OTG_HS AHB configuration
register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>GINT</name>
<description>Global interrupt mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HBSTLEN</name>
<description>Burst length/type</description>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFELVL</name>
<description>TxFIFO empty level</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PTXFELVL</name>
<description>Periodic TxFIFO empty
level</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GUSBCFG</name>
<displayName>GUSBCFG</displayName>
<description>OTG_HS USB configuration
register</description>
<addressOffset>0xC</addressOffset>
<size>32</size>
<resetValue>0x00000A00</resetValue>
<fields>
<field>
<name>TOCAL</name>
<description>FS timeout calibration</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PHYSEL</name>
<description>USB 2.0 high-speed ULPI PHY or USB 1.1
full-speed serial transceiver select</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SRPCAP</name>
<description>SRP-capable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HNPCAP</name>
<description>HNP-capable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TRDT</name>
<description>USB turnaround time</description>
<bitOffset>10</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PHYLPCS</name>
<description>PHY Low-power clock select</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPIFSLS</name>
<description>ULPI FS/LS select</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPIAR</name>
<description>ULPI Auto-resume</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPICSM</name>
<description>ULPI Clock SuspendM</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPIEVBUSD</name>
<description>ULPI External VBUS Drive</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPIEVBUSI</name>
<description>ULPI external VBUS
indicator</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TSDPS</name>
<description>TermSel DLine pulsing
selection</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PCCI</name>
<description>Indicator complement</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTCI</name>
<description>Indicator pass through</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ULPIIPD</name>
<description>ULPI interface protect
disable</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FHMOD</name>
<description>Forced host mode</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FDMOD</name>
<description>Forced peripheral mode</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTXPKT</name>
<description>Corrupt Tx packet</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GRSTCTL</name>
<displayName>GRSTCTL</displayName>
<description>OTG_HS reset register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x20000000</resetValue>
<fields>
<field>
<name>CSRST</name>
<description>Core soft reset</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HSRST</name>
<description>HCLK soft reset</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FCRST</name>
<description>Host frame counter reset</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXFFLSH</name>
<description>RxFIFO flush</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFFLSH</name>
<description>TxFIFO flush</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>6</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMAREQ</name>
<description>DMA request signal</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AHBIDL</name>
<description>AHB master idle</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>GINTSTS</name>
<displayName>GINTSTS</displayName>
<description>OTG_HS core interrupt register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x04000020</resetValue>
<fields>
<field>
<name>CMOD</name>
<description>Current mode of operation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>MMIS</name>
<description>Mode mismatch interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OTGINT</name>
<description>OTG interrupt</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SOF</name>
<description>Start of frame</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXFLVL</name>
<description>RxFIFO nonempty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NPTXFE</name>
<description>Nonperiodic TxFIFO empty</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>GINAKEFF</name>
<description>Global IN nonperiodic NAK
effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BOUTNAKEFF</name>
<description>Global OUT NAK effective</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>ESUSP</name>
<description>Early suspend</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBSUSP</name>
<description>USB suspend</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBRST</name>
<description>USB reset</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ENUMDNE</name>
<description>Enumeration done</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ISOODRP</name>
<description>Isochronous OUT packet dropped
interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EOPF</name>
<description>End of periodic frame
interrupt</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEPINT</name>
<description>IN endpoint interrupt</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OEPINT</name>
<description>OUT endpoint interrupt</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>IISOIXFR</name>
<description>Incomplete isochronous IN
transfer</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PXFR_INCOMPISOOUT</name>
<description>Incomplete periodic
transfer</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DATAFSUSP</name>
<description>Data fetch suspended</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>HPRTINT</name>
<description>Host port interrupt</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HCINT</name>
<description>Host channels interrupt</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PTXFE</name>
<description>Periodic TxFIFO empty</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CIDSCHG</name>
<description>Connector ID status change</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DISCINT</name>
<description>Disconnect detected
interrupt</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SRQINT</name>
<description>Session request/new session detected
interrupt</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WKUPINT</name>
<description>Resume/remote wakeup detected interrupt</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GINTMSK</name>
<displayName>GINTMSK</displayName>
<description>OTG_HS interrupt mask register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MMISM</name>
<description>Mode mismatch interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OTGINT</name>
<description>OTG interrupt mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SOFM</name>
<description>Start of frame mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXFLVLM</name>
<description>Receive FIFO nonempty mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NPTXFEM</name>
<description>Nonperiodic TxFIFO empty
mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GINAKEFFM</name>
<description>Global nonperiodic IN NAK effective
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GONAKEFFM</name>
<description>Global OUT NAK effective
mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ESUSPM</name>
<description>Early suspend mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBSUSPM</name>
<description>USB suspend mask</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBRST</name>
<description>USB reset mask</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ENUMDNEM</name>
<description>Enumeration done mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ISOODRPM</name>
<description>Isochronous OUT packet dropped interrupt
mask</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EOPFM</name>
<description>End of periodic frame interrupt
mask</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPMISM</name>
<description>Endpoint mismatch interrupt
mask</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IEPINT</name>
<description>IN endpoints interrupt
mask</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OEPINT</name>
<description>OUT endpoints interrupt
mask</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IISOIXFRM</name>
<description>Incomplete isochronous IN transfer
mask</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PXFRM_IISOOXFRM</name>
<description>Incomplete periodic transfer
mask</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FSUSPM</name>
<description>Data fetch suspended mask</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRTIM</name>
<description>Host port interrupt mask</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>HCIM</name>
<description>Host channels interrupt
mask</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTXFEM</name>
<description>Periodic TxFIFO empty mask</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CIDSCHGM</name>
<description>Connector ID status change
mask</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DISCINT</name>
<description>Disconnect detected interrupt
mask</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SRQIM</name>
<description>Session request/new session detected
interrupt mask</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WUIM</name>
<description>Resume/remote wakeup detected interrupt
mask</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>GRXSTSR_Host</name>
<displayName>GRXSTSR_Host</displayName>
<description>OTG_HS Receive status debug read register
(host mode)</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>CHNUM</name>
<description>Channel number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BCNT</name>
<description>Byte count</description>
<bitOffset>4</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTSTS</name>
<description>Packet status</description>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GRXSTSP_Host</name>
<displayName>GRXSTSP_Host</displayName>
<description>OTG_HS status read and pop register (host
mode)</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>CHNUM</name>
<description>Channel number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BCNT</name>
<description>Byte count</description>
<bitOffset>4</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTSTS</name>
<description>Packet status</description>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GRXFSIZ</name>
<displayName>GRXFSIZ</displayName>
<description>OTG_HS Receive FIFO size
register</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>RXFD</name>
<description>RxFIFO depth</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>GNPTXFSIZ</name>
<displayName>GNPTXFSIZ</displayName>
<description>OTG_HS nonperiodic transmit FIFO size
register (host mode)</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>NPTXFSA</name>
<description>Nonperiodic transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>NPTXFD</name>
<description>Nonperiodic TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TX0FSIZ</name>
<displayName>TX0FSIZ</displayName>
<description>Endpoint 0 transmit FIFO size (peripheral
mode)</description>
<alternateRegister>GNPTXFSIZ</alternateRegister>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000200</resetValue>
<fields>
<field>
<name>TX0FSA</name>
<description>Endpoint 0 transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TX0FD</name>
<description>Endpoint 0 TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>GNPTXSTS</name>
<displayName>GNPTXSTS</displayName>
<description>OTG_HS nonperiodic transmit FIFO/queue
status register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00080200</resetValue>
<fields>
<field>
<name>NPTXFSAV</name>
<description>Nonperiodic TxFIFO space
available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>NPTQXSAV</name>
<description>Nonperiodic transmit request queue space
available</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>NPTXQTOP</name>
<description>Top of the nonperiodic transmit request
queue</description>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>GCCFG</name>
<displayName>GCCFG</displayName>
<description>OTG_HS general core configuration
register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PWRDWN</name>
<description>Power down</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2CPADEN</name>
<description>Enable I2C bus connection for the
external I2C PHY interface</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBUSASEN</name>
<description>Enable the VBUS sensing
device</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VBUSBSEN</name>
<description>Enable the VBUS sensing
device</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SOFOUTEN</name>
<description>SOF output enable</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOVBUSSENS</name>
<description>VBUS sensing disable
option</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CID</name>
<displayName>CID</displayName>
<description>OTG_HS core ID register</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00001200</resetValue>
<fields>
<field>
<name>PRODUCT_ID</name>
<description>Product ID field</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HPTXFSIZ</name>
<displayName>HPTXFSIZ</displayName>
<description>OTG_HS Host periodic transmit FIFO size
register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02000600</resetValue>
<fields>
<field>
<name>PTXSA</name>
<description>Host periodic TxFIFO start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>PTXFD</name>
<description>Host periodic TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<dim>5</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4,5</dimIndex><name>DIEPTXF%s</name>
<displayName>DIEPTXF1</displayName>
<description>OTG_HS device IN endpoint transmit FIFO size
register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02000400</resetValue>
<fields>
<field>
<name>INEPTXSA</name>
<description>IN endpoint FIFOx transmit RAM start
address</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>INEPTXFD</name>
<description>IN endpoint TxFIFO depth</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>GRXSTSR_Peripheral</name>
<displayName>GRXSTSR_Peripheral</displayName>
<description>OTG_HS Receive status debug read register
(peripheral mode mode)</description>
<alternateRegister>OTG_HS_GRXSTSR_Host</alternateRegister>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BCNT</name>
<description>Byte count</description>
<bitOffset>4</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTSTS</name>
<description>Packet status</description>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FRMNUM</name>
<description>Frame number</description>
<bitOffset>21</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GRXSTSP_Peripheral</name>
<displayName>GRXSTSP_Peripheral</displayName>
<description>OTG_HS status read and pop register
(peripheral mode)</description>
<alternateRegister>OTG_HS_GRXSTSP_Host</alternateRegister>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BCNT</name>
<description>Byte count</description>
<bitOffset>4</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PKTSTS</name>
<description>Packet status</description>
<bitOffset>17</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>FRMNUM</name>
<description>Frame number</description>
<bitOffset>21</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OTG_HS_HOST</name>
<description>USB on the go high speed</description>
<groupName>USB_OTG_HS</groupName>
<baseAddress>0x40040400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>HCFG</name>
<displayName>HCFG</displayName>
<description>OTG_HS host configuration
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>FSLSPCS</name>
<description>FS/LS PHY clock select</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FSLSS</name>
<description>FS- and LS-only support</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HFIR</name>
<displayName>HFIR</displayName>
<description>OTG_HS Host frame interval
register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0000EA60</resetValue>
<fields>
<field>
<name>FRIVL</name>
<description>Frame interval</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>HFNUM</name>
<displayName>HFNUM</displayName>
<description>OTG_HS host frame number/frame time
remaining register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00003FFF</resetValue>
<fields>
<field>
<name>FRNUM</name>
<description>Frame number</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>FTREM</name>
<description>Frame time remaining</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>HPTXSTS</name>
<displayName>HPTXSTS</displayName>
<description>OTG_HS_Host periodic transmit FIFO/queue
status register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00080100</resetValue>
<fields>
<field>
<name>PTXFSAVL</name>
<description>Periodic transmit data FIFO space
available</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTXQSAV</name>
<description>Periodic transmit request queue space
available</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PTXQTOP</name>
<description>Top of the periodic transmit request
queue</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HAINT</name>
<displayName>HAINT</displayName>
<description>OTG_HS Host all channels interrupt
register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>HAINT</name>
<description>Channel interrupts</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>HAINTMSK</name>
<displayName>HAINTMSK</displayName>
<description>OTG_HS host all channels interrupt mask
register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>HAINTM</name>
<description>Channel interrupt mask</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>HPRT</name>
<displayName>HPRT</displayName>
<description>OTG_HS host port control and status
register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PCSTS</name>
<description>Port connect status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PCDET</name>
<description>Port connect detected</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PENA</name>
<description>Port enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PENCHNG</name>
<description>Port enable/disable change</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>POCA</name>
<description>Port overcurrent active</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>POCCHNG</name>
<description>Port overcurrent change</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRES</name>
<description>Port resume</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PSUSP</name>
<description>Port suspend</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRST</name>
<description>Port reset</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PLSTS</name>
<description>Port line status</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PPWR</name>
<description>Port power</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PTCTL</name>
<description>Port test control</description>
<bitOffset>13</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PSPD</name>
<description>Port speed</description>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>HCCHAR0</name>
<displayName>HCCHAR0</displayName>
<description>OTG_HS host channel-0 characteristics
register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR1</name>
<displayName>HCCHAR1</displayName>
<description>OTG_HS host channel-1 characteristics
register</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR2</name>
<displayName>HCCHAR2</displayName>
<description>OTG_HS host channel-2 characteristics
register</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR3</name>
<displayName>HCCHAR3</displayName>
<description>OTG_HS host channel-3 characteristics
register</description>
<addressOffset>0x160</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR4</name>
<displayName>HCCHAR4</displayName>
<description>OTG_HS host channel-4 characteristics
register</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR5</name>
<displayName>HCCHAR5</displayName>
<description>OTG_HS host channel-5 characteristics
register</description>
<addressOffset>0x1A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR6</name>
<displayName>HCCHAR6</displayName>
<description>OTG_HS host channel-6 characteristics
register</description>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR7</name>
<displayName>HCCHAR7</displayName>
<description>OTG_HS host channel-7 characteristics
register</description>
<addressOffset>0x1E0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR8</name>
<displayName>HCCHAR8</displayName>
<description>OTG_HS host channel-8 characteristics
register</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR9</name>
<displayName>HCCHAR9</displayName>
<description>OTG_HS host channel-9 characteristics
register</description>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR10</name>
<displayName>HCCHAR10</displayName>
<description>OTG_HS host channel-10 characteristics
register</description>
<addressOffset>0x240</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCCHAR11</name>
<displayName>HCCHAR11</displayName>
<description>OTG_HS host channel-11 characteristics
register</description>
<addressOffset>0x260</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>EPNUM</name>
<description>Endpoint number</description>
<bitOffset>11</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>EPDIR</name>
<description>Endpoint direction</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSDEV</name>
<description>Low-speed device</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MC</name>
<description>Multi Count (MC) / Error Count
(EC)</description>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>22</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ODDFRM</name>
<description>Odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHDIS</name>
<description>Channel disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHENA</name>
<description>Channel enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT0</name>
<displayName>HCSPLT0</displayName>
<description>OTG_HS host channel-0 split control
register</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT1</name>
<displayName>HCSPLT1</displayName>
<description>OTG_HS host channel-1 split control
register</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT2</name>
<displayName>HCSPLT2</displayName>
<description>OTG_HS host channel-2 split control
register</description>
<addressOffset>0x144</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT3</name>
<displayName>HCSPLT3</displayName>
<description>OTG_HS host channel-3 split control
register</description>
<addressOffset>0x164</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT4</name>
<displayName>HCSPLT4</displayName>
<description>OTG_HS host channel-4 split control
register</description>
<addressOffset>0x184</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT5</name>
<displayName>HCSPLT5</displayName>
<description>OTG_HS host channel-5 split control
register</description>
<addressOffset>0x1A4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT6</name>
<displayName>HCSPLT6</displayName>
<description>OTG_HS host channel-6 split control
register</description>
<addressOffset>0x1C4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT7</name>
<displayName>HCSPLT7</displayName>
<description>OTG_HS host channel-7 split control
register</description>
<addressOffset>0x1E4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT8</name>
<displayName>HCSPLT8</displayName>
<description>OTG_HS host channel-8 split control
register</description>
<addressOffset>0x204</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT9</name>
<displayName>HCSPLT9</displayName>
<description>OTG_HS host channel-9 split control
register</description>
<addressOffset>0x224</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT10</name>
<displayName>HCSPLT10</displayName>
<description>OTG_HS host channel-10 split control
register</description>
<addressOffset>0x244</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCSPLT11</name>
<displayName>HCSPLT11</displayName>
<description>OTG_HS host channel-11 split control
register</description>
<addressOffset>0x264</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>PRTADDR</name>
<description>Port address</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>HUBADDR</name>
<description>Hub address</description>
<bitOffset>7</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>XACTPOS</name>
<description>XACTPOS</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>COMPLSPLT</name>
<description>Do complete split</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPLITEN</name>
<description>Split enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT0</name>
<displayName>HCINT0</displayName>
<description>OTG_HS host channel-11 interrupt
register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT1</name>
<displayName>HCINT1</displayName>
<description>OTG_HS host channel-1 interrupt
register</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT2</name>
<displayName>HCINT2</displayName>
<description>OTG_HS host channel-2 interrupt
register</description>
<addressOffset>0x148</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT3</name>
<displayName>HCINT3</displayName>
<description>OTG_HS host channel-3 interrupt
register</description>
<addressOffset>0x168</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT4</name>
<displayName>HCINT4</displayName>
<description>OTG_HS host channel-4 interrupt
register</description>
<addressOffset>0x188</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT5</name>
<displayName>HCINT5</displayName>
<description>OTG_HS host channel-5 interrupt
register</description>
<addressOffset>0x1A8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT6</name>
<displayName>HCINT6</displayName>
<description>OTG_HS host channel-6 interrupt
register</description>
<addressOffset>0x1C8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT7</name>
<displayName>HCINT7</displayName>
<description>OTG_HS host channel-7 interrupt
register</description>
<addressOffset>0x1E8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT8</name>
<displayName>HCINT8</displayName>
<description>OTG_HS host channel-8 interrupt
register</description>
<addressOffset>0x208</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT9</name>
<displayName>HCINT9</displayName>
<description>OTG_HS host channel-9 interrupt
register</description>
<addressOffset>0x228</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT10</name>
<displayName>HCINT10</displayName>
<description>OTG_HS host channel-10 interrupt
register</description>
<addressOffset>0x248</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINT11</name>
<displayName>HCINT11</displayName>
<description>OTG_HS host channel-11 interrupt
register</description>
<addressOffset>0x268</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHH</name>
<description>Channel halted</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALL</name>
<description>STALL response received
interrupt</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAK</name>
<description>NAK response received
interrupt</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK</name>
<description>ACK response received/transmitted
interrupt</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>Response received
interrupt</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERR</name>
<description>Transaction error</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERR</name>
<description>Babble error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMOR</name>
<description>Frame overrun</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERR</name>
<description>Data toggle error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK0</name>
<displayName>HCINTMSK0</displayName>
<description>OTG_HS host channel-11 interrupt mask
register</description>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK1</name>
<displayName>HCINTMSK1</displayName>
<description>OTG_HS host channel-1 interrupt mask
register</description>
<addressOffset>0x12C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK2</name>
<displayName>HCINTMSK2</displayName>
<description>OTG_HS host channel-2 interrupt mask
register</description>
<addressOffset>0x14C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK3</name>
<displayName>HCINTMSK3</displayName>
<description>OTG_HS host channel-3 interrupt mask
register</description>
<addressOffset>0x16C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK4</name>
<displayName>HCINTMSK4</displayName>
<description>OTG_HS host channel-4 interrupt mask
register</description>
<addressOffset>0x18C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK5</name>
<displayName>HCINTMSK5</displayName>
<description>OTG_HS host channel-5 interrupt mask
register</description>
<addressOffset>0x1AC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK6</name>
<displayName>HCINTMSK6</displayName>
<description>OTG_HS host channel-6 interrupt mask
register</description>
<addressOffset>0x1CC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK7</name>
<displayName>HCINTMSK7</displayName>
<description>OTG_HS host channel-7 interrupt mask
register</description>
<addressOffset>0x1EC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK8</name>
<displayName>HCINTMSK8</displayName>
<description>OTG_HS host channel-8 interrupt mask
register</description>
<addressOffset>0x20C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK9</name>
<displayName>HCINTMSK9</displayName>
<description>OTG_HS host channel-9 interrupt mask
register</description>
<addressOffset>0x22C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK10</name>
<displayName>HCINTMSK10</displayName>
<description>OTG_HS host channel-10 interrupt mask
register</description>
<addressOffset>0x24C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCINTMSK11</name>
<displayName>HCINTMSK11</displayName>
<description>OTG_HS host channel-11 interrupt mask
register</description>
<addressOffset>0x26C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHHM</name>
<description>Channel halted mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBERR</name>
<description>AHB error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STALLM</name>
<description>STALL response received interrupt
mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK response received interrupt
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACKM</name>
<description>ACK response received/transmitted
interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>response received interrupt
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXERRM</name>
<description>Transaction error mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBERRM</name>
<description>Babble error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRMORM</name>
<description>Frame overrun mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTERRM</name>
<description>Data toggle error mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ0</name>
<displayName>HCTSIZ0</displayName>
<description>OTG_HS host channel-11 transfer size
register</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ1</name>
<displayName>HCTSIZ1</displayName>
<description>OTG_HS host channel-1 transfer size
register</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ2</name>
<displayName>HCTSIZ2</displayName>
<description>OTG_HS host channel-2 transfer size
register</description>
<addressOffset>0x150</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ3</name>
<displayName>HCTSIZ3</displayName>
<description>OTG_HS host channel-3 transfer size
register</description>
<addressOffset>0x170</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ4</name>
<displayName>HCTSIZ4</displayName>
<description>OTG_HS host channel-4 transfer size
register</description>
<addressOffset>0x190</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ5</name>
<displayName>HCTSIZ5</displayName>
<description>OTG_HS host channel-5 transfer size
register</description>
<addressOffset>0x1B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ6</name>
<displayName>HCTSIZ6</displayName>
<description>OTG_HS host channel-6 transfer size
register</description>
<addressOffset>0x1D0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ7</name>
<displayName>HCTSIZ7</displayName>
<description>OTG_HS host channel-7 transfer size
register</description>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ8</name>
<displayName>HCTSIZ8</displayName>
<description>OTG_HS host channel-8 transfer size
register</description>
<addressOffset>0x210</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ9</name>
<displayName>HCTSIZ9</displayName>
<description>OTG_HS host channel-9 transfer size
register</description>
<addressOffset>0x230</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ10</name>
<displayName>HCTSIZ10</displayName>
<description>OTG_HS host channel-10 transfer size
register</description>
<addressOffset>0x250</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCTSIZ11</name>
<displayName>HCTSIZ11</displayName>
<description>OTG_HS host channel-11 transfer size
register</description>
<addressOffset>0x270</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DPID</name>
<description>Data PID</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA0</name>
<displayName>HCDMA0</displayName>
<description>OTG_HS host channel-0 DMA address
register</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA1</name>
<displayName>HCDMA1</displayName>
<description>OTG_HS host channel-1 DMA address
register</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA2</name>
<displayName>HCDMA2</displayName>
<description>OTG_HS host channel-2 DMA address
register</description>
<addressOffset>0x154</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA3</name>
<displayName>HCDMA3</displayName>
<description>OTG_HS host channel-3 DMA address
register</description>
<addressOffset>0x174</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA4</name>
<displayName>HCDMA4</displayName>
<description>OTG_HS host channel-4 DMA address
register</description>
<addressOffset>0x194</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA5</name>
<displayName>HCDMA5</displayName>
<description>OTG_HS host channel-5 DMA address
register</description>
<addressOffset>0x1B4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA6</name>
<displayName>HCDMA6</displayName>
<description>OTG_HS host channel-6 DMA address
register</description>
<addressOffset>0x1D4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA7</name>
<displayName>HCDMA7</displayName>
<description>OTG_HS host channel-7 DMA address
register</description>
<addressOffset>0x1F4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA8</name>
<displayName>HCDMA8</displayName>
<description>OTG_HS host channel-8 DMA address
register</description>
<addressOffset>0x214</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA9</name>
<displayName>HCDMA9</displayName>
<description>OTG_HS host channel-9 DMA address
register</description>
<addressOffset>0x234</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA10</name>
<displayName>HCDMA10</displayName>
<description>OTG_HS host channel-10 DMA address
register</description>
<addressOffset>0x254</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HCDMA11</name>
<displayName>HCDMA11</displayName>
<description>OTG_HS host channel-11 DMA address
register</description>
<addressOffset>0x274</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OTG_HS_DEVICE</name>
<description>USB on the go high speed</description>
<groupName>USB_OTG_HS</groupName>
<baseAddress>0x40040800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DCFG</name>
<displayName>DCFG</displayName>
<description>OTG_HS device configuration
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x02200000</resetValue>
<fields>
<field>
<name>DSPD</name>
<description>Device speed</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>NZLSOHSK</name>
<description>Nonzero-length status OUT
handshake</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAD</name>
<description>Device address</description>
<bitOffset>4</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PFIVL</name>
<description>Periodic (micro)frame
interval</description>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PERSCHIVL</name>
<description>Periodic scheduling
interval</description>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DCTL</name>
<displayName>DCTL</displayName>
<description>OTG_HS device control register</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>RWUSIG</name>
<description>Remote wakeup signaling</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SDIS</name>
<description>Soft disconnect</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>GINSTS</name>
<description>Global IN NAK status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>GONSTS</name>
<description>Global OUT NAK status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TCTL</name>
<description>Test control</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SGINAK</name>
<description>Set global IN NAK</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CGINAK</name>
<description>Clear global IN NAK</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SGONAK</name>
<description>Set global OUT NAK</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CGONAK</name>
<description>Clear global OUT NAK</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>POPRGDNE</name>
<description>Power-on programming done</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DSTS</name>
<displayName>DSTS</displayName>
<description>OTG_HS device status register</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>SUSPSTS</name>
<description>Suspend status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENUMSPD</name>
<description>Enumerated speed</description>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>EERR</name>
<description>Erratic error</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FNSOF</name>
<description>Frame number of the received
SOF</description>
<bitOffset>8</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPMSK</name>
<displayName>DIEPMSK</displayName>
<description>OTG_HS device IN endpoint common interrupt
mask register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed interrupt
mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDM</name>
<description>Endpoint disabled interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOM</name>
<description>Timeout condition mask (nonisochronous
endpoints)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITTXFEMSK</name>
<description>IN token received when TxFIFO empty
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INEPNMM</name>
<description>IN token received with EP mismatch
mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INEPNEM</name>
<description>IN endpoint NAK effective
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFURM</name>
<description>FIFO underrun mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIM</name>
<description>BNA interrupt mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPMSK</name>
<displayName>DOEPMSK</displayName>
<description>OTG_HS device OUT endpoint common interrupt
mask register</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed interrupt
mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDM</name>
<description>Endpoint disabled interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUPM</name>
<description>SETUP phase done mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDM</name>
<description>OUT token received when endpoint
disabled mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2BSTUP</name>
<description>Back-to-back SETUP packets received
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OPEM</name>
<description>OUT packet error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BOIM</name>
<description>BNA interrupt mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAINT</name>
<displayName>DAINT</displayName>
<description>OTG_HS device all endpoints interrupt
register</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>IEPINT</name>
<description>IN endpoint interrupt bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>OEPINT</name>
<description>OUT endpoint interrupt
bits</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAINTMSK</name>
<displayName>DAINTMSK</displayName>
<description>OTG_HS all endpoints interrupt mask
register</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>IEPM</name>
<description>IN EP interrupt mask bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>OEPM</name>
<description>OUT EP interrupt mask bits</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DVBUSDIS</name>
<displayName>DVBUSDIS</displayName>
<description>OTG_HS device VBUS discharge time
register</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x000017D7</resetValue>
<fields>
<field>
<name>VBUSDT</name>
<description>Device VBUS discharge time</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DVBUSPULSE</name>
<displayName>DVBUSPULSE</displayName>
<description>OTG_HS device VBUS pulsing time
register</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x000005B8</resetValue>
<fields>
<field>
<name>DVBUSP</name>
<description>Device VBUS pulsing time</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DTHRCTL</name>
<displayName>DTHRCTL</displayName>
<description>OTG_HS Device threshold control
register</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>NONISOTHREN</name>
<description>Nonisochronous IN endpoints threshold
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ISOTHREN</name>
<description>ISO IN endpoint threshold
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXTHRLEN</name>
<description>Transmit threshold length</description>
<bitOffset>2</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>RXTHREN</name>
<description>Receive threshold enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXTHRLEN</name>
<description>Receive threshold length</description>
<bitOffset>17</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>ARPEN</name>
<description>Arbiter parking enable</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPEMPMSK</name>
<displayName>DIEPEMPMSK</displayName>
<description>OTG_HS device IN endpoint FIFO empty
interrupt mask register</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>INEPTXFEM</name>
<description>IN EP Tx FIFO empty interrupt mask
bits</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEACHINT</name>
<displayName>DEACHINT</displayName>
<description>OTG_HS device each endpoint interrupt
register</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>IEP1INT</name>
<description>IN endpoint 1interrupt bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OEP1INT</name>
<description>OUT endpoint 1 interrupt
bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEACHINTMSK</name>
<displayName>DEACHINTMSK</displayName>
<description>OTG_HS device each endpoint interrupt
register mask</description>
<addressOffset>0x3C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>IEP1INTM</name>
<description>IN Endpoint 1 interrupt mask
bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OEP1INTM</name>
<description>OUT Endpoint 1 interrupt mask
bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPEACHMSK1</name>
<displayName>DIEPEACHMSK1</displayName>
<description>OTG_HS device each in endpoint-1 interrupt
register</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed interrupt
mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDM</name>
<description>Endpoint disabled interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOM</name>
<description>Timeout condition mask (nonisochronous
endpoints)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITTXFEMSK</name>
<description>IN token received when TxFIFO empty
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INEPNMM</name>
<description>IN token received with EP mismatch
mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INEPNEM</name>
<description>IN endpoint NAK effective
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFURM</name>
<description>FIFO underrun mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIM</name>
<description>BNA interrupt mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK interrupt mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPEACHMSK1</name>
<displayName>DOEPEACHMSK1</displayName>
<description>OTG_HS device each OUT endpoint-1 interrupt
register</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRCM</name>
<description>Transfer completed interrupt
mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDM</name>
<description>Endpoint disabled interrupt
mask</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOM</name>
<description>Timeout condition mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ITTXFEMSK</name>
<description>IN token received when TxFIFO empty
mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INEPNMM</name>
<description>IN token received with EP mismatch
mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INEPNEM</name>
<description>IN endpoint NAK effective
mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFURM</name>
<description>OUT packet error mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIM</name>
<description>BNA interrupt mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BERRM</name>
<description>Bubble error interrupt
mask</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NAKM</name>
<description>NAK interrupt mask</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYETM</name>
<description>NYET interrupt mask</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPCTL0</name>
<displayName>DIEPCTL0</displayName>
<description>OTG device endpoint-0 control
register</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even/odd frame</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>5</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3,4,5</dimIndex><name>DIEPCTL%s</name>
<displayName>DIEPCTL1</displayName>
<description>OTG device endpoint-1 control
register</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even/odd frame</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFNUM</name>
<description>TxFIFO number</description>
<bitOffset>22</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>6</dim><dimIncrement>0x20</dimIncrement><dimIndex>0,1,2,3,4,5</dimIndex><name>DIEPINT%s</name>
<displayName>DIEPINT0</displayName>
<description>OTG device endpoint-%s interrupt
register</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TOC</name>
<description>Timeout condition</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>ITTXFE</name>
<description>IN token received when TxFIFO is
empty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>INEPNE</name>
<description>IN endpoint NAK effective</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFE</name>
<description>Transmit FIFO empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXFIFOUDRN</name>
<description>Transmit Fifo Underrun</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BNA</name>
<description>Buffer not available
interrupt</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PKTDRPSTS</name>
<description>Packet dropped status</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BERR</name>
<description>Babble error interrupt</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>NAK</name>
<description>NAK interrupt</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIEPTSIZ0</name>
<displayName>DIEPTSIZ0</displayName>
<description>OTG_HS device IN endpoint 0 transfer size
register</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPDMA1</name>
<displayName>DIEPDMA1</displayName>
<description>OTG_HS device endpoint-1 DMA address
register</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPDMA2</name>
<displayName>DIEPDMA2</displayName>
<description>OTG_HS device endpoint-2 DMA address
register</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPDMA3</name>
<displayName>DIEPDMA3</displayName>
<description>OTG_HS device endpoint-3 DMA address
register</description>
<addressOffset>0x154</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPDMA4</name>
<displayName>DIEPDMA4</displayName>
<description>OTG_HS device endpoint-4 DMA address
register</description>
<addressOffset>0x174</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIEPDMA5</name>
<displayName>DIEPDMA5</displayName>
<description>OTG_HS device endpoint-5 DMA address
register</description>
<addressOffset>0x194</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>DMAADDR</name>
<description>DMA address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<dim>6</dim><dimIncrement>0x20</dimIncrement><dimIndex>0,1,2,3,4,5</dimIndex><name>DTXFSTS%s</name>
<displayName>DTXFSTS0</displayName>
<description>OTG_HS device IN endpoint transmit FIFO
status register</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>INEPTFSAV</name>
<description>IN endpoint TxFIFO space
avail</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<dim>5</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3,4,5</dimIndex><name>DIEPTSIZ%s</name>
<displayName>DIEPTSIZ1</displayName>
<description>OTG_HS device endpoint transfer size
register</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MCNT</name>
<description>Multi count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPCTL0</name>
<displayName>DOEPCTL0</displayName>
<description>OTG_HS device control OUT endpoint 0 control
register</description>
<addressOffset>0x300</addressOffset>
<size>32</size>
<resetValue>0x00008000</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SNPM</name>
<description>Snoop mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<dim>5</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3,4,5</dimIndex><name>DOEPCTL%s</name>
<displayName>DOEPCTL1</displayName>
<description>OTG device endpoint-1 control
register</description>
<addressOffset>0x320</addressOffset>
<size>32</size>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>MPSIZ</name>
<description>Maximum packet size</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<access>read-write</access>
</field>
<field>
<name>USBAEP</name>
<description>USB active endpoint</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EONUM_DPID</name>
<description>Even odd frame/Endpoint data
PID</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>NAKSTS</name>
<description>NAK status</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>EPTYP</name>
<description>Endpoint type</description>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SNPM</name>
<description>Snoop mode</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STALL</name>
<description>STALL handshake</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CNAK</name>
<description>Clear NAK</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SNAK</name>
<description>Set NAK</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SD0PID_SEVNFRM</name>
<description>Set DATA0 PID/Set even
frame</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>SODDFRM</name>
<description>Set odd frame</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>EPDIS</name>
<description>Endpoint disable</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPENA</name>
<description>Endpoint enable</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>6</dim><dimIncrement>0x20</dimIncrement><dimIndex>0,1,2,3,4,5</dimIndex><name>DOEPINT%s</name>
<displayName>DOEPINT0</displayName>
<description>OTG_HS device endpoint-%s interrupt
register</description>
<addressOffset>0x308</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<fields>
<field>
<name>XFRC</name>
<description>Transfer completed
interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EPDISD</name>
<description>Endpoint disabled
interrupt</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUP</name>
<description>SETUP phase done</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OTEPDIS</name>
<description>OUT token received when endpoint
disabled</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>B2BSTUP</name>
<description>Back-to-back SETUP packets
received</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NYET</name>
<description>NYET interrupt</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DOEPTSIZ0</name>
<displayName>DOEPTSIZ0</displayName>
<description>OTG_HS device endpoint-1 transfer size
register</description>
<addressOffset>0x310</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STUPCNT</name>
<description>SETUP packet count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<dim>5</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3,4,5</dimIndex><name>DOEPTSIZ%s</name>
<displayName>DOEPTSIZ1</displayName>
<description>OTG_HS device endpoint-2 transfer size
register</description>
<addressOffset>0x330</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>XFRSIZ</name>
<description>Transfer size</description>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
<field>
<name>PKTCNT</name>
<description>Packet count</description>
<bitOffset>19</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>RXDPID_STUPCNT</name>
<description>Received data PID/SETUP packet
count</description>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>OTG_HS_PWRCLK</name>
<description>USB on the go high speed</description>
<groupName>USB_OTG_HS</groupName>
<baseAddress>0x40040E00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x3F200</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PCGCCTL</name>
<displayName>PCGCCTL</displayName>
<description>Power and clock gating control
register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>STPPCLK</name>
<description>Stop PHY clock</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GATEHCLK</name>
<description>Gate HCLK</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PHYSUSP</name>
<description>PHY suspended</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LTDC</name>
<description>LCD-TFT Controller</description>
<groupName>LTDC</groupName>
<baseAddress>0x40016800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LCD_TFT</name>
<description>LTDC global interrupt</description>
<value>88</value>
</interrupt>
<interrupt>
<name>LCD_TFT</name>
<description>LTDC global interrupt</description>
<value>88</value>
</interrupt>
<interrupt>
<name>LCD_TFT_1</name>
<description>LTDC global error interrupt</description>
<value>89</value>
</interrupt>
<interrupt>
<name>LCD_TFT_1</name>
<description>LTDC global error interrupt</description>
<value>89</value>
</interrupt>
<registers>
<cluster><dim>2</dim><dimIncrement>0x80</dimIncrement><dimIndex>1,2</dimIndex><name>LAYER%s</name><description>Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR</description><addressOffset>0x84</addressOffset><register>
<name>CR</name>
<displayName>L1CR</displayName>
<description>Layerx Control Register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLUTEN</name>
<description>Color Look-Up Table Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CLUTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Color look-up table disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Color look-up table enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>COLKEN</name>
<description>Color Keying Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>COLKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Color keying disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Color keying enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LEN</name>
<description>Layer Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Layer disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Layer enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>WHPCR</name>
<displayName>L1WHPCR</displayName>
<description>Layerx Window Horizontal Position
Configuration Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WHSPPOS</name>
<description>Window Horizontal Stop
Position</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
<field>
<name>WHSTPOS</name>
<description>Window Horizontal Start
Position</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>WVPCR</name>
<displayName>L1WVPCR</displayName>
<description>Layerx Window Vertical Position
Configuration Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WVSPPOS</name>
<description>Window Vertical Stop
Position</description>
<bitOffset>16</bitOffset>
<bitWidth>11</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint>
</field>
<field>
<name>WVSTPOS</name>
<description>Window Vertical Start
Position</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CKCR</name>
<displayName>L1CKCR</displayName>
<description>Layerx Color Keying Configuration
Register</description>
<addressOffset>0xc</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CKRED</name>
<description>Color Key Red value</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>CKGREEN</name>
<description>Color Key Green value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>CKBLUE</name>
<description>Color Key Blue value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>PFCR</name>
<displayName>L1PFCR</displayName>
<description>Layerx Pixel Format Configuration
Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PF</name>
<description>Pixel Format</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>PF</name><usage>read-write</usage><enumeratedValue><name>ARGB8888</name><description>ARGB8888</description><value>0</value></enumeratedValue><enumeratedValue><name>RGB888</name><description>RGB888</description><value>1</value></enumeratedValue><enumeratedValue><name>RGB565</name><description>RGB565</description><value>2</value></enumeratedValue><enumeratedValue><name>ARGB1555</name><description>ARGB1555</description><value>3</value></enumeratedValue><enumeratedValue><name>ARGB4444</name><description>ARGB4444</description><value>4</value></enumeratedValue><enumeratedValue><name>L8</name><description>L8 (8-bit luminance)</description><value>5</value></enumeratedValue><enumeratedValue><name>AL44</name><description>AL44 (4-bit alpha, 4-bit luminance)</description><value>6</value></enumeratedValue><enumeratedValue><name>AL88</name><description>AL88 (8-bit alpha, 8-bit luminance)</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CACR</name>
<displayName>L1CACR</displayName>
<description>Layerx Constant Alpha Configuration
Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CONSTA</name>
<description>Constant Alpha</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>DCCR</name>
<displayName>L1DCCR</displayName>
<description>Layerx Default Color Configuration
Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DCALPHA</name>
<description>Default Color Alpha</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>DCRED</name>
<description>Default Color Red</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>DCGREEN</name>
<description>Default Color Green</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>DCBLUE</name>
<description>Default Color Blue</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>BFCR</name>
<displayName>L1BFCR</displayName>
<description>Layerx Blending Factors Configuration
Register</description>
<addressOffset>0x1c</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000607</resetValue>
<fields>
<field>
<name>BF1</name>
<description>Blending Factor 1</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>BF1</name><usage>read-write</usage><enumeratedValue><name>Constant</name><description>BF1 = constant alpha</description><value>4</value></enumeratedValue><enumeratedValue><name>Pixel</name><description>BF1 = pixel alpha * constant alpha</description><value>6</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BF2</name>
<description>Blending Factor 2</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>BF2</name><usage>read-write</usage><enumeratedValue><name>Constant</name><description>BF2 = 1 - constant alpha</description><value>5</value></enumeratedValue><enumeratedValue><name>Pixel</name><description>BF2 = 1 - pixel alpha * constant alpha</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CFBAR</name>
<displayName>L1CFBAR</displayName>
<description>Layerx Color Frame Buffer Address
Register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CFBADD</name>
<description>Color Frame Buffer Start
Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CFBLR</name>
<displayName>L1CFBLR</displayName>
<description>Layerx Color Frame Buffer Length
Register</description>
<addressOffset>0x2c</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CFBP</name>
<description>Color Frame Buffer Pitch in
bytes</description>
<bitOffset>16</bitOffset>
<bitWidth>13</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>8191</maximum></range></writeConstraint>
</field>
<field>
<name>CFBLL</name>
<description>Color Frame Buffer Line
Length</description>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>8191</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CFBLNR</name>
<displayName>L1CFBLNR</displayName>
<description>Layerx ColorFrame Buffer Line Number
Register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CFBLNBR</name>
<description>Frame Buffer Line Number</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CLUTWR</name>
<displayName>L1CLUTWR</displayName>
<description>Layerx CLUT Write Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLUTADD</name>
<description>CLUT Address</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>RED</name>
<description>Red value</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>GREEN</name>
<description>Green value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field>
<name>BLUE</name>
<description>Blue value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
</cluster><register>
<name>SSCR</name>
<displayName>SSCR</displayName>
<description>Synchronization Size Configuration
Register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HSW</name>
<description>Horizontal Synchronization Width (in
units of pixel clock period)</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
<field>
<name>VSH</name>
<description>Vertical Synchronization Height (in
units of horizontal scan line)</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>BPCR</name>
<displayName>BPCR</displayName>
<description>Back Porch Configuration
Register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AHBP</name>
<description>Accumulated Horizontal back porch (in
units of pixel clock period)</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
<field>
<name>AVBP</name>
<description>Accumulated Vertical back porch (in
units of horizontal scan line)</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>AWCR</name>
<displayName>AWCR</displayName>
<description>Active Width Configuration
Register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AAW</name>
<description>Accumulated Active Width (in units of pixel clock period)</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
<field>
<name>AAH</name>
<description>Accumulated Active Height (in units of
horizontal scan line)</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>TWCR</name>
<displayName>TWCR</displayName>
<description>Total Width Configuration
Register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOTALW</name>
<description>Total Width (in units of pixel clock
period)</description>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
<field>
<name>TOTALH</name>
<description>Total Height (in units of horizontal
scan line)</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>GCR</name>
<displayName>GCR</displayName>
<description>Global Control Register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x00002220</resetValue>
<fields>
<field>
<name>HSPOL</name>
<description>Horizontal Synchronization
Polarity</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>HSPOL</name><usage>read-write</usage><enumeratedValue><name>ActiveLow</name><description>Horizontal synchronization polarity is active low</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveHigh</name><description>Horizontal synchronization polarity is active high</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>VSPOL</name>
<description>Vertical Synchronization
Polarity</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>VSPOL</name><usage>read-write</usage><enumeratedValue><name>ActiveLow</name><description>Vertical synchronization polarity is active low</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveHigh</name><description>Vertical synchronization polarity is active high</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DEPOL</name>
<description>Data Enable Polarity</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>DEPOL</name><usage>read-write</usage><enumeratedValue><name>ActiveLow</name><description>Data enable polarity is active low</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveHigh</name><description>Data enable polarity is active high</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PCPOL</name>
<description>Pixel Clock Polarity</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>PCPOL</name><usage>read-write</usage><enumeratedValue><name>RisingEdge</name><description>Pixel clock on rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>FallingEdge</name><description>Pixel clock on falling edge</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DEN</name>
<description>Dither Enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>DEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Dither disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Dither enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DRW</name>
<description>Dither Red Width</description>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DGW</name>
<description>Dither Green Width</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DBW</name>
<description>Dither Blue Width</description>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
<access>read-only</access>
</field>
<field>
<name>LTDCEN</name>
<description>LCD-TFT controller enable
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>LTDCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>LCD-TFT controller disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>LCD-TFT controller enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SRCR</name>
<displayName>SRCR</displayName>
<description>Shadow Reload Configuration
Register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VBR</name>
<description>Vertical Blanking Reload</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>VBR</name><usage>read-write</usage><enumeratedValue><name>Reload</name><description>The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area).</description><value>1</value></enumeratedValue><enumeratedValue><name>NoEffect</name><description>This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>IMR</name>
<description>Immediate Reload</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>IMR</name><usage>read-write</usage><enumeratedValue><name>Reload</name><description>The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload</description><value>1</value></enumeratedValue><enumeratedValue><name>NoEffect</name><description>This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)</description><value>0</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>BCCR</name>
<displayName>BCCR</displayName>
<description>Background Color Configuration
Register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field><name>BCBLUE</name><description>Background color blue value</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field><name>BCGREEN</name><description>Background color green value</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
<field><name>BCRED</name><description>Background color red value</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>IER</name>
<displayName>IER</displayName>
<description>Interrupt Enable Register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RRIE</name>
<description>Register Reload interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Register reload interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Register reload interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TERRIE</name>
<description>Transfer Error Interrupt
Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TERRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Transfer error interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Transfer error interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FUIE</name>
<description>FIFO Underrun Interrupt
Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FUIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>FIFO underrun interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>FIFO underrun interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LIE</name>
<description>Line Interrupt Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Line interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Line interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt Status Register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RRIF</name>
<description>Register Reload Interrupt
Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>RRIF</name><usage>read-write</usage><enumeratedValue><name>NoReload</name><description>No register reload</description><value>0</value></enumeratedValue><enumeratedValue><name>Reload</name><description>Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TERRIF</name>
<description>Transfer Error interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>TERRIF</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No transfer error</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>Transfer error interrupt generated when a bus error occurs</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FUIF</name>
<description>FIFO Underrun Interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FUIF</name><usage>read-write</usage><enumeratedValue><name>NoUnderrun</name><description>No FIFO underrun</description><value>0</value></enumeratedValue><enumeratedValue><name>Underrun</name><description>FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LIF</name>
<description>Line Interrupt flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LIF</name><usage>read-write</usage><enumeratedValue><name>NotReached</name><description>Programmed line not reached</description><value>0</value></enumeratedValue><enumeratedValue><name>Reached</name><description>Line interrupt generated when a programmed line is reached</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<displayName>ICR</displayName>
<description>Interrupt Clear Register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CRRIF</name>
<description>Clears Register Reload Interrupt
Flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CRRIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clears the RRIF flag in the ISR register</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CTERRIF</name>
<description>Clears the Transfer Error Interrupt
Flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CTERRIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clears the TERRIF flag in the ISR register</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CFUIF</name>
<description>Clears the FIFO Underrun Interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CFUIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clears the FUIF flag in the ISR register</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CLIF</name>
<description>Clears the Line Interrupt
Flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CLIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clears the LIF flag in the ISR register</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>LIPCR</name>
<displayName>LIPCR</displayName>
<description>Line Interrupt Position Configuration
Register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LIPOS</name>
<description>Line Interrupt Position</description>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>CPSR</name>
<displayName>CPSR</displayName>
<description>Current Position Status
Register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CXPOS</name>
<description>Current X Position</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CYPOS</name>
<description>Current Y Position</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CDSR</name>
<displayName>CDSR</displayName>
<description>Current Display Status
Register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000000F</resetValue>
<fields>
<field>
<name>HSYNCS</name>
<description>Horizontal Synchronization display
Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>HSYNCS</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Currently not in HSYNC phase</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Currently in HSYNC phase</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>VSYNCS</name>
<description>Vertical Synchronization display
Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>VSYNCS</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Currently not in VSYNC phase</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Currently in VSYNC phase</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>HDES</name>
<description>Horizontal Data Enable display
Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>HDES</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Currently not in horizontal Data Enable phase</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Currently in horizontal Data Enable phase</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>VDES</name>
<description>Vertical Data Enable display
Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>VDES</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Currently not in vertical Data Enable phase</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Currently in vertical Data Enable phase</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SAI</name>
<description>Serial audio interface</description>
<groupName>SAI</groupName>
<baseAddress>0x40015800</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SAI1</name>
<description>SAI1 global interrupt</description>
<value>87</value>
</interrupt>
<interrupt>
<name>SAI1</name>
<description>SAI1 global interrupt</description>
<value>87</value>
</interrupt>
<registers>
<cluster><dim>2</dim><dimIncrement>0x20</dimIncrement><dimIndex>A,B</dimIndex><name>CH%s</name><description>Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR</description><addressOffset>0x4</addressOffset><register>
<name>CR1</name>
<displayName>ACR1</displayName>
<description>AConfiguration register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000040</resetValue>
<fields>
<field>
<name>MCKDIV</name>
<description>Master clock divider</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>NODIV</name>
<description>No divider</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>NODIV</name><usage>read-write</usage><enumeratedValue><name>MasterClock</name><description>MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value</description><value>0</value></enumeratedValue><enumeratedValue><name>NoDiv</name><description>MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA enable</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SAIEN</name>
<description>Audio block A enable</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SAIEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>SAI audio block disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>SAI audio block enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OUTDRIV</name>
<description>Output drive</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OUTDRIV</name><usage>read-write</usage><enumeratedValue><name>OnStart</name><description>Audio block output driven when SAIEN is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Immediately</name><description>Audio block output driven immediately after the setting of this bit</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MONO</name>
<description>Mono mode</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MONO</name><usage>read-write</usage><enumeratedValue><name>Stereo</name><description>Stereo mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Mono</name><description>Mono mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SYNCEN</name>
<description>Synchronization enable</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>SYNCEN</name><usage>read-write</usage><enumeratedValue><name>Asynchronous</name><description>audio sub-block in asynchronous mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Internal</name><description>audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode</description><value>1</value></enumeratedValue><enumeratedValue><name>External</name><description>audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CKSTR</name>
<description>Clock strobing edge</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CKSTR</name><usage>read-write</usage><enumeratedValue><name>FallingEdge</name><description>Data strobing edge is falling edge of SCK</description><value>0</value></enumeratedValue><enumeratedValue><name>RisingEdge</name><description>Data strobing edge is rising edge of SCK</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LSBFIRST</name>
<description>Least significant bit
first</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LSBFIRST</name><usage>read-write</usage><enumeratedValue><name>MsbFirst</name><description>Data are transferred with MSB first</description><value>0</value></enumeratedValue><enumeratedValue><name>LsbFirst</name><description>Data are transferred with LSB first</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DS</name>
<description>Data size</description>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>DS</name><usage>read-write</usage><enumeratedValue><name>Bit8</name><description>8 bits</description><value>2</value></enumeratedValue><enumeratedValue><name>Bit10</name><description>10 bits</description><value>3</value></enumeratedValue><enumeratedValue><name>Bit16</name><description>16 bits</description><value>4</value></enumeratedValue><enumeratedValue><name>Bit20</name><description>20 bits</description><value>5</value></enumeratedValue><enumeratedValue><name>Bit24</name><description>24 bits</description><value>6</value></enumeratedValue><enumeratedValue><name>Bit32</name><description>32 bits</description><value>7</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PRTCFG</name>
<description>Protocol configuration</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>PRTCFG</name><usage>read-write</usage><enumeratedValue><name>Free</name><description>Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol</description><value>0</value></enumeratedValue><enumeratedValue><name>Spdif</name><description>SPDIF protocol</description><value>1</value></enumeratedValue><enumeratedValue><name>Ac97</name><description>AC&#8217;97 protocol</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MODE</name>
<description>Audio block mode</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>MODE</name><usage>read-write</usage><enumeratedValue><name>MasterTx</name><description>Master transmitter</description><value>0</value></enumeratedValue><enumeratedValue><name>MasterRx</name><description>Master receiver</description><value>1</value></enumeratedValue><enumeratedValue><name>SlaveTx</name><description>Slave transmitter</description><value>2</value></enumeratedValue><enumeratedValue><name>SlaveRx</name><description>Slave receiver</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>ACR2</displayName>
<description>AConfiguration register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMP</name>
<description>Companding mode</description>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>COMP</name><usage>read-write</usage><enumeratedValue><name>NoCompanding</name><description>No companding algorithm</description><value>0</value></enumeratedValue><enumeratedValue><name>MuLaw</name><description>&#956;-Law algorithm</description><value>2</value></enumeratedValue><enumeratedValue><name>ALaw</name><description>A-Law algorithm</description><value>3</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CPL</name>
<description>Complement bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CPL</name><usage>read-write</usage><enumeratedValue><name>OnesComplement</name><description>1&#8217;s complement representation</description><value>0</value></enumeratedValue><enumeratedValue><name>TwosComplement</name><description>2&#8217;s complement representation</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MUTECN</name>
<description>Mute counter</description>
<bitOffset>7</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>MUTEVAL</name>
<description>Mute value</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MUTEVAL</name><usage>read-write</usage><enumeratedValue><name>SendZero</name><description>Bit value 0 is sent during the mute mode</description><value>0</value></enumeratedValue><enumeratedValue><name>SendLast</name><description>Last values are sent during the mute mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MUTE</name>
<description>Mute</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MUTE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No mute mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Mute mode enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TRIS</name>
<description>Tristate management on data
line</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FFLUSH</name>
<description>FIFO flush</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FFLUSH</name><usage>read-write</usage><enumeratedValue><name>NoFlush</name><description>No FIFO flush</description><value>0</value></enumeratedValue><enumeratedValue><name>Flush</name><description>FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FTH</name>
<description>FIFO threshold</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>FTH</name><usage>read-write</usage><enumeratedValue><name>Empty</name><description>FIFO empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Quarter1</name><description>1&#8260;4 FIFO</description><value>1</value></enumeratedValue><enumeratedValue><name>Quarter2</name><description>1&#8260;2 FIFO</description><value>2</value></enumeratedValue><enumeratedValue><name>Quarter3</name><description>3&#8260;4 FIFO</description><value>3</value></enumeratedValue><enumeratedValue><name>Full</name><description>FIFO full</description><value>4</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>FRCR</name>
<displayName>AFRCR</displayName>
<description>AFRCR</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000007</resetValue>
<fields>
<field>
<name>FSOFF</name>
<description>Frame synchronization
offset</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FSOFF</name><usage>read-write</usage><enumeratedValue><name>OnFirst</name><description>FS is asserted on the first bit of the slot 0</description><value>0</value></enumeratedValue><enumeratedValue><name>BeforeFirst</name><description>FS is asserted one bit before the first bit of the slot 0</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FSPOL</name>
<description>Frame synchronization
polarity</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FSPOL</name><usage>read-write</usage><enumeratedValue><name>FallingEdge</name><description>FS is active low (falling edge)</description><value>0</value></enumeratedValue><enumeratedValue><name>RisingEdge</name><description>FS is active high (rising edge)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FSDEF</name>
<description>Frame synchronization
definition</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FSALL</name>
<description>Frame synchronization active level
length</description>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>FRL</name>
<description>Frame length</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLOTR</name>
<displayName>ASLOTR</displayName>
<description>ASlot register</description>
<addressOffset>0xc</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLOTEN</name>
<description>Slot enable</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<enumeratedValues><name>SLOTEN</name><usage>read-write</usage><enumeratedValue><name>Inactive</name><description>Inactive slot</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Active slot</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>NBSLOT</name>
<description>Number of slots in an audio
frame</description>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SLOTSZ</name>
<description>Slot size</description>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues><name>SLOTSZ</name><usage>read-write</usage><enumeratedValue><name>DataSize</name><description>The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)</description><value>0</value></enumeratedValue><enumeratedValue><name>Bit16</name><description>16-bit</description><value>1</value></enumeratedValue><enumeratedValue><name>Bit32</name><description>32-bit</description><value>2</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FBOFF</name>
<description>First bit offset</description>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>IM</name>
<displayName>AIM</displayName>
<description>AInterrupt mask register2</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LFSDETIE</name>
<description>Late frame synchronization detection
interrupt enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LFSDETIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AFSDETIE</name>
<description>Anticipated frame synchronization
detection interrupt enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>AFSDETIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CNRDYIE</name>
<description>Codec not ready interrupt
enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CNRDYIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FREQIE</name>
<description>FIFO request interrupt
enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FREQIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WCKCFGIE</name>
<description>Wrong clock configuration interrupt
enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WCKCFGIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MUTEDETIE</name>
<description>Mute detection interrupt
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MUTEDETIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OVRUDRIE</name>
<description>Overrun/underrun interrupt
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OVRUDRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR</name>
<displayName>ASR</displayName>
<description>AStatus register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLVL</name>
<description>FIFO level threshold</description>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues><name>FLVLR</name><usage>read</usage><enumeratedValue><name>Empty</name><description>FIFO empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Quarter1</name><description>FIFO &lt;= 1&#8260;4 but not empty</description><value>1</value></enumeratedValue><enumeratedValue><name>Quarter2</name><description>1&#8260;4 &lt; FIFO &lt;= 1&#8260;2</description><value>2</value></enumeratedValue><enumeratedValue><name>Quarter3</name><description>1&#8260;2 &lt; FIFO &lt;= 3&#8260;4</description><value>3</value></enumeratedValue><enumeratedValue><name>Quarter4</name><description>3&#8260;4 &lt; FIFO but not full</description><value>4</value></enumeratedValue><enumeratedValue><name>Full</name><description>FIFO full</description><value>5</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>LFSDET</name>
<description>Late frame synchronization
detection</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LFSDETR</name><usage>read</usage><enumeratedValue><name>NoError</name><description>No error</description><value>0</value></enumeratedValue><enumeratedValue><name>NoSync</name><description>Frame synchronization signal is not present at the right time</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AFSDET</name>
<description>Anticipated frame synchronization
detection</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>AFSDETR</name><usage>read</usage><enumeratedValue><name>NoError</name><description>No error</description><value>0</value></enumeratedValue><enumeratedValue><name>EarlySync</name><description>Frame synchronization signal is detected earlier than expected</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CNRDY</name>
<description>Codec not ready</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CNRDYR</name><usage>read</usage><enumeratedValue><name>Ready</name><description>External AC&#8217;97 Codec is ready</description><value>0</value></enumeratedValue><enumeratedValue><name>NotReady</name><description>External AC&#8217;97 Codec is not ready</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FREQ</name>
<description>FIFO request</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>FREQR</name><usage>read</usage><enumeratedValue><name>NoRequest</name><description>No FIFO request</description><value>0</value></enumeratedValue><enumeratedValue><name>Request</name><description>FIFO request to read or to write the SAI_xDR</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>WCKCFG</name>
<description>Wrong clock configuration flag. This bit
is read only.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>WCKCFGR</name><usage>read</usage><enumeratedValue><name>Correct</name><description>Clock configuration is correct</description><value>0</value></enumeratedValue><enumeratedValue><name>Wrong</name><description>Clock configuration does not respect the rule concerning the frame length specification</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>MUTEDET</name>
<description>Mute detection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>MUTEDETR</name><usage>read</usage><enumeratedValue><name>NoMute</name><description>No MUTE detection on the SD input line</description><value>0</value></enumeratedValue><enumeratedValue><name>Mute</name><description>MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OVRUDR</name>
<description>Overrun / underrun</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>OVRUDRR</name><usage>read</usage><enumeratedValue><name>NoError</name><description>No overrun/underrun error</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Overrun/underrun error detection</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CLRFR</name>
<displayName>ACLRFR</displayName>
<description>AClear flag register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLFSDET</name>
<description>Clear late frame synchronization
detection flag</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CLFSDETW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the LFSDET flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CAFSDET</name>
<description>Clear anticipated frame synchronization
detection flag.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CAFSDETW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the AFSDET flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CCNRDY</name>
<description>Clear codec not ready flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CCNRDYW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the CNRDY flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CWCKCFG</name>
<description>Clear wrong clock configuration
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CWCKCFGW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the WCKCFG flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CMUTEDET</name>
<description>Mute detection flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>CMUTEDETW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the MUTEDET flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>COVRUDR</name>
<description>Clear overrun / underrun</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>COVRUDRW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the OVRUDR flag</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>ADR</displayName>
<description>AData register</description>
<addressOffset>0x1c</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</cluster></registers>
</peripheral>
<peripheral>
<name>DMA2D</name>
<description>DMA2D controller</description>
<groupName>DMA2D</groupName>
<baseAddress>0x4002B000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xC00</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DMA2D</name>
<description>DMA2D global interrupt</description>
<value>90</value>
</interrupt>
<interrupt>
<name>DMA2D</name>
<description>DMA2D global interrupt</description>
<value>90</value>
</interrupt>
<registers>
<register>
<name>CR</name>
<displayName>CR</displayName>
<description>control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MODE</name>
<description>DMA2D mode</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CEIE</name>
<description>Configuration Error Interrupt
Enable</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIE</name>
<description>CLUT transfer complete interrupt
enable</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAEIE</name>
<description>CLUT access error interrupt
enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TWIE</name>
<description>Transfer watermark interrupt
enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIE</name>
<description>Transfer complete interrupt
enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIE</name>
<description>Transfer error interrupt
enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABORT</name>
<description>Abort</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SUSP</name>
<description>Suspend</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>START</name>
<description>Start</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ISR</name>
<displayName>ISR</displayName>
<description>Interrupt Status Register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CEIF</name>
<description>Configuration error interrupt
flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF</name>
<description>CLUT transfer complete interrupt
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAEIF</name>
<description>CLUT access error interrupt
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TWIF</name>
<description>Transfer watermark interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TCIF</name>
<description>Transfer complete interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEIF</name>
<description>Transfer error interrupt
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IFCR</name>
<displayName>IFCR</displayName>
<description>interrupt flag clear register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CCEIF</name>
<description>Clear configuration error interrupt
flag</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCTCIF</name>
<description>Clear CLUT transfer complete interrupt
flag</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAECIF</name>
<description>Clear CLUT access error interrupt
flag</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTWIF</name>
<description>Clear transfer watermark interrupt
flag</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTCIF</name>
<description>Clear transfer complete interrupt
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTEIF</name>
<description>Clear Transfer error interrupt
flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGMAR</name>
<displayName>FGMAR</displayName>
<description>foreground memory address
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGOR</name>
<displayName>FGOR</displayName>
<description>foreground offset register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LO</name>
<description>Line offset</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGMAR</name>
<displayName>BGMAR</displayName>
<description>background memory address
register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGOR</name>
<displayName>BGOR</displayName>
<description>background offset register</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LO</name>
<description>Line offset</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGPFCCR</name>
<displayName>FGPFCCR</displayName>
<description>foreground PFC control
register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALPHA</name>
<description>Alpha value</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>AM</name>
<description>Alpha mode</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CS</name>
<description>CLUT size</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>START</name>
<description>Start</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCM</name>
<description>CLUT color mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CM</name>
<description>Color mode</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGCOLR</name>
<displayName>FGCOLR</displayName>
<description>foreground color register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RED</name>
<description>Red Value</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>GREEN</name>
<description>Green Value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BLUE</name>
<description>Blue Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGPFCCR</name>
<displayName>BGPFCCR</displayName>
<description>background PFC control
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALPHA</name>
<description>Alpha value</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>AM</name>
<description>Alpha mode</description>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CS</name>
<description>CLUT size</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>START</name>
<description>Start</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CCM</name>
<description>CLUT Color mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CM</name>
<description>Color mode</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGCOLR</name>
<displayName>BGCOLR</displayName>
<description>background color register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RED</name>
<description>Red Value</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>GREEN</name>
<description>Green Value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BLUE</name>
<description>Blue Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGCMAR</name>
<displayName>FGCMAR</displayName>
<description>foreground CLUT memory address
register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGCMAR</name>
<displayName>BGCMAR</displayName>
<description>background CLUT memory address
register</description>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPFCCR</name>
<displayName>OPFCCR</displayName>
<description>output PFC control register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CM</name>
<description>Color mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>OCOLR</name>
<displayName>OCOLR</displayName>
<description>output color register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APLHA</name>
<description>Alpha Channel Value</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RED</name>
<description>Red Value</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>GREEN</name>
<description>Green Value</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BLUE</name>
<description>Blue Value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>OMAR</name>
<displayName>OMAR</displayName>
<description>output memory address register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MA</name>
<description>Memory Address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OOR</name>
<displayName>OOR</displayName>
<description>output offset register</description>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LO</name>
<description>Line Offset</description>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>NLR</name>
<displayName>NLR</displayName>
<description>number of line register</description>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PL</name>
<description>Pixel per lines</description>
<bitOffset>16</bitOffset>
<bitWidth>14</bitWidth>
</field>
<field>
<name>NL</name>
<description>Number of lines</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>LWR</name>
<displayName>LWR</displayName>
<description>line watermark register</description>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LW</name>
<description>Line watermark</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>AMTCR</name>
<displayName>AMTCR</displayName>
<description>AHB master timer configuration
register</description>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT</name>
<description>Dead Time</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>EN</name>
<description>Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FGCLUT</name>
<displayName>FGCLUT</displayName>
<description>FGCLUT</description>
<addressOffset>0x400</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APLHA</name>
<description>APLHA</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RED</name>
<description>RED</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>GREEN</name>
<description>GREEN</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BLUE</name>
<description>BLUE</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BGCLUT</name>
<displayName>BGCLUT</displayName>
<description>BGCLUT</description>
<addressOffset>0x800</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APLHA</name>
<description>APLHA</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RED</name>
<description>RED</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>GREEN</name>
<description>GREEN</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BLUE</name>
<description>BLUE</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="I2C1">
<name>I2C3</name>
<baseAddress>0x40005C00</baseAddress>
<interrupt>
<name>I2C3_EV</name>
<description>I2C3 event interrupt</description>
<value>72</value>
</interrupt>
<interrupt>
<name>I2C3_EV</name>
<description>I2C3 event interrupt</description>
<value>72</value>
</interrupt>
<interrupt>
<name>I2C3_ER</name>
<description>I2C3 error interrupt</description>
<value>73</value>
</interrupt>
<interrupt>
<name>I2C3_ER</name>
<description>I2C3 error interrupt</description>
<value>73</value>
</interrupt>
</peripheral>
<peripheral derivedFrom="I2C1">
<name>I2C2</name>
<baseAddress>0x40005800</baseAddress>
<interrupt>
<name>I2C2_EV</name>
<description>I2C2 event interrupt</description>
<value>33</value>
</interrupt>
<interrupt>
<name>I2C2_EV</name>
<description>I2C2 event interrupt</description>
<value>33</value>
</interrupt>
<interrupt>
<name>I2C2_ER</name>
<description>I2C2 error interrupt</description>
<value>34</value>
</interrupt>
<interrupt>
<name>I2C2_ER</name>
<description>I2C2 error interrupt</description>
<value>34</value>
</interrupt>
</peripheral>
<peripheral>
<name>I2C1</name>
<description>Inter-integrated circuit</description>
<groupName>I2C</groupName>
<baseAddress>0x40005400</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x400</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C1_EV</name>
<description>I2C1 event interrupt</description>
<value>31</value>
</interrupt>
<interrupt>
<name>I2C1_EV</name>
<description>I2C1 event interrupt</description>
<value>31</value>
</interrupt>
<interrupt>
<name>I2C1_ER</name>
<description>I2C1 error interrupt</description>
<value>32</value>
</interrupt>
<interrupt>
<name>I2C1_ER</name>
<description>I2C1 error interrupt</description>
<value>32</value>
</interrupt>
<registers>
<register>
<name>CR1</name>
<displayName>CR1</displayName>
<description>Control register 1</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>SWRST</name>
<description>Software reset</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SWRST</name><usage>read-write</usage><enumeratedValue><name>NotReset</name><description>I2C peripheral not under reset</description><value>0</value></enumeratedValue><enumeratedValue><name>Reset</name><description>I2C peripheral under reset</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ALERT</name>
<description>SMBus alert</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ALERT</name><usage>read-write</usage><enumeratedValue><name>Release</name><description>SMBA pin released high</description><value>0</value></enumeratedValue><enumeratedValue><name>Drive</name><description>SMBA pin driven low</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PEC</name>
<description>Packet error checking</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PEC</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No PEC transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>PEC transfer</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>POS</name>
<description>Acknowledge/PEC Position (for data
reception)</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>POS</name><usage>read-write</usage><enumeratedValue><name>Current</name><description>ACK bit controls the (N)ACK of the current byte being received</description><value>0</value></enumeratedValue><enumeratedValue><name>Next</name><description>ACK bit controls the (N)ACK of the next byte to be received</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ACK</name>
<description>Acknowledge enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ACK</name><usage>read-write</usage><enumeratedValue><name>NAK</name><description>No acknowledge returned</description><value>0</value></enumeratedValue><enumeratedValue><name>ACK</name><description>Acknowledge returned after a byte is received</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>STOP</name>
<description>Stop generation</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>STOP</name><usage>read-write</usage><enumeratedValue><name>NoStop</name><description>No Stop generation</description><value>0</value></enumeratedValue><enumeratedValue><name>Stop</name><description>In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>START</name>
<description>Start generation</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>START</name><usage>read-write</usage><enumeratedValue><name>NoStart</name><description>No Start generation</description><value>0</value></enumeratedValue><enumeratedValue><name>Start</name><description>In master mode: repeated start generation, in slave mode: start generation when bus is free</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>NOSTRETCH</name>
<description>Clock stretching disable (Slave
mode)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>NOSTRETCH</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Clock stretching enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Clock stretching disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ENGC</name>
<description>General call enable</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ENGC</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>General call disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>General call enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ENPEC</name>
<description>PEC enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ENPEC</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>PEC calculation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>PEC calculation enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ENARP</name>
<description>ARP enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ENARP</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ARP disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ARP enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SMBTYPE</name>
<description>SMBus type</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SMBTYPE</name><usage>read-write</usage><enumeratedValue><name>Device</name><description>SMBus Device</description><value>0</value></enumeratedValue><enumeratedValue><name>Host</name><description>SMBus Host</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SMBUS</name>
<description>SMBus mode</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>SMBUS</name><usage>read-write</usage><enumeratedValue><name>I2C</name><description>I2C Mode</description><value>0</value></enumeratedValue><enumeratedValue><name>SMBus</name><description>SMBus</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PE</name>
<description>Peripheral enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Peripheral disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Peripheral enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>CR2</name>
<displayName>CR2</displayName>
<description>Control register 2</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>LAST</name>
<description>DMA last transfer</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>LAST</name><usage>read-write</usage><enumeratedValue><name>NotLast</name><description>Next DMA EOT is not the last transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>Last</name><description>Next DMA EOT is the last transfer</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DMAEN</name>
<description>DMA requests enable</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DMAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA requests disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA request enabled when TxE=1 or RxNE=1</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ITBUFEN</name>
<description>Buffer interrupt enable</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ITBUFEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TxE=1 or RxNE=1 does not generate any interrupt</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TxE=1 or RxNE=1 generates Event interrupt</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ITEVTEN</name>
<description>Event interrupt enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ITEVTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Event interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Event interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ITERREN</name>
<description>Error interrupt enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ITERREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Error interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Error interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>FREQ</name>
<description>Peripheral clock frequency</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<writeConstraint><range><minimum>2</minimum><maximum>50</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>OAR1</name>
<displayName>OAR1</displayName>
<description>Own address register 1</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADDMODE</name>
<description>Addressing mode (slave
mode)</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ADDMODE</name><usage>read-write</usage><enumeratedValue><name>ADD7</name><description>7-bit slave address</description><value>0</value></enumeratedValue><enumeratedValue><name>ADD10</name><description>10-bit slave address</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field><name>ADD</name><description>Interface address</description><bitOffset>0</bitOffset><bitWidth>10</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>1023</maximum></range></writeConstraint>
</field></fields>
</register>
<register>
<name>OAR2</name>
<displayName>OAR2</displayName>
<description>Own address register 2</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>ADD2</name>
<description>Interface address</description>
<bitOffset>1</bitOffset>
<bitWidth>7</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>127</maximum></range></writeConstraint>
</field>
<field>
<name>ENDUAL</name>
<description>Dual addressing mode
enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ENDUAL</name><usage>read-write</usage><enumeratedValue><name>Single</name><description>Single addressing mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Dual</name><description>Dual addressing mode</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>DR</name>
<displayName>DR</displayName>
<description>Data register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DR</name>
<description>8-bit data register</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>SR1</name>
<displayName>SR1</displayName>
<description>Status register 1</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>SMBALERT</name>
<description>SMBus alert</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>SMBALERT</name><usage>read-write</usage><enumeratedValue><name>NoAlert</name><description>No SMBALERT occured</description><value>0</value></enumeratedValue><enumeratedValue><name>Alert</name><description>SMBALERT occurred</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TIMEOUT</name>
<description>Timeout or Tlow error</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>TIMEOUT</name><usage>read-write</usage><enumeratedValue><name>NoTimeout</name><description>No Timeout error</description><value>0</value></enumeratedValue><enumeratedValue><name>Timeout</name><description>SCL remained LOW for 25 ms</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>PECERR</name>
<description>PEC Error in reception</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>PECERR</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>no PEC error: receiver returns ACK after PEC reception (if ACK=1)</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>PEC error: receiver returns NACK after PEC reception (whatever ACK)</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>OVR</name>
<description>Overrun/Underrun</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>OVR</name><usage>read-write</usage><enumeratedValue><name>NoOverrun</name><description>No overrun/underrun occured</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Overrun/underrun occured</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>AF</name>
<description>Acknowledge failure</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>AF</name><usage>read-write</usage><enumeratedValue><name>NoFailure</name><description>No acknowledge failure</description><value>0</value></enumeratedValue><enumeratedValue><name>Failure</name><description>Acknowledge failure</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ARLO</name>
<description>Arbitration lost (master
mode)</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>ARLO</name><usage>read-write</usage><enumeratedValue><name>NoLost</name><description>No Arbitration Lost detected</description><value>0</value></enumeratedValue><enumeratedValue><name>Lost</name><description>Arbitration Lost detected</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>BERR</name>
<description>Bus error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues><name>BERR</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No misplaced Start or Stop condition</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>Misplaced Start or Stop condition</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>TxE</name>
<description>Data register empty
(transmitters)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>TxE</name><usage>read-write</usage><enumeratedValue><name>NotEmpty</name><description>Data register not empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Empty</name><description>Data register empty</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>RxNE</name>
<description>Data register not empty
(receivers)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>RxNE</name><usage>read-write</usage><enumeratedValue><name>Empty</name><description>Data register empty</description><value>0</value></enumeratedValue><enumeratedValue><name>NotEmpty</name><description>Data register not empty</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>STOPF</name>
<description>Stop detection (slave
mode)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>STOPF</name><usage>read-write</usage><enumeratedValue><name>NoStop</name><description>No Stop condition detected</description><value>0</value></enumeratedValue><enumeratedValue><name>Stop</name><description>Stop condition detected</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ADD10</name>
<description>10-bit header sent (Master
mode)</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BTF</name>
<description>Byte transfer finished</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>BTF</name><usage>read-write</usage><enumeratedValue><name>NotFinished</name><description>Data byte transfer not done</description><value>0</value></enumeratedValue><enumeratedValue><name>Finished</name><description>Data byte transfer successful</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ADDR</name>
<description>Address sent (master mode)/matched
(slave mode)</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>ADDR</name><usage>read-write</usage><enumeratedValue><name>NotMatch</name><description>Adress mismatched or not received</description><value>0</value></enumeratedValue><enumeratedValue><name>Match</name><description>Received slave address matched with one of the enabled slave addresses</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>SB</name>
<description>Start bit (Master mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues><name>SB</name><usage>read-write</usage><enumeratedValue><name>NoStart</name><description>No Start condition</description><value>0</value></enumeratedValue><enumeratedValue><name>Start</name><description>Start condition generated</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SR2</name>
<displayName>SR2</displayName>
<description>Status register 2</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>PEC</name>
<description>acket error checking
register</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DUALF</name>
<description>Dual flag (Slave mode)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBHOST</name>
<description>SMBus host header (Slave
mode)</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SMBDEFAULT</name>
<description>SMBus device default address (Slave
mode)</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GENCALL</name>
<description>General call address (Slave
mode)</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRA</name>
<description>Transmitter/receiver</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>Bus busy</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSL</name>
<description>Master/slave</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>Clock control register</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>F_S</name>
<description>I2C master mode selection</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>F_S</name><usage>read-write</usage><enumeratedValue><name>Standard</name><description>Standard mode I2C</description><value>0</value></enumeratedValue><enumeratedValue><name>Fast</name><description>Fast mode I2C</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>DUTY</name>
<description>Fast mode duty cycle</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>DUTY</name><usage>read-write</usage><enumeratedValue><name>Duty2_1</name><description>Duty cycle t_low/t_high = 2/1</description><value>0</value></enumeratedValue><enumeratedValue><name>Duty16_9</name><description>Duty cycle t_low/t_high = 16/9</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>CCR</name>
<description>Clock control register in Fast/Standard
mode (Master mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<writeConstraint><range><minimum>1</minimum><maximum>4095</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>TRISE</name>
<displayName>TRISE</displayName>
<description>TRISE register</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0002</resetValue>
<fields>
<field>
<name>TRISE</name>
<description>Maximum rise time in Fast/Standard mode
(Master mode)</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint>
</field>
</fields>
</register>
<register>
<name>FLTR</name>
<displayName>FLTR</displayName>
<description>I2C FLTR register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000</resetValue>
<fields>
<field>
<name>DNF</name>
<description>Digital noise filter</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues><name>DNF</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>Digital filter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Filter1</name><description>Digital filter enabled and filtering capability up to 1 tI2CCLK</description><value>1</value></enumeratedValue><enumeratedValue><name>Filter2</name><description>Digital filter enabled and filtering capability up to 2 tI2CCLK</description><value>2</value></enumeratedValue><enumeratedValue><name>Filter3</name><description>Digital filter enabled and filtering capability up to 3 tI2CCLK</description><value>3</value></enumeratedValue><enumeratedValue><name>Filter4</name><description>Digital filter enabled and filtering capability up to 4 tI2CCLK</description><value>4</value></enumeratedValue><enumeratedValue><name>Filter5</name><description>Digital filter enabled and filtering capability up to 5 tI2CCLK</description><value>5</value></enumeratedValue><enumeratedValue><name>Filter6</name><description>Digital filter enabled and filtering capability up to 6 tI2CCLK</description><value>6</value></enumeratedValue><enumeratedValue><name>Filter7</name><description>Digital filter enabled and filtering capability up to 7 tI2CCLK</description><value>7</value></enumeratedValue><enumeratedValue><name>Filter8</name><description>Digital filter enabled and filtering capability up to 8 tI2CCLK</description><value>8</value></enumeratedValue><enumeratedValue><name>Filter9</name><description>Digital filter enabled and filtering capability up to 9 tI2CCLK</description><value>9</value></enumeratedValue><enumeratedValue><name>Filter10</name><description>Digital filter enabled and filtering capability up to 10 tI2CCLK</description><value>10</value></enumeratedValue><enumeratedValue><name>Filter11</name><description>Digital filter enabled and filtering capability up to 11 tI2CCLK</description><value>11</value></enumeratedValue><enumeratedValue><name>Filter12</name><description>Digital filter enabled and filtering capability up to 12 tI2CCLK</description><value>12</value></enumeratedValue><enumeratedValue><name>Filter13</name><description>Digital filter enabled and filtering capability up to 13 tI2CCLK</description><value>13</value></enumeratedValue><enumeratedValue><name>Filter14</name><description>Digital filter enabled and filtering capability up to 14 tI2CCLK</description><value>14</value></enumeratedValue><enumeratedValue><name>Filter15</name><description>Digital filter enabled and filtering capability up to 15 tI2CCLK</description><value>15</value></enumeratedValue></enumeratedValues>
</field>
<field>
<name>ANOFF</name>
<description>Analog noise filter OFF</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues><name>ANOFF</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Analog noise filter enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Analog noise filter disabled</description><value>1</value></enumeratedValue></enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FPU</name>
<description>Floting point unit</description>
<groupName>FPU</groupName>
<baseAddress>0xE000EF34</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xD</size>
<usage>registers</usage>
</addressBlock>
<interrupt><name>FPU</name><description>Floating point unit</description><value>81</value></interrupt>
<registers>
<register>
<name>FPCCR</name>
<displayName>FPCCR</displayName>
<description>Floating-point context control
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSPACT</name>
<description>LSPACT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USER</name>
<description>USER</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THREAD</name>
<description>THREAD</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFRDY</name>
<description>HFRDY</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMRDY</name>
<description>MMRDY</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFRDY</name>
<description>BFRDY</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONRDY</name>
<description>MONRDY</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSPEN</name>
<description>LSPEN</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ASPEN</name>
<description>ASPEN</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPCAR</name>
<displayName>FPCAR</displayName>
<description>Floating-point context address
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDRESS</name>
<description>Location of unpopulated
floating-point</description>
<bitOffset>3</bitOffset>
<bitWidth>29</bitWidth>
</field>
</fields>
</register>
<register>
<name>FPSCR</name>
<displayName>FPSCR</displayName>
<description>Floating-point status control
register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IOC</name>
<description>Invalid operation cumulative exception
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DZC</name>
<description>Division by zero cumulative exception
bit.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OFC</name>
<description>Overflow cumulative exception
bit</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UFC</name>
<description>Underflow cumulative exception
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IXC</name>
<description>Inexact cumulative exception
bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDC</name>
<description>Input denormal cumulative exception
bit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RMode</name>
<description>Rounding Mode control
field</description>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FZ</name>
<description>Flush-to-zero mode control
bit:</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DN</name>
<description>Default NaN mode control
bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHP</name>
<description>Alternative half-precision control
bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>V</name>
<description>Overflow condition code
flag</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C</name>
<description>Carry condition code flag</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>Z</name>
<description>Zero condition code flag</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>N</name>
<description>Negative condition code
flag</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MPU</name>
<description>Memory protection unit</description>
<groupName>MPU</groupName>
<baseAddress>0xE000ED90</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x15</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>TYPER</name>
<displayName>TYPER</displayName>
<description>MPU type register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0X00000800</resetValue>
<fields>
<field>
<name>SEPARATE</name>
<description>Separate flag</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DREGION</name>
<description>Number of MPU data regions</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>IREGION</name>
<description>Number of MPU instruction
regions</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>MPU control register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Enables the MPU</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HFNMIENA</name>
<description>Enables the operation of MPU during hard
fault</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRIVDEFENA</name>
<description>Enable priviliged software access to
default memory map</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RNR</name>
<displayName>RNR</displayName>
<description>MPU region number register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>REGION</name>
<description>MPU region</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RBAR</name>
<displayName>RBAR</displayName>
<description>MPU region base address
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>REGION</name>
<description>MPU region field</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>VALID</name>
<description>MPU region number valid</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADDR</name>
<description>Region base address field</description>
<bitOffset>5</bitOffset>
<bitWidth>27</bitWidth>
</field>
</fields>
</register>
<register>
<name>RASR</name>
<displayName>RASR</displayName>
<description>MPU region attribute and size
register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Region enable bit.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIZE</name>
<description>Size of the MPU protection
region</description>
<bitOffset>1</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SRD</name>
<description>Subregion disable bits</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>B</name>
<description>memory attribute</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>C</name>
<description>memory attribute</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>S</name>
<description>Shareable memory attribute</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TEX</name>
<description>memory attribute</description>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>AP</name>
<description>Access permission</description>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>XN</name>
<description>Instruction access disable
bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>STK</name>
<description>SysTick timer</description>
<groupName>STK</groupName>
<baseAddress>0xE000E010</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x11</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<displayName>CTRL</displayName>
<description>SysTick control and status
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<description>Counter enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TICKINT</name>
<description>SysTick exception request
enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKSOURCE</name>
<description>Clock source selection</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COUNTFLAG</name>
<description>COUNTFLAG</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LOAD</name>
<displayName>LOAD</displayName>
<description>SysTick reload value register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>RELOAD</name>
<description>RELOAD value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>VAL</name>
<displayName>VAL</displayName>
<description>SysTick current value register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>CURRENT</name>
<description>Current counter value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CALIB</name>
<displayName>CALIB</displayName>
<description>SysTick calibration value
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0X00000000</resetValue>
<fields>
<field>
<name>TENMS</name>
<description>Calibration value</description>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>SKEW</name>
<description>SKEW flag: Indicates whether the TENMS
value is exact</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOREF</name>
<description>NOREF flag. Reads as zero</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCB</name>
<description>System control block</description>
<groupName>SCB</groupName>
<baseAddress>0xE000ED00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x41</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CPUID</name>
<displayName>CPUID</displayName>
<description>CPUID base register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x410FC241</resetValue>
<fields>
<field>
<name>Revision</name>
<description>Revision number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PartNo</name>
<description>Part number of the
processor</description>
<bitOffset>4</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>Constant</name>
<description>Reads as 0xF</description>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Variant</name>
<description>Variant number</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>Implementer</name>
<description>Implementer code</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ICSR</name>
<displayName>ICSR</displayName>
<description>Interrupt control and state
register</description>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTACTIVE</name>
<description>Active vector</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>RETTOBASE</name>
<description>Return to base level</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTPENDING</name>
<description>Pending vector</description>
<bitOffset>12</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ISRPENDING</name>
<description>Interrupt pending flag</description>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSTCLR</name>
<description>SysTick exception clear-pending
bit</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSTSET</name>
<description>SysTick exception set-pending
bit</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVCLR</name>
<description>PendSV clear-pending bit</description>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVSET</name>
<description>PendSV set-pending bit</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NMIPENDSET</name>
<description>NMI set-pending bit.</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>VTOR</name>
<displayName>VTOR</displayName>
<description>Vector table offset register</description>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TBLOFF</name>
<description>Vector table base offset
field</description>
<bitOffset>9</bitOffset>
<bitWidth>21</bitWidth>
</field>
</fields>
</register>
<register>
<name>AIRCR</name>
<displayName>AIRCR</displayName>
<description>Application interrupt and reset control
register</description>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTRESET</name>
<description>VECTRESET</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTCLRACTIVE</name>
<description>VECTCLRACTIVE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSRESETREQ</name>
<description>SYSRESETREQ</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRIGROUP</name>
<description>PRIGROUP</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>ENDIANESS</name>
<description>ENDIANESS</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>VECTKEYSTAT</name>
<description>Register key</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCR</name>
<displayName>SCR</displayName>
<description>System control register</description>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLEEPONEXIT</name>
<description>SLEEPONEXIT</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLEEPDEEP</name>
<description>SLEEPDEEP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEVEONPEND</name>
<description>Send Event on Pending bit</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CCR</name>
<displayName>CCR</displayName>
<description>Configuration and control
register</description>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NONBASETHRDENA</name>
<description>Configures how the processor enters
Thread mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USERSETMPEND</name>
<description>USERSETMPEND</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNALIGN__TRP</name>
<description>UNALIGN_ TRP</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_0_TRP</name>
<description>DIV_0_TRP</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFHFNMIGN</name>
<description>BFHFNMIGN</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STKALIGN</name>
<description>STKALIGN</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR1</name>
<displayName>SHPR1</displayName>
<description>System handler priority
registers</description>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_4</name>
<description>Priority of system handler
4</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_5</name>
<description>Priority of system handler
5</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_6</name>
<description>Priority of system handler
6</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR2</name>
<displayName>SHPR2</displayName>
<description>System handler priority
registers</description>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_11</name>
<description>Priority of system handler
11</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHPR3</name>
<displayName>SHPR3</displayName>
<description>System handler priority
registers</description>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRI_14</name>
<description>Priority of system handler
14</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PRI_15</name>
<description>Priority of system handler
15</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHCRS</name>
<displayName>SHCRS</displayName>
<description>System handler control and state
register</description>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEMFAULTACT</name>
<description>Memory management fault exception active
bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTACT</name>
<description>Bus fault exception active
bit</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTACT</name>
<description>Usage fault exception active
bit</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVCALLACT</name>
<description>SVC call active bit</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MONITORACT</name>
<description>Debug monitor active bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PENDSVACT</name>
<description>PendSV exception active
bit</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SYSTICKACT</name>
<description>SysTick exception active
bit</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTPENDED</name>
<description>Usage fault exception pending
bit</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEMFAULTPENDED</name>
<description>Memory management fault exception
pending bit</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTPENDED</name>
<description>Bus fault exception pending
bit</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SVCALLPENDED</name>
<description>SVC call pending bit</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEMFAULTENA</name>
<description>Memory management fault enable
bit</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSFAULTENA</name>
<description>Bus fault enable bit</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USGFAULTENA</name>
<description>Usage fault enable bit</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFSR_UFSR_BFSR_MMFSR</name>
<displayName>CFSR_UFSR_BFSR_MMFSR</displayName>
<description>Configurable fault status
register</description>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IACCVIOL</name>
<description>Instruction access violation
flag</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUNSTKERR</name>
<description>Memory manager fault on unstacking for a
return from exception</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MSTKERR</name>
<description>Memory manager fault on stacking for
exception entry.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MLSPERR</name>
<description>MLSPERR</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MMARVALID</name>
<description>Memory Management Fault Address Register
(MMAR) valid flag</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IBUSERR</name>
<description>Instruction bus error</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRECISERR</name>
<description>Precise data bus error</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IMPRECISERR</name>
<description>Imprecise data bus error</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNSTKERR</name>
<description>Bus fault on unstacking for a return
from exception</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STKERR</name>
<description>Bus fault on stacking for exception
entry</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSPERR</name>
<description>Bus fault on floating-point lazy state
preservation</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BFARVALID</name>
<description>Bus Fault Address Register (BFAR) valid
flag</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNDEFINSTR</name>
<description>Undefined instruction usage
fault</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVSTATE</name>
<description>Invalid state usage fault</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INVPC</name>
<description>Invalid PC load usage
fault</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NOCP</name>
<description>No coprocessor usage
fault.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UNALIGNED</name>
<description>Unaligned access usage
fault</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIVBYZERO</name>
<description>Divide by zero usage fault</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HFSR</name>
<displayName>HFSR</displayName>
<description>Hard fault status register</description>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VECTTBL</name>
<description>Vector table hard fault</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCED</name>
<description>Forced hard fault</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEBUG_VT</name>
<description>Reserved for Debug use</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMFAR</name>
<displayName>MMFAR</displayName>
<description>Memory management fault address
register</description>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MMFAR</name>
<description>Memory management fault
address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BFAR</name>
<displayName>BFAR</displayName>
<description>Bus fault address register</description>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BFAR</name>
<description>Bus fault address</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AFSR</name>
<displayName>AFSR</displayName>
<description>Auxiliary fault status
register</description>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMPDEF</name>
<description>Implementation defined</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>NVIC_STIR</name>
<description>Nested vectored interrupt
controller</description>
<groupName>NVIC</groupName>
<baseAddress>0xE000EF00</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>STIR</name>
<displayName>STIR</displayName>
<description>Software trigger interrupt
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTID</name>
<description>Software generated interrupt
ID</description>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FPU_CPACR</name>
<description>Floating point unit CPACR</description>
<groupName>FPU</groupName>
<baseAddress>0xE000ED88</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CPACR</name>
<displayName>CPACR</displayName>
<description>Coprocessor access control
register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x0000000</resetValue>
<fields>
<field>
<name>CP</name>
<description>CP</description>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SCB_ACTRL</name>
<description>System control block ACTLR</description>
<groupName>SCB</groupName>
<baseAddress>0xE000E008</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>ACTRL</name>
<displayName>ACTRL</displayName>
<description>Auxiliary control register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DISMCYCINT</name>
<description>DISMCYCINT</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISDEFWBUF</name>
<description>DISDEFWBUF</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISFOLD</name>
<description>DISFOLD</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISFPCA</name>
<description>DISFPCA</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISOOFP</name>
<description>DISOOFP</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
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