STM32F429 1.2 STM32F429 CM4 r1p0 little false false 4 false 8 32 0x20 0x0 0xFFFFFFFF RNG Random number generator RNG 0x50060800 0x0 0x400 registers FPU FPU interrupt 81 FPU FPU interrupt 81 CR CR control register 0x0 0x20 read-write 0x00000000 IE Interrupt enable 3 1 IEread-writeDisabledRNG interrupt is disabled0EnabledRNG interrupt is enabled1 RNGEN Random number generator enable 2 1 RNGENread-writeDisabledRandom number generator is disabled0EnabledRandom number generator is enabled1 SR SR status register 0x4 0x20 0x00000000 SEIS Seed error interrupt status 6 1 read-write CEIS Clock error interrupt status 5 1 read-write SECS Seed error current status 2 1 read-only CECS Clock error current status 1 1 read-only DRDY Data ready 0 1 read-only DR DR data register 0x8 0x20 read-only 0x00000000 RNDATA Random data 0 32 HASH Hash processor HASH 0x50060400 0x0 0x400 registers HASH_RNG Hash and Rng global interrupt 80 HASH_RNG Hash and Rng global interrupt 80 CR CR control register 0x0 0x20 0x00000000 INIT Initialize message digest calculation 2 1 write-only DMAE DMA enable 3 1 read-write DATATYPE Data type selection 4 2 read-write MODE Mode selection 6 1 read-write ALGO0 Algorithm selection 7 1 read-write NBW Number of words already pushed 8 4 read-only DINNE DIN not empty 12 1 read-only MDMAT Multiple DMA Transfers 13 1 read-write LKEY Long key selection 16 1 read-write ALGO1 ALGO 18 1 read-write DIN DIN data input register 0x4 0x20 read-write 0x00000000 DATAIN Data input 0 32 STR STR start register 0x8 0x20 0x00000000 DCAL Digest calculation 8 1 write-only NBLW Number of valid bits in the last word of the message 0 5 read-write 50x40,1,2,3,4HR%s HR0 digest registers 0xC 0x20 read-only 0x00000000 H H0 0 32 IMR IMR interrupt enable register 0x20 0x20 read-write 0x00000000 DCIE Digest calculation completion interrupt enable 1 1 DINIE Data input interrupt enable 0 1 SR SR status register 0x24 0x20 0x00000001 BUSY Busy bit 3 1 read-only DMAS DMA Status 2 1 read-only DCIS Digest calculation completion interrupt status 1 1 read-write DINIS Data input interrupt status 0 1 read-write 540x40,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53CSR%s CSR0 context swap registers 0xF8 0x20 read-write 0x00000000 CSR CSR0 0 32 80x40,1,2,3,4,5,6,7HASH_HR%s HASH_HR0 HASH digest register 0x310 0x20 read-only 0x00000000 H H0 0 32 CRYP Cryptographic processor CRYP 0x50060000 0x0 0x400 registers CRYP CRYP crypto global interrupt 79 CRYP CRYP crypto global interrupt 79 40x80,1,2,3KEY%sCluster KEY%s, containing K?LR, K?RR0x20 KLR K0LR key registers 0x0 0x20 write-only 0x00000000 b2b224032 KRR K0RR key registers 0x4 0x20 write-only 0x00000000 bb192032 20x80,1INIT%sCluster INIT%s, containing IV?LR, IV?RR0x40 IVLR IV0LR initialization vector registers 0x0 0x20 read-write 0x00000000 IVIV31032 IVRR IV0RR initialization vector registers 0x4 0x20 read-write 0x00000000 IVIV63032 CR CR control register 0x0 0x20 0x00000000 ALGODIR Algorithm direction 2 1 read-write ALGOMODE0 Algorithm mode 3 3 read-write DATATYPE Data type selection 6 2 read-write KEYSIZE Key size selection (AES mode only) 8 2 read-write FFLUSH FIFO flush 14 1 write-only CRYPEN Cryptographic processor enable 15 1 read-write GCM_CCMPH GCM_CCMPH 16 2 read-write ALGOMODE3 ALGOMODE 19 1 read-write SR SR status register 0x4 0x20 read-only 0x00000003 BUSY Busy bit 4 1 OFFU Output FIFO full 3 1 OFNE Output FIFO not empty 2 1 IFNF Input FIFO not full 1 1 IFEM Input FIFO empty 0 1 DIN DIN data input register 0x8 0x20 read-write 0x00000000 DATAIN Data input 0 32 DOUT DOUT data output register 0xC 0x20 read-only 0x00000000 DATAOUT Data output 0 32 DMACR DMACR DMA control register 0x10 0x20 read-write 0x00000000 DOEN DMA output enable 1 1 DIEN DMA input enable 0 1 IMSCR IMSCR interrupt mask set/clear register 0x14 0x20 read-write 0x00000000 OUTIM Output FIFO service interrupt mask 1 1 INIM Input FIFO service interrupt mask 0 1 RISR RISR raw interrupt status register 0x18 0x20 read-only 0x00000001 OUTRIS Output FIFO service raw interrupt status 1 1 INRIS Input FIFO service raw interrupt status 0 1 MISR MISR masked interrupt status register 0x1C 0x20 read-only 0x00000000 OUTMIS Output FIFO service masked interrupt status 1 1 INMIS Input FIFO service masked interrupt status 0 1 80x40,1,2,3,4,5,6,7CSGCMCCM%sR CSGCMCCM0R context swap register 0x50 0x20 read-write 0x00000000 CSGCMCCM0R CSGCMCCM0R 0 32 80x40,1,2,3,4,5,6,7CSGCM%sR CSGCM0R context swap register 0x70 0x20 read-write 0x00000000 CSGCMR CSGCM0R 0 32 DCMI Digital camera interface DCMI 0x50050000 0x0 0x400 registers DCMI DCMI global interrupt 78 DCMI DCMI global interrupt 78 CR CR control register 1 0x0 0x20 read-write 0x0000 ENABLE DCMI enable 14 1 EDM Extended data mode 10 2 FCRC Frame capture rate control 8 2 VSPOL Vertical synchronization polarity 7 1 HSPOL Horizontal synchronization polarity 6 1 PCKPOL Pixel clock polarity 5 1 ESS Embedded synchronization select 4 1 JPEG JPEG format 3 1 CROP Crop feature 2 1 CM Capture mode 1 1 CAPTURE Capture enable 0 1 SR SR status register 0x4 0x20 read-only 0x0000 FNE FIFO not empty 2 1 VSYNC VSYNC 1 1 HSYNC HSYNC 0 1 RIS RIS raw interrupt status register 0x8 0x20 read-only 0x0000 LINE_RIS Line raw interrupt status 4 1 VSYNC_RIS VSYNC raw interrupt status 3 1 ERR_RIS Synchronization error raw interrupt status 2 1 OVR_RIS Overrun raw interrupt status 1 1 FRAME_RIS Capture complete raw interrupt status 0 1 IER IER interrupt enable register 0xC 0x20 read-write 0x0000 LINE_IE Line interrupt enable 4 1 VSYNC_IE VSYNC interrupt enable 3 1 ERR_IE Synchronization error interrupt enable 2 1 OVR_IE Overrun interrupt enable 1 1 FRAME_IE Capture complete interrupt enable 0 1 MIS MIS masked interrupt status register 0x10 0x20 read-only 0x0000 LINE_MIS Line masked interrupt status 4 1 VSYNC_MIS VSYNC masked interrupt status 3 1 ERR_MIS Synchronization error masked interrupt status 2 1 OVR_MIS Overrun masked interrupt status 1 1 FRAME_MIS Capture complete masked interrupt status 0 1 ICR ICR interrupt clear register 0x14 0x20 write-only 0x0000 LINE_ISC line interrupt status clear 4 1 VSYNC_ISC Vertical synch interrupt status clear 3 1 ERR_ISC Synchronization error interrupt status clear 2 1 OVR_ISC Overrun interrupt status clear 1 1 FRAME_ISC Capture complete interrupt status clear 0 1 ESCR ESCR embedded synchronization code register 0x18 0x20 read-write 0x0000 FEC Frame end delimiter code 24 8 LEC Line end delimiter code 16 8 LSC Line start delimiter code 8 8 FSC Frame start delimiter code 0 8 ESUR ESUR embedded synchronization unmask register 0x1C 0x20 read-write 0x0000 FEU Frame end delimiter unmask 24 8 LEU Line end delimiter unmask 16 8 LSU Line start delimiter unmask 8 8 FSU Frame start delimiter unmask 0 8 CWSTRT CWSTRT crop window start 0x20 0x20 read-write 0x0000 VST Vertical start line count 16 13 HOFFCNT Horizontal offset count 0 14 CWSIZE CWSIZE crop window size 0x24 0x20 read-write 0x0000 VLINE Vertical line count 16 14 CAPCNT Capture count 0 14 DR DR data register 0x28 0x20 read-only 0x0000 Byte3 Data byte 3 24 8 Byte2 Data byte 2 16 8 Byte1 Data byte 1 8 8 Byte0 Data byte 0 0 8 FMC Flexible memory controller FSMC 0xA0000000 0x0 0x400 registers FMC FMC global interrupt 48 FMC FMC global interrupt 48 BCR1 BCR1 SRAM/NOR-Flash chip-select control register 1 0x0 0x20 read-write 0x000030D0 CCLKEN CCLKEN 20 1 CBURSTRW CBURSTRW 19 1 CBURSTRWread-writeEnabledWrite operations are performed in synchronous mode1DisabledWrite operations are always performed in asynchronous mode0 ASYNCWAIT ASYNCWAIT 15 1 ASYNCWAITread-writeDisabledWait signal not used in asynchronous mode0EnabledWait signal used even in asynchronous mode1 EXTMOD EXTMOD 14 1 EXTMODread-writeDisabledValues inside the FMC_BWTR are not taken into account0EnabledValues inside the FMC_BWTR are taken into account1 WAITEN WAITEN 13 1 WAITENread-writeDisabledValues inside the FMC_BWTR are taken into account0EnabledNWAIT signal enabled1 WREN WREN 12 1 WRENread-writeDisabledWrite operations disabled for the bank by the FMC0EnabledWrite operations enabled for the bank by the FMC1 WAITCFG WAITCFG 11 1 WAITCFGread-writeBeforeWaitStateNWAIT signal is active one data cycle before wait state0DuringWaitStateNWAIT signal is active during wait state1 WAITPOL WAITPOL 9 1 WAITPOLread-writeActiveLowNWAIT active low0ActiveHighNWAIT active high1 BURSTEN BURSTEN 8 1 BURSTENread-writeDisabledBurst mode disabled0EnabledBurst mode enabled1 FACCEN FACCEN 6 1 FACCENread-writeDisabledCorresponding NOR Flash memory access is disabled0EnabledCorresponding NOR Flash memory access is enabled1 MWID MWID 4 2 MWIDread-writeBits8Memory data bus width 8 bits0Bits16Memory data bus width 16 bits1Bits32Memory data bus width 32 bits2 MTYP MTYP 2 2 MTYPread-writeSRAMSRAM memory type0PSRAMPSRAM (CRAM) memory type1FlashNOR Flash/OneNAND Flash2 MUXEN MUXEN 1 1 MUXENread-writeDisabledAddress/Data non-multiplexed0EnabledAddress/Data multiplexed on databus1 MBKEN MBKEN 0 1 MBKENread-writeDisabledCorresponding memory bank is disabled0EnabledCorresponding memory bank is enabled1 WRAPMODWRAPMOD101 CPSIZECRAM page size163read-writeCPSIZEread-writeNoBurstSplitNo burst split when crossing page boundary0Bytes128128 bytes CRAM page size1Bytes256256 bytes CRAM page size2Bytes512512 bytes CRAM page size3Bytes10241024 bytes CRAM page size4 40x81,2,3,4BTR%s BTR1 SRAM/NOR-Flash chip-select timing register 1 0x4 0x20 read-write 0xFFFFFFFF ACCMOD ACCMOD 28 2 ACCMODread-writeAAccess mode A0BAccess mode B1CAccess mode C2DAccess mode D3 DATLAT DATLAT 24 4 015 CLKDIV CLKDIV 20 4 115 BUSTURN BUSTURN 16 4 015 DATAST DATAST 8 8 1255 ADDHLD ADDHLD 4 4 115 ADDSET ADDSET 0 4 015 30x82,3,4BCR%s BCR2 SRAM/NOR-Flash chip-select control register 2 0x8 0x20 read-write 0x000030D0 CBURSTRW CBURSTRW 19 1 CBURSTRWread-writeEnabledWrite operations are performed in synchronous mode1DisabledWrite operations are always performed in asynchronous mode0 ASYNCWAIT ASYNCWAIT 15 1 ASYNCWAITread-writeDisabledWait signal not used in asynchronous mode0EnabledWait signal used even in asynchronous mode1 EXTMOD EXTMOD 14 1 EXTMODread-writeDisabledValues inside the FMC_BWTR are not taken into account0EnabledValues inside the FMC_BWTR are taken into account1 WAITEN WAITEN 13 1 WAITENread-writeDisabledValues inside the FMC_BWTR are taken into account0EnabledNWAIT signal enabled1 WREN WREN 12 1 WRENread-writeDisabledWrite operations disabled for the bank by the FMC0EnabledWrite operations enabled for the bank by the FMC1 WAITCFG WAITCFG 11 1 WAITCFGread-writeBeforeWaitStateNWAIT signal is active one data cycle before wait state0DuringWaitStateNWAIT signal is active during wait state1 WRAPMOD WRAPMOD 10 1 WAITPOL WAITPOL 9 1 WAITPOLread-writeActiveLowNWAIT active low0ActiveHighNWAIT active high1 BURSTEN BURSTEN 8 1 BURSTENread-writeDisabledBurst mode disabled0EnabledBurst mode enabled1 FACCEN FACCEN 6 1 FACCENread-writeDisabledCorresponding NOR Flash memory access is disabled0EnabledCorresponding NOR Flash memory access is enabled1 MWID MWID 4 2 MWIDread-writeBits8Memory data bus width 8 bits0Bits16Memory data bus width 16 bits1Bits32Memory data bus width 32 bits2 MTYP MTYP 2 2 MTYPread-writeSRAMSRAM memory type0PSRAMPSRAM (CRAM) memory type1FlashNOR Flash/OneNAND Flash2 MUXEN MUXEN 1 1 MUXENread-writeDisabledAddress/Data non-multiplexed0EnabledAddress/Data multiplexed on databus1 MBKEN MBKEN 0 1 MBKENread-writeDisabledCorresponding memory bank is disabled0EnabledCorresponding memory bank is enabled1 CPSIZECRAM page size163read-writeCPSIZEread-writeNoBurstSplitNo burst split when crossing page boundary0Bytes128128 bytes CRAM page size1Bytes256256 bytes CRAM page size2Bytes512512 bytes CRAM page size3Bytes10241024 bytes CRAM page size4 30x202,3,4PCR%s PCR2 PC Card/NAND Flash control register 2 0x60 0x20 read-write 0x00000018 ECCPS ECCPS 17 3 ECCPSread-writeBytes256ECC page size 256 bytes0Bytes512ECC page size 512 bytes1Bytes1024ECC page size 1024 bytes2Bytes2048ECC page size 2048 bytes3Bytes4096ECC page size 4096 bytes4Bytes8192ECC page size 8192 bytes5 TAR TAR 13 4 015 TCLR TCLR 9 4 015 ECCEN ECCEN 6 1 ECCENread-writeDisabledECC logic is disabled and reset0EnabledECC logic is enabled1 PWID PWID 4 2 PWIDread-writeBits8External memory device width 8 bits0Bits16External memory device width 16 bits1 PTYP PTYP 3 1 PTYPread-writeNANDFlashNAND Flash1 PBKEN PBKEN 2 1 PBKENread-writeDisabledCorresponding memory bank is disabled0EnabledCorresponding memory bank is enabled1 PWAITEN PWAITEN 1 1 PWAITENread-writeDisabledWait feature disabled0EnabledWait feature enabled1 30x202,3,4SR%s SR2 FIFO status and interrupt register 2 0x64 0x20 0x00000040 FEMPT FEMPT 6 1 read-only FEMPTread-writeNotEmptyFIFO not empty0EmptyFIFO empty1 IFEN IFEN 5 1 read-write IFENread-writeDisabledInterrupt falling edge detection request disabled0EnabledInterrupt falling edge detection request enabled1 ILEN ILEN 4 1 read-write ILENread-writeDisabledInterrupt high-level detection request disabled0EnabledInterrupt high-level detection request enabled1 IREN IREN 3 1 read-write IRENread-writeDisabledInterrupt rising edge detection request disabled0EnabledInterrupt rising edge detection request enabled1 IFS IFS 2 1 read-write IFSread-writeDidNotOccurInterrupt falling edge did not occur0OccurredInterrupt falling edge occurred1 ILS ILS 1 1 read-write ILSread-writeDidNotOccurInterrupt high-level did not occur0OccurredInterrupt high-level occurred1 IRS IRS 0 1 read-write IRSread-writeDidNotOccurInterrupt rising edge did not occur0OccurredInterrupt rising edge occurred1 PMEM2 PMEM2 Common memory space timing register 2 0x68 0x20 read-write 0xFCFCFCFC MEMHIZ MEMHIZx 24 8 0254 MEMHOLD MEMHOLDx 16 8 1254 MEMWAIT MEMWAITx 8 8 1254 MEMSET MEMSETx 0 8 0254 PATT2 PATT2 Attribute memory space timing register 2 0x6C 0x20 read-write 0xFCFCFCFC ATTHIZ ATTHIZx 24 8 0254 ATTHOLD ATTHOLDx 16 8 1254 ATTWAIT ATTWAITx 8 8 1254 ATTSET ATTSETx 0 8 0254 ECCR2 ECCR2 ECC result register 2 0x74 0x20 read-only 0x00000000 ECC ECCx 0 32 04294967295 PMEM3 PMEM3 Common memory space timing register 3 0x88 0x20 read-write 0xFCFCFCFC MEMHIZ MEMHIZx 24 8 0254 MEMHOLD MEMHOLDx 16 8 1254 MEMWAIT MEMWAITx 8 8 1254 MEMSET MEMSETx 0 8 0254 PATT3 PATT3 Attribute memory space timing register 3 0x8C 0x20 read-write 0xFCFCFCFC ATTHIZ ATTHIZx 24 8 0254 ATTHOLD ATTHOLDx 16 8 1254 ATTWAIT ATTWAITx 8 8 1254 ATTSET ATTSETx 0 8 0254 ECCR3 ECCR3 ECC result register 3 0x94 0x20 read-only 0x00000000 ECC ECCx 0 32 04294967295 PMEM4 PMEM4 Common memory space timing register 4 0xA8 0x20 read-write 0xFCFCFCFC MEMHIZ MEMHIZx 24 8 0254 MEMHOLD MEMHOLDx 16 8 1254 MEMWAIT MEMWAITx 8 8 1254 MEMSET MEMSETx 0 8 0254 PATT4 PATT4 Attribute memory space timing register 4 0xAC 0x20 read-write 0xFCFCFCFC ATTHIZ ATTHIZx 24 8 0254 ATTHOLD ATTHOLDx 16 8 1254 ATTWAIT ATTWAITx 8 8 1254 ATTSET ATTSETx 0 8 0254 PIO4 PIO4 I/O space timing register 4 0xB0 0x20 read-write 0xFCFCFCFC IOHIZx IOHIZx 24 8 IOHOLDx IOHOLDx 16 8 IOWAITx IOWAITx 8 8 IOSETx IOSETx 0 8 40x81,2,3,4BWTR%s BWTR1 SRAM/NOR-Flash write timing registers 1 0x104 0x20 read-write 0x0FFFFFFF ACCMOD ACCMOD 28 2 ACCMODread-writeAAccess mode A0BAccess mode B1CAccess mode C2DAccess mode D3 DATLAT DATLAT 24 4 CLKDIV CLKDIV 20 4 DATAST DATAST 8 8 1255 ADDHLD ADDHLD 4 4 115 ADDSET ADDSET 0 4 015 BUSTURNBus turnaround phase duration164read-write015 20x41,2SDCR%s SDCR1 SDRAM Control Register 1 0x140 0x20 read-write 0x000002D0 NC Number of column address bits 0 2 NCread-writeBits88 bits0Bits99 bits1Bits1010 bits2Bits1111 bits3 NR Number of row address bits 2 2 NRread-writeBits1111 bits0Bits1212 bits1Bits1313 bits2 MWID Memory data bus width 4 2 MWIDread-writeBits8Memory data bus width 8 bits0Bits16Memory data bus width 16 bits1Bits32Memory data bus width 32 bits2 NB Number of internal banks 6 1 NBread-writeNB2Two internal Banks0NB4Four internal Banks1 CAS CAS latency 7 2 CASread-writeClocks11 cycle1Clocks22 cycles2Clocks33 cycles3 WP Write protection 9 1 WPread-writeDisabledWrite accesses allowed0EnabledWrite accesses ignored1 SDCLK SDRAM clock configuration 10 2 SDCLKread-writeDisabledSDCLK clock disabled0Div2SDCLK period = 2 x HCLK period2Div3SDCLK period = 3 x HCLK period3 RBURST Burst read 12 1 RBURSTread-writeDisabledSingle read requests are not managed as bursts0EnabledSingle read requests are always managed as bursts1 RPIPE Read pipe 13 2 RPIPEread-writeNoDelayNo clock cycle delay0Clocks1One clock cycle delay1Clocks2Two clock cycles delay2 20x41,2SDTR%s SDTR1 SDRAM Timing register 1 0x148 0x20 read-write 0x0FFFFFFF TMRD Load Mode Register to Active 0 4 015 TXSR Exit self-refresh delay 4 4 015 TRAS Self refresh time 8 4 015 TRC Row cycle delay 12 4 015 TWR Recovery delay 16 4 015 TRP Row precharge delay 20 4 015 TRCD Row to column delay 24 4 015 SDCMR SDCMR SDRAM Command Mode register 0x150 0x20 0x00000000 MODE Command mode 0 3 write-only MODEread-writeNormalNormal Mode0ClockConfigurationEnableClock Configuration Enable1PALLPALL (All Bank Precharge) command2AutoRefreshCommandAuto-refresh command3LoadModeRegisterLoad Mode Resgier4SelfRefreshCommandSelf-refresh command5PowerDownCommandPower-down command6 CTB2 Command target bank 2 3 1 write-only CTB2read-writeNotIssuedCommand not issued to SDRAM Bank 10IssuedCommand issued to SDRAM Bank 11 CTB1 Command target bank 1 4 1 write-only NRFS Number of Auto-refresh 5 4 read-write 015 MRD Mode Register definition 9 13 read-write 08191 SDRTR SDRTR SDRAM Refresh Timer register 0x154 0x20 0x00000000 CRE Clear Refresh error flag 0 1 write-only CREread-writeClearRefresh Error Flag is cleared1 COUNT Refresh Timer Count 1 13 read-write 08191 REIE RES Interrupt Enable 14 1 read-write REIEread-writeDisabledInterrupt is disabled0EnabledInterrupt is generated if RE = 11 SDSR SDSR SDRAM Status register 0x158 0x20 read-only 0x00000000 RE Refresh error flag 0 1 REread-writeNoErrorNo refresh error has been detected0ErrorA refresh error has been detected1 MODES1 Status Mode for Bank 1 1 2 MODES1read-writeNormalNormal Mode0SelfRefreshSelf-refresh mode1PowerDownPower-down mode2 MODES2 Status Mode for Bank 2 3 2 BUSY Busy status 5 1 BUSYread-writeNotBusySDRAM Controller is ready to accept a new request0BusySDRAM Controller is not ready to accept a new request1 DBGMCU Debug support DBG 0xE0042000 0x0 0x400 registers IDCODE IDCODE IDCODE 0x0 0x20 read-only 0x10006411 DEV_ID DEV_ID 0 12 REV_ID REV_ID 16 16 CR CR Control Register 0x4 0x20 read-write 0x00000000 DBG_SLEEP DBG_SLEEP 0 1 DBG_STOP DBG_STOP 1 1 DBG_STANDBY DBG_STANDBY 2 1 TRACE_IOEN TRACE_IOEN 5 1 TRACE_MODE TRACE_MODE 6 2 APB1_FZ APB1_FZ Debug MCU APB1 Freeze registe 0x8 0x20 read-write 0x00000000 DBG_TIM2_STOP DBG_TIM2_STOP 0 1 DBG_TIM3_STOP DBG_TIM3 _STOP 1 1 DBG_TIM4_STOP DBG_TIM4_STOP 2 1 DBG_TIM5_STOP DBG_TIM5_STOP 3 1 DBG_TIM6_STOP DBG_TIM6_STOP 4 1 DBG_TIM7_STOP DBG_TIM7_STOP 5 1 DBG_TIM12_STOP DBG_TIM12_STOP 6 1 DBG_TIM13_STOP DBG_TIM13_STOP 7 1 DBG_TIM14_STOP DBG_TIM14_STOP 8 1 DBG_WWDG_STOP DBG_WWDG_STOP 11 1 DBG_IWDG_STOP DBG_IWDEG_STOP 12 1 DBG_J2C1_SMBUS_TIMEOUT DBG_J2C1_SMBUS_TIMEOUT 21 1 DBG_J2C2_SMBUS_TIMEOUT DBG_J2C2_SMBUS_TIMEOUT 22 1 DBG_J2C3SMBUS_TIMEOUT DBG_J2C3SMBUS_TIMEOUT 23 1 DBG_CAN1_STOP DBG_CAN1_STOP 25 1 DBG_CAN2_STOP DBG_CAN2_STOP 26 1 APB2_FZ APB2_FZ Debug MCU APB2 Freeze registe 0xC 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 0 1 DBG_TIM8_STOP TIM8 counter stopped when core is halted 1 1 DBG_TIM9_STOP TIM9 counter stopped when core is halted 16 1 DBG_TIM10_STOP TIM10 counter stopped when core is halted 17 1 DBG_TIM11_STOP TIM11 counter stopped when core is halted 18 1 DMA2 DMA controller DMA 0x40026400 0x0 0x400 registers DMA2_Stream0 DMA2 Stream0 global interrupt 56 DMA2_Stream0 DMA2 Stream0 global interrupt 56 DMA2_Stream1 DMA2 Stream1 global interrupt 57 DMA2_Stream1 DMA2 Stream1 global interrupt 57 DMA2_Stream2 DMA2 Stream2 global interrupt 58 DMA2_Stream2 DMA2 Stream2 global interrupt 58 DMA2_Stream3 DMA2 Stream3 global interrupt 59 DMA2_Stream3 DMA2 Stream3 global interrupt 59 DMA2_Stream4 DMA2 Stream4 global interrupt 60 DMA2_Stream4 DMA2 Stream4 global interrupt 60 DMA2_Stream5 DMA2 Stream5 global interrupt 68 DMA2_Stream5 DMA2 Stream5 global interrupt 68 DMA2_Stream6 DMA2 Stream6 global interrupt 69 DMA2_Stream6 DMA2 Stream6 global interrupt 69 DMA2_Stream7 DMA2 Stream7 global interrupt 70 DMA2_Stream7 DMA2 Stream7 global interrupt 70 80x180,1,2,3,4,5,6,7ST%sStream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers0x10 CR S0CR stream x configuration register 0x0 0x20 read-write 0x00000000 CHSEL Channel selection 25 3 07 MBURST Memory burst transfer configuration 23 2 PBURST Peripheral burst transfer configuration 21 2 PBURSTread-writeSingleSingle transfer0INCR4Incremental burst of 4 beats1INCR8Incremental burst of 8 beats2INCR16Incremental burst of 16 beats3 CT Current target (only in double buffer mode) 19 1 CTread-writeMemory0The current target memory is Memory 00Memory1The current target memory is Memory 11 DBM Double buffer mode 18 1 DBMread-writeDisabledNo buffer switching at the end of transfer0EnabledMemory target switched at the end of the DMA transfer1 PL Priority level 16 2 PLread-writeLowLow0MediumMedium1HighHigh2VeryHighVery high3 PINCOS Peripheral increment offset size 15 1 PINCOSread-writePSIZEThe offset size for the peripheral address calculation is linked to the PSIZE0Fixed4The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)1 MSIZE Memory data size 13 2 PSIZE Peripheral data size 11 2 PSIZEread-writeBits8Byte (8-bit)0Bits16Half-word (16-bit)1Bits32Word (32-bit)2 MINC Memory increment mode 10 1 PINC Peripheral increment mode 9 1 PINCread-writeFixedAddress pointer is fixed0IncrementedAddress pointer is incremented after each data transfer1 CIRC Circular mode 8 1 CIRCread-writeDisabledCircular mode disabled0EnabledCircular mode enabled1 DIR Data transfer direction 6 2 DIRread-writePeripheralToMemoryPeripheral-to-memory0MemoryToPeripheralMemory-to-peripheral1MemoryToMemoryMemory-to-memory2 PFCTRL Peripheral flow controller 5 1 PFCTRLread-writeDMAThe DMA is the flow controller0PeripheralThe peripheral is the flow controller1 TCIE Transfer complete interrupt enable 4 1 TCIEread-writeDisabledTC interrupt disabled0EnabledTC interrupt enabled1 HTIE Half transfer interrupt enable 3 1 HTIEread-writeDisabledHT interrupt disabled0EnabledHT interrupt enabled1 TEIE Transfer error interrupt enable 2 1 TEIEread-writeDisabledTE interrupt disabled0EnabledTE interrupt enabled1 DMEIE Direct mode error interrupt enable 1 1 DMEIEread-writeDisabledDME interrupt disabled0EnabledDME interrupt enabled1 EN Stream enable / flag stream ready when read low 0 1 ENread-writeDisabledStream disabled0EnabledStream enabled1 NDTR S0NDTR stream x number of data register 0x4 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 065535 PAR S0PAR stream x peripheral address register 0x8 0x20 read-write 0x00000000 PA Peripheral address 0 32 M0AR S0M0AR stream x memory 0 address register 0xc 0x20 read-write 0x00000000 M0A Memory 0 address 0 32 M1AR S0M1AR stream x memory 1 address register 0x10 0x20 read-write 0x00000000 M1A Memory 1 address (used in case of Double buffer mode) 0 32 FCR S0FCR stream x FIFO control register 0x14 0x20 0x00000021 FEIE FIFO error interrupt enable 7 1 read-write FEIEread-writeDisabledFE interrupt disabled0EnabledFE interrupt enabled1 FS FIFO status 3 3 read-only FSread-writeQuarter10 < fifo_level < 1/40Quarter21/4 <= fifo_level < 1/21Quarter31/2 <= fifo_level < 3/42Quarter43/4 <= fifo_level < full3EmptyFIFO is empty4FullFIFO is full5 DMDIS Direct mode disable 2 1 read-write DMDISread-writeEnabledDirect mode is enabled0DisabledDirect mode is disabled1 FTH FIFO threshold selection 0 2 read-write FTHread-writeQuarter1/4 full FIFO0Half1/2 full FIFO1ThreeQuarters3/4 full FIFO2FullFull FIFO3 LISR LISR low interrupt status register 0x0 0x20 read-only 0x00000000 TCIF3 Stream x transfer complete interrupt flag (x = 3..0) 27 1 HTIF3 Stream x half transfer interrupt flag (x=3..0) 26 1 TEIF3 Stream x transfer error interrupt flag (x=3..0) 25 1 DMEIF3 Stream x direct mode error interrupt flag (x=3..0) 24 1 FEIF3 Stream x FIFO error interrupt flag (x=3..0) 22 1 TCIF2 Stream x transfer complete interrupt flag (x = 3..0) 21 1 HTIF2 Stream x half transfer interrupt flag (x=3..0) 20 1 TEIF2 Stream x transfer error interrupt flag (x=3..0) 19 1 DMEIF2 Stream x direct mode error interrupt flag (x=3..0) 18 1 FEIF2 Stream x FIFO error interrupt flag (x=3..0) 16 1 TCIF1 Stream x transfer complete interrupt flag (x = 3..0) 11 1 HTIF1 Stream x half transfer interrupt flag (x=3..0) 10 1 TEIF1 Stream x transfer error interrupt flag (x=3..0) 9 1 DMEIF1 Stream x direct mode error interrupt flag (x=3..0) 8 1 FEIF1 Stream x FIFO error interrupt flag (x=3..0) 6 1 TCIF0 Stream x transfer complete interrupt flag (x = 3..0) 5 1 TCIF0read-writeNotCompleteNo transfer complete event on stream x0CompleteA transfer complete event occurred on stream x1 HTIF0 Stream x half transfer interrupt flag (x=3..0) 4 1 HTIF0read-writeNotHalfNo half transfer event on stream x0HalfA half transfer event occurred on stream x1 TEIF0 Stream x transfer error interrupt flag (x=3..0) 3 1 TEIF0read-writeNoErrorNo transfer error on stream x0ErrorA transfer error occurred on stream x1 DMEIF0 Stream x direct mode error interrupt flag (x=3..0) 2 1 DMEIF0read-writeNoErrorNo Direct Mode error on stream x0ErrorA Direct Mode error occurred on stream x1 FEIF0 Stream x FIFO error interrupt flag (x=3..0) 0 1 FEIF0read-writeNoErrorNo FIFO error event on stream x0ErrorA FIFO error event occurred on stream x1 HISR HISR high interrupt status register 0x4 0x20 read-only 0x00000000 TCIF7 Stream x transfer complete interrupt flag (x=7..4) 27 1 HTIF7 Stream x half transfer interrupt flag (x=7..4) 26 1 TEIF7 Stream x transfer error interrupt flag (x=7..4) 25 1 DMEIF7 Stream x direct mode error interrupt flag (x=7..4) 24 1 FEIF7 Stream x FIFO error interrupt flag (x=7..4) 22 1 TCIF6 Stream x transfer complete interrupt flag (x=7..4) 21 1 HTIF6 Stream x half transfer interrupt flag (x=7..4) 20 1 TEIF6 Stream x transfer error interrupt flag (x=7..4) 19 1 DMEIF6 Stream x direct mode error interrupt flag (x=7..4) 18 1 FEIF6 Stream x FIFO error interrupt flag (x=7..4) 16 1 TCIF5 Stream x transfer complete interrupt flag (x=7..4) 11 1 HTIF5 Stream x half transfer interrupt flag (x=7..4) 10 1 TEIF5 Stream x transfer error interrupt flag (x=7..4) 9 1 DMEIF5 Stream x direct mode error interrupt flag (x=7..4) 8 1 FEIF5 Stream x FIFO error interrupt flag (x=7..4) 6 1 TCIF4 Stream x transfer complete interrupt flag (x=7..4) 5 1 TCIF4read-writeNotCompleteNo transfer complete event on stream x0CompleteA transfer complete event occurred on stream x1 HTIF4 Stream x half transfer interrupt flag (x=7..4) 4 1 HTIF4read-writeNotHalfNo half transfer event on stream x0HalfA half transfer event occurred on stream x1 TEIF4 Stream x transfer error interrupt flag (x=7..4) 3 1 TEIF4read-writeNoErrorNo transfer error on stream x0ErrorA transfer error occurred on stream x1 DMEIF4 Stream x direct mode error interrupt flag (x=7..4) 2 1 DMEIF4read-writeNoErrorNo Direct Mode error on stream x0ErrorA Direct Mode error occurred on stream x1 FEIF4 Stream x FIFO error interrupt flag (x=7..4) 0 1 FEIF4read-writeNoErrorNo FIFO error event on stream x0ErrorA FIFO error event occurred on stream x1 LIFCR LIFCR low interrupt flag clear register 0x8 0x20 write-only 0x00000000 CTCIF3 Stream x clear transfer complete interrupt flag (x = 3..0) 27 1 CHTIF3 Stream x clear half transfer interrupt flag (x = 3..0) 26 1 CTEIF3 Stream x clear transfer error interrupt flag (x = 3..0) 25 1 CDMEIF3 Stream x clear direct mode error interrupt flag (x = 3..0) 24 1 CFEIF3 Stream x clear FIFO error interrupt flag (x = 3..0) 22 1 CTCIF2 Stream x clear transfer complete interrupt flag (x = 3..0) 21 1 CHTIF2 Stream x clear half transfer interrupt flag (x = 3..0) 20 1 CTEIF2 Stream x clear transfer error interrupt flag (x = 3..0) 19 1 CDMEIF2 Stream x clear direct mode error interrupt flag (x = 3..0) 18 1 CFEIF2 Stream x clear FIFO error interrupt flag (x = 3..0) 16 1 CTCIF1 Stream x clear transfer complete interrupt flag (x = 3..0) 11 1 CHTIF1 Stream x clear half transfer interrupt flag (x = 3..0) 10 1 CTEIF1 Stream x clear transfer error interrupt flag (x = 3..0) 9 1 CDMEIF1 Stream x clear direct mode error interrupt flag (x = 3..0) 8 1 CFEIF1 Stream x clear FIFO error interrupt flag (x = 3..0) 6 1 CTCIF0 Stream x clear transfer complete interrupt flag (x = 3..0) 5 1 CTCIF0read-writeClearClear the corresponding TCIFx flag1 CHTIF0 Stream x clear half transfer interrupt flag (x = 3..0) 4 1 CHTIF0read-writeClearClear the corresponding HTIFx flag1 CTEIF0 Stream x clear transfer error interrupt flag (x = 3..0) 3 1 CTEIF0read-writeClearClear the corresponding TEIFx flag1 CDMEIF0 Stream x clear direct mode error interrupt flag (x = 3..0) 2 1 CDMEIF0read-writeClearClear the corresponding DMEIFx flag1 CFEIF0 Stream x clear FIFO error interrupt flag (x = 3..0) 0 1 CFEIF0read-writeClearClear the corresponding CFEIFx flag1 HIFCR HIFCR high interrupt flag clear register 0xC 0x20 write-only 0x00000000 CTCIF7 Stream x clear transfer complete interrupt flag (x = 7..4) 27 1 CHTIF7 Stream x clear half transfer interrupt flag (x = 7..4) 26 1 CTEIF7 Stream x clear transfer error interrupt flag (x = 7..4) 25 1 CDMEIF7 Stream x clear direct mode error interrupt flag (x = 7..4) 24 1 CFEIF7 Stream x clear FIFO error interrupt flag (x = 7..4) 22 1 CTCIF6 Stream x clear transfer complete interrupt flag (x = 7..4) 21 1 CHTIF6 Stream x clear half transfer interrupt flag (x = 7..4) 20 1 CTEIF6 Stream x clear transfer error interrupt flag (x = 7..4) 19 1 CDMEIF6 Stream x clear direct mode error interrupt flag (x = 7..4) 18 1 CFEIF6 Stream x clear FIFO error interrupt flag (x = 7..4) 16 1 CTCIF5 Stream x clear transfer complete interrupt flag (x = 7..4) 11 1 CHTIF5 Stream x clear half transfer interrupt flag (x = 7..4) 10 1 CTEIF5 Stream x clear transfer error interrupt flag (x = 7..4) 9 1 CDMEIF5 Stream x clear direct mode error interrupt flag (x = 7..4) 8 1 CFEIF5 Stream x clear FIFO error interrupt flag (x = 7..4) 6 1 CTCIF4 Stream x clear transfer complete interrupt flag (x = 7..4) 5 1 CTCIF4read-writeClearClear the corresponding TCIFx flag1 CHTIF4 Stream x clear half transfer interrupt flag (x = 7..4) 4 1 CHTIF4read-writeClearClear the corresponding HTIFx flag1 CTEIF4 Stream x clear transfer error interrupt flag (x = 7..4) 3 1 CTEIF4read-writeClearClear the corresponding TEIFx flag1 CDMEIF4 Stream x clear direct mode error interrupt flag (x = 7..4) 2 1 CDMEIF4read-writeClearClear the corresponding DMEIFx flag1 CFEIF4 Stream x clear FIFO error interrupt flag (x = 7..4) 0 1 CFEIF4read-writeClearClear the corresponding CFEIFx flag1 DMA1 0x40026000 DMA1_Stream0 DMA1 Stream0 global interrupt 11 DMA1_Stream0 DMA1 Stream0 global interrupt 11 DMA1_Stream1 DMA1 Stream1 global interrupt 12 DMA1_Stream1 DMA1 Stream1 global interrupt 12 DMA1_Stream2 DMA1 Stream2 global interrupt 13 DMA1_Stream2 DMA1 Stream2 global interrupt 13 DMA1_Stream3 DMA1 Stream3 global interrupt 14 DMA1_Stream3 DMA1 Stream3 global interrupt 14 DMA1_Stream4 DMA1 Stream4 global interrupt 15 DMA1_Stream4 DMA1 Stream4 global interrupt 15 DMA1_Stream5 DMA1 Stream5 global interrupt 16 DMA1_Stream5 DMA1 Stream5 global interrupt 16 DMA1_Stream6 DMA1 Stream6 global interrupt 17 DMA1_Stream6 DMA1 Stream6 global interrupt 17 DMA1_Stream7 DMA1 Stream7 global interrupt 47 DMA1_Stream7 DMA1 Stream7 global interrupt 47 RCC Reset and clock control RCC 0x40023800 0x0 0x400 registers RCC RCC global interrupt 5 RCC RCC global interrupt 5 CR CR clock control register 0x0 0x20 0x00000083 PLLI2SRDY PLLI2S clock ready flag 27 1 read-only PLLI2SON PLLI2S enable 26 1 read-write PLLRDY Main PLL (PLL) clock ready flag 25 1 read-only PLLON Main PLL (PLL) enable 24 1 read-write CSSON Clock security system enable 19 1 read-write CSSONread-writeOffClock security system disabled (clock detector OFF)0OnClock security system enable (clock detector ON if the HSE is ready, OFF if not)1 HSEBYP HSE clock bypass 18 1 read-write HSEBYPread-writeNotBypassedHSE crystal oscillator not bypassed0BypassedHSE crystal oscillator bypassed with external clock1 HSERDY HSE clock ready flag 17 1 read-only HSEON HSE clock enable 16 1 read-write HSICAL Internal high-speed clock calibration 8 8 read-only 0255 HSITRIM Internal high-speed clock trimming 3 5 read-write 031 HSIRDY Internal high-speed clock ready flag 1 1 read-only HSIRDYRreadNotReadyClock not ready0ReadyClock ready1 HSION Internal high-speed clock enable 0 1 read-write HSIONread-writeOffClock Off0OnClock On1 PLLSAIRDYPLLSAI clock ready flag291read-only PLLSAIONPLLSAI enable281read-write PLLCFGR PLLCFGR PLL configuration register 0x4 0x20 read-write 0x24003010 PLLSRC Main PLL(PLL) and audio PLL (PLLI2S) entry clock source 22 1 PLLSRCread-writeHSIHSI clock selected as PLL and PLLI2S clock entry0HSEHSE oscillator clock selected as PLL and PLLI2S clock entry1 PLLMDivision factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock06263 PLLNMain PLL (PLL) multiplication factor for VCO6950432 PLLPMain PLL (PLL) division factor for main system clock162PLLPread-writeDiv2PLLP=20Div4PLLP=41Div6PLLP=62Div8PLLP=83 PLLQMain PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks244215 CFGR CFGR clock configuration register 0x8 0x20 0x00000000 MCO2 Microcontroller clock output 2 30 2 read-write MCO2read-writeSYSCLKSystem clock (SYSCLK) selected0PLLI2SPLLI2S clock selected1HSEHSE oscillator clock selected2PLLPLL clock selected3 MCO2PRE MCO2 prescaler 27 3 read-write MCO1PRE MCO1 prescaler 24 3 read-write MCO1PREread-writeDiv1No division0Div2Division by 24Div3Division by 35Div4Division by 46Div5Division by 57 I2SSRC I2S clock selection 23 1 read-write I2SSRCread-writePLLI2SPLLI2S clock used as I2S clock source0CKINExternal clock mapped on the I2S_CKIN pin used as I2S clock source1 MCO1 Microcontroller clock output 1 21 2 read-write MCO1read-writeHSIHSI clock selected0LSELSE oscillator selected1HSEHSE oscillator clock selected2PLLPLL clock selected3 RTCPRE HSE division factor for RTC clock 16 5 read-write 031 PPRE2 APB high-speed prescaler (APB2) 13 3 read-write PPRE1 APB Low speed prescaler (APB1) 10 3 read-write PPRE1read-writeDiv1HCLK not divided0Div2HCLK divided by 24Div4HCLK divided by 45Div8HCLK divided by 86Div16HCLK divided by 167 HPRE AHB prescaler 4 4 read-write HPREread-writeDiv1SYSCLK not divided0Div2SYSCLK divided by 28Div4SYSCLK divided by 49Div8SYSCLK divided by 810Div16SYSCLK divided by 1611Div64SYSCLK divided by 6412Div128SYSCLK divided by 12813Div256SYSCLK divided by 25614Div512SYSCLK divided by 51215 SWSystem clock switch02SWread-writeHSIHSI selected as system clock0HSEHSE selected as system clock1PLLPLL selected as system clock2 SWSSystem clock switch status22SWSRreadHSIHSI oscillator used as system clock0HSEHSE oscillator used as system clock1PLLPLL used as system clock2 CIR CIR clock interrupt register 0xC 0x20 0x00000000 CSSC Clock security system interrupt clear 23 1 write-only CSSCWwriteClearClear CSSF flag1 PLLI2SRDYC PLLI2S ready interrupt clear 21 1 write-only PLLRDYC Main PLL(PLL) ready interrupt clear 20 1 write-only HSERDYC HSE ready interrupt clear 19 1 write-only HSIRDYC HSI ready interrupt clear 18 1 write-only LSERDYC LSE ready interrupt clear 17 1 write-only LSIRDYC LSI ready interrupt clear 16 1 write-only LSIRDYCWwriteClearClear interrupt flag1 PLLI2SRDYIE PLLI2S ready interrupt enable 13 1 read-write PLLRDYIE Main PLL (PLL) ready interrupt enable 12 1 read-write HSERDYIE HSE ready interrupt enable 11 1 read-write HSIRDYIE HSI ready interrupt enable 10 1 read-write LSERDYIE LSE ready interrupt enable 9 1 read-write LSIRDYIE LSI ready interrupt enable 8 1 read-write LSIRDYIEread-writeDisabledInterrupt disabled0EnabledInterrupt enabled1 CSSF Clock security system interrupt flag 7 1 read-only CSSFRreadNotInterruptedNo clock security interrupt caused by HSE clock failure0InterruptedClock security interrupt caused by HSE clock failure1 PLLI2SRDYF PLLI2S ready interrupt flag 5 1 read-only PLLRDYF Main PLL (PLL) ready interrupt flag 4 1 read-only HSERDYF HSE ready interrupt flag 3 1 read-only HSIRDYF HSI ready interrupt flag 2 1 read-only LSERDYF LSE ready interrupt flag 1 1 read-only LSIRDYF LSI ready interrupt flag 0 1 read-only LSIRDYFRreadNotInterruptedNo clock ready interrupt0InterruptedClock ready interrupt1 AHB1RSTR AHB1RSTR AHB1 peripheral reset register 0x10 0x20 read-write 0x00000000 OTGHSRST USB OTG HS module reset 29 1 ETHMACRST Ethernet MAC reset 25 1 DMA2RST DMA2 reset 22 1 DMA1RST DMA2 reset 21 1 CRCRST CRC reset 12 1 GPIOIRST IO port I reset 8 1 GPIOHRST IO port H reset 7 1 GPIOGRST IO port G reset 6 1 GPIOFRST IO port F reset 5 1 GPIOERST IO port E reset 4 1 GPIODRST IO port D reset 3 1 GPIOCRST IO port C reset 2 1 GPIOBRST IO port B reset 1 1 GPIOARST IO port A reset 0 1 GPIOARSTread-writeResetReset the selected module1 DMA2DRSTDMA2D reset231 GPIOJRSTIO port J reset91 GPIOKRSTIO port K reset101 AHB2RSTR AHB2RSTR AHB2 peripheral reset register 0x14 0x20 read-write 0x00000000 OTGFSRST USB OTG FS module reset 7 1 RNGRST Random number generator module reset 6 1 HSAHRST Hash module reset 5 1 CRYPRST Cryptographic module reset 4 1 DCMIRST Camera interface reset 0 1 DCMIRSTread-writeResetReset the selected module1 AHB3RSTR AHB3RSTR AHB3 peripheral reset register 0x18 0x20 read-write 0x00000000 FMCRST Flexible memory controller module reset 0 1 FMCRSTread-writeResetReset the selected module1 APB1RSTR APB1RSTR APB1 peripheral reset register 0x20 0x20 read-write 0x00000000 TIM2RST TIM2 reset 0 1 TIM2RSTread-writeResetReset the selected module1 TIM3RST TIM3 reset 1 1 TIM4RST TIM4 reset 2 1 TIM5RST TIM5 reset 3 1 TIM6RST TIM6 reset 4 1 TIM7RST TIM7 reset 5 1 TIM12RST TIM12 reset 6 1 TIM13RST TIM13 reset 7 1 TIM14RST TIM14 reset 8 1 WWDGRST Window watchdog reset 11 1 SPI2RST SPI 2 reset 14 1 SPI3RST SPI 3 reset 15 1 USART2RST USART 2 reset 17 1 USART3RST USART 3 reset 18 1 UART4RST USART 4 reset 19 1 UART5RST USART 5 reset 20 1 I2C1RST I2C 1 reset 21 1 I2C2RST I2C 2 reset 22 1 I2C3RST I2C3 reset 23 1 CAN1RST CAN1 reset 25 1 CAN2RST CAN2 reset 26 1 PWRRST Power interface reset 28 1 DACRST DAC reset 29 1 UART7RSTUART7 reset301 UART8RSTUART8 reset311 APB2RSTR APB2RSTR APB2 peripheral reset register 0x24 0x20 read-write 0x00000000 TIM1RST TIM1 reset 0 1 TIM1RSTread-writeResetReset the selected module1 TIM8RST TIM8 reset 1 1 USART1RST USART1 reset 4 1 USART6RST USART6 reset 5 1 ADCRST ADC interface reset (common to all ADCs) 8 1 SDIORST SDIO reset 11 1 SPI1RST SPI 1 reset 12 1 SYSCFGRST System configuration controller reset 14 1 TIM9RST TIM9 reset 16 1 TIM10RST TIM10 reset 17 1 TIM11RST TIM11 reset 18 1 SPI6RSTSPI6 reset211 SAI1RSTSAI1 reset221 LTDCRSTLTDC reset261 SPI4RSTSPI4 reset131 SPI5RSTSPI5 reset201 AHB1ENR AHB1ENR AHB1 peripheral clock register 0x30 0x20 read-write 0x00100000 OTGHSULPIEN USB OTG HSULPI clock enable 30 1 OTGHSEN USB OTG HS clock enable 29 1 ETHMACPTPEN Ethernet PTP clock enable 28 1 ETHMACRXEN Ethernet Reception clock enable 27 1 ETHMACTXEN Ethernet Transmission clock enable 26 1 ETHMACEN Ethernet MAC clock enable 25 1 DMA2EN DMA2 clock enable 22 1 DMA1EN DMA1 clock enable 21 1 CCMDATARAMEN CCM data RAM clock enable 20 1 BKPSRAMEN Backup SRAM interface clock enable 18 1 CRCEN CRC clock enable 12 1 GPIOIEN IO port I clock enable 8 1 GPIOHEN IO port H clock enable 7 1 GPIOGEN IO port G clock enable 6 1 GPIOFEN IO port F clock enable 5 1 GPIOEEN IO port E clock enable 4 1 GPIODEN IO port D clock enable 3 1 GPIOCEN IO port C clock enable 2 1 GPIOBEN IO port B clock enable 1 1 GPIOAEN IO port A clock enable 0 1 GPIOAENread-writeDisabledThe selected clock is disabled0EnabledThe selected clock is enabled1 DMA2DENDMA2D clock enable231 GPIOJENIO port J clock enable91 GPIOKENIO port K clock enable101 AHB2ENR AHB2ENR AHB2 peripheral clock enable register 0x34 0x20 read-write 0x00000000 OTGFSEN USB OTG FS clock enable 7 1 RNGEN Random number generator clock enable 6 1 HASHEN Hash modules clock enable 5 1 CRYPEN Cryptographic modules clock enable 4 1 DCMIEN Camera interface enable 0 1 DCMIENread-writeDisabledThe selected clock is disabled0EnabledThe selected clock is enabled1 AHB3ENR AHB3ENR AHB3 peripheral clock enable register 0x38 0x20 read-write 0x00000000 FMCEN Flexible memory controller module clock enable 0 1 FMCENread-writeDisabledThe selected clock is disabled0EnabledThe selected clock is enabled1 APB1ENR APB1ENR APB1 peripheral clock enable register 0x40 0x20 read-write 0x00000000 TIM2EN TIM2 clock enable 0 1 TIM2ENread-writeDisabledThe selected clock is disabled0EnabledThe selected clock is enabled1 TIM3EN TIM3 clock enable 1 1 TIM4EN TIM4 clock enable 2 1 TIM5EN TIM5 clock enable 3 1 TIM6EN TIM6 clock enable 4 1 TIM7EN TIM7 clock enable 5 1 TIM12EN TIM12 clock enable 6 1 TIM13EN TIM13 clock enable 7 1 TIM14EN TIM14 clock enable 8 1 WWDGEN Window watchdog clock enable 11 1 SPI2EN SPI2 clock enable 14 1 SPI3EN SPI3 clock enable 15 1 USART2EN USART 2 clock enable 17 1 USART3EN USART3 clock enable 18 1 UART4EN UART4 clock enable 19 1 UART5EN UART5 clock enable 20 1 I2C1EN I2C1 clock enable 21 1 I2C2EN I2C2 clock enable 22 1 I2C3EN I2C3 clock enable 23 1 CAN1EN CAN 1 clock enable 25 1 CAN2EN CAN 2 clock enable 26 1 PWREN Power interface clock enable 28 1 DACEN DAC interface clock enable 29 1 UART7ENUART7 clock enable301 UART8ENUART8 clock enable311 APB2ENR APB2ENR APB2 peripheral clock enable register 0x44 0x20 read-write 0x00000000 TIM1EN TIM1 clock enable 0 1 TIM1ENread-writeDisabledThe selected clock is disabled0EnabledThe selected clock is enabled1 TIM8EN TIM8 clock enable 1 1 USART1EN USART1 clock enable 4 1 USART6EN USART6 clock enable 5 1 ADC1EN ADC1 clock enable 8 1 ADC2EN ADC2 clock enable 9 1 ADC3EN ADC3 clock enable 10 1 SDIOEN SDIO clock enable 11 1 SPI1EN SPI1 clock enable 12 1 SYSCFGEN System configuration controller clock enable 14 1 TIM9EN TIM9 clock enable 16 1 TIM10EN TIM10 clock enable 17 1 TIM11EN TIM11 clock enable 18 1 SPI6ENSPI6 clock enable211 SAI1ENSAI1 clock enable221 LTDCENLTDC clock enable261 SPI4ENSPI4 clock enable131 SPI5ENSPI5 clock enable201 AHB1LPENR AHB1LPENR AHB1 peripheral clock enable in low power mode register 0x50 0x20 read-write 0x7E6791FF GPIOALPEN IO port A clock enable during sleep mode 0 1 GPIOALPENread-writeDisabledInSleepSelected module is disabled during Sleep mode0EnabledInSleepSelected module is enabled during Sleep mode1 GPIOBLPEN IO port B clock enable during Sleep mode 1 1 GPIOCLPEN IO port C clock enable during Sleep mode 2 1 GPIODLPEN IO port D clock enable during Sleep mode 3 1 GPIOELPEN IO port E clock enable during Sleep mode 4 1 GPIOFLPEN IO port F clock enable during Sleep mode 5 1 GPIOGLPEN IO port G clock enable during Sleep mode 6 1 GPIOHLPEN IO port H clock enable during Sleep mode 7 1 GPIOILPEN IO port I clock enable during Sleep mode 8 1 CRCLPEN CRC clock enable during Sleep mode 12 1 FLITFLPEN Flash interface clock enable during Sleep mode 15 1 SRAM1LPEN SRAM 1interface clock enable during Sleep mode 16 1 SRAM2LPEN SRAM 2 interface clock enable during Sleep mode 17 1 BKPSRAMLPEN Backup SRAM interface clock enable during Sleep mode 18 1 DMA1LPEN DMA1 clock enable during Sleep mode 21 1 DMA2LPEN DMA2 clock enable during Sleep mode 22 1 ETHMACLPEN Ethernet MAC clock enable during Sleep mode 25 1 ETHMACTXLPEN Ethernet transmission clock enable during Sleep mode 26 1 ETHMACRXLPEN Ethernet reception clock enable during Sleep mode 27 1 ETHMACPTPLPEN Ethernet PTP clock enable during Sleep mode 28 1 OTGHSLPEN USB OTG HS clock enable during Sleep mode 29 1 OTGHSULPILPEN USB OTG HS ULPI clock enable during Sleep mode 30 1 SRAM3LPENSRAM3 interface clock enable during Sleep mode191 DMA2DLPENDMA2D clock enable during Sleep mode231 GPIOJLPENIO port J clock enable during Sleep mode91 GPIOKLPENIO port K clock enable during Sleep mode101 AHB2LPENR AHB2LPENR AHB2 peripheral clock enable in low power mode register 0x54 0x20 read-write 0x000000F1 OTGFSLPEN USB OTG FS clock enable during Sleep mode 7 1 RNGLPEN Random number generator clock enable during Sleep mode 6 1 HASHLPEN Hash modules clock enable during Sleep mode 5 1 CRYPLPEN Cryptography modules clock enable during Sleep mode 4 1 DCMILPEN Camera interface enable during Sleep mode 0 1 DCMILPENread-writeDisabledInSleepSelected module is disabled during Sleep mode0EnabledInSleepSelected module is enabled during Sleep mode1 AHB3LPENR AHB3LPENR AHB3 peripheral clock enable in low power mode register 0x58 0x20 read-write 0x00000001 FMCLPEN Flexible memory controller module clock enable during Sleep mode 0 1 FMCLPENread-writeDisabledInSleepSelected module is disabled during Sleep mode0EnabledInSleepSelected module is enabled during Sleep mode1 APB1LPENR APB1LPENR APB1 peripheral clock enable in low power mode register 0x60 0x20 read-write 0x36FEC9FF TIM2LPEN TIM2 clock enable during Sleep mode 0 1 TIM2LPENread-writeDisabledInSleepSelected module is disabled during Sleep mode0EnabledInSleepSelected module is enabled during Sleep mode1 TIM3LPEN TIM3 clock enable during Sleep mode 1 1 TIM4LPEN TIM4 clock enable during Sleep mode 2 1 TIM5LPEN TIM5 clock enable during Sleep mode 3 1 TIM6LPEN TIM6 clock enable during Sleep mode 4 1 TIM7LPEN TIM7 clock enable during Sleep mode 5 1 TIM12LPEN TIM12 clock enable during Sleep mode 6 1 TIM13LPEN TIM13 clock enable during Sleep mode 7 1 TIM14LPEN TIM14 clock enable during Sleep mode 8 1 WWDGLPEN Window watchdog clock enable during Sleep mode 11 1 SPI2LPEN SPI2 clock enable during Sleep mode 14 1 SPI3LPEN SPI3 clock enable during Sleep mode 15 1 USART2LPEN USART2 clock enable during Sleep mode 17 1 USART3LPEN USART3 clock enable during Sleep mode 18 1 UART4LPEN UART4 clock enable during Sleep mode 19 1 UART5LPEN UART5 clock enable during Sleep mode 20 1 I2C1LPEN I2C1 clock enable during Sleep mode 21 1 I2C2LPEN I2C2 clock enable during Sleep mode 22 1 I2C3LPEN I2C3 clock enable during Sleep mode 23 1 CAN1LPEN CAN 1 clock enable during Sleep mode 25 1 CAN2LPEN CAN 2 clock enable during Sleep mode 26 1 PWRLPEN Power interface clock enable during Sleep mode 28 1 DACLPEN DAC interface clock enable during Sleep mode 29 1 UART7LPENUART7 clock enable during Sleep mode301 UART8LPENUART8 clock enable during Sleep mode311 APB2LPENR APB2LPENR APB2 peripheral clock enabled in low power mode register 0x64 0x20 read-write 0x00075F33 TIM1LPEN TIM1 clock enable during Sleep mode 0 1 TIM1LPENread-writeDisabledInSleepSelected module is disabled during Sleep mode0EnabledInSleepSelected module is enabled during Sleep mode1 TIM8LPEN TIM8 clock enable during Sleep mode 1 1 USART1LPEN USART1 clock enable during Sleep mode 4 1 USART6LPEN USART6 clock enable during Sleep mode 5 1 ADC1LPEN ADC1 clock enable during Sleep mode 8 1 ADC2LPEN ADC2 clock enable during Sleep mode 9 1 ADC3LPEN ADC 3 clock enable during Sleep mode 10 1 SDIOLPEN SDIO clock enable during Sleep mode 11 1 SPI1LPEN SPI 1 clock enable during Sleep mode 12 1 SYSCFGLPEN System configuration controller clock enable during Sleep mode 14 1 TIM9LPEN TIM9 clock enable during sleep mode 16 1 TIM10LPEN TIM10 clock enable during Sleep mode 17 1 TIM11LPEN TIM11 clock enable during Sleep mode 18 1 SPI6LPENSPI6 clock enable during Sleep mode211 SAI1LPENSAI1 clock enable during Sleep mode221 LTDCLPENLTDC clock enable during Sleep mode261 SPI4LPENSPI4 clock enable during Sleep mode131 SPI5LPENSPI5 clock enable during Sleep mode201 BDCR BDCR Backup domain control register 0x70 0x20 0x00000000 BDRST Backup domain software reset 16 1 read-write BDRSTread-writeDisabledReset not activated0EnabledReset the entire RTC domain1 RTCEN RTC clock enable 15 1 read-write RTCENread-writeDisabledRTC clock disabled0EnabledRTC clock enabled1 LSEBYP External low-speed oscillator bypass 2 1 read-write LSEBYPread-writeNotBypassedLSE crystal oscillator not bypassed0BypassedLSE crystal oscillator bypassed with external clock1 LSERDY External low-speed oscillator ready 1 1 read-only LSERDYRreadNotReadyLSE oscillator not ready0ReadyLSE oscillator ready1 LSEON External low-speed oscillator enable 0 1 read-write LSEONread-writeOffLSE oscillator Off0OnLSE oscillator On1 RTCSELRTC clock source selection82RTCSELread-writeNoClockNo clock0LSELSE oscillator clock used as RTC clock1LSILSI oscillator clock used as RTC clock2HSEHSE oscillator clock divided by a prescaler used as RTC clock3 CSR CSR clock control & status register 0x74 0x20 0x0E000000 LPWRRSTF Low-power reset flag 31 1 read-write WWDGRSTF Window watchdog reset flag 30 1 read-write WDGRSTF Independent watchdog reset flag 29 1 read-write SFTRSTF Software reset flag 28 1 read-write PORRSTF POR/PDR reset flag 27 1 read-write PADRSTF PIN reset flag 26 1 read-write BORRSTF BOR reset flag 25 1 read-write BORRSTFRreadNoResetNo reset has occured0ResetA reset has occured1 RMVF Remove reset flag 24 1 read-write RMVFWwriteClearClears the reset flag1 LSIRDY Internal low-speed oscillator ready 1 1 read-only LSIRDYRreadNotReadyLSI oscillator not ready0ReadyLSI oscillator ready1 LSION Internal low-speed oscillator enable 0 1 read-write LSIONread-writeOffLSI oscillator Off0OnLSI oscillator On1 SSCGR SSCGR spread spectrum clock generation register 0x80 0x20 read-write 0x00000000 SSCGEN Spread spectrum modulation enable 31 1 SSCGENread-writeDisabledSpread spectrum modulation disabled0EnabledSpread spectrum modulation enabled1 SPREADSEL Spread Select 30 1 SPREADSELread-writeCenterCenter spread0DownDown spread1 INCSTEP Incrementation step 13 15 032767 MODPER Modulation period 0 13 08191 PLLI2SCFGR PLLI2SCFGR PLLI2S configuration register 0x84 0x20 read-write 0x20003000 PLLI2SR PLLI2S division factor for I2S clocks 28 3 27 PLLI2SQ PLLI2S division factor for SAI1 clock 24 4 215 PLLI2SN PLLI2S multiplication factor for VCO 6 9 50432 DCKCFGR DCKCFGR RCC Dedicated Clock Configuration Register 0x8C 0x20 read-write 0x00000000 PLLI2SDIVQ PLLI2S division factor for SAI1 clock 0 5 PLLI2SDIVQread-writeDiv1PLLI2SDIVQ = /10Div2PLLI2SDIVQ = /21Div3PLLI2SDIVQ = /32Div4PLLI2SDIVQ = /43Div5PLLI2SDIVQ = /54Div6PLLI2SDIVQ = /65Div7PLLI2SDIVQ = /76Div8PLLI2SDIVQ = /87Div9PLLI2SDIVQ = /98Div10PLLI2SDIVQ = /109Div11PLLI2SDIVQ = /1110Div12PLLI2SDIVQ = /1211Div13PLLI2SDIVQ = /1312Div14PLLI2SDIVQ = /1413Div15PLLI2SDIVQ = /1514Div16PLLI2SDIVQ = /1615Div17PLLI2SDIVQ = /1716Div18PLLI2SDIVQ = /1817Div19PLLI2SDIVQ = /1918Div20PLLI2SDIVQ = /2019Div21PLLI2SDIVQ = /2120Div22PLLI2SDIVQ = /2221Div23PLLI2SDIVQ = /2322Div24PLLI2SDIVQ = /2423Div25PLLI2SDIVQ = /2524Div26PLLI2SDIVQ = /2625Div27PLLI2SDIVQ = /2726Div28PLLI2SDIVQ = /2827Div29PLLI2SDIVQ = /2928Div30PLLI2SDIVQ = /3029Div31PLLI2SDIVQ = /3130Div32PLLI2SDIVQ = /3231 PLLSAIDIVQ PLLSAI division factor for SAI1 clock 8 5 PLLSAIDIVQread-writeDiv1PLLSAIDIVQ = /10Div2PLLSAIDIVQ = /21Div3PLLSAIDIVQ = /32Div4PLLSAIDIVQ = /43Div5PLLSAIDIVQ = /54Div6PLLSAIDIVQ = /65Div7PLLSAIDIVQ = /76Div8PLLSAIDIVQ = /87Div9PLLSAIDIVQ = /98Div10PLLSAIDIVQ = /109Div11PLLSAIDIVQ = /1110Div12PLLSAIDIVQ = /1211Div13PLLSAIDIVQ = /1312Div14PLLSAIDIVQ = /1413Div15PLLSAIDIVQ = /1514Div16PLLSAIDIVQ = /1615Div17PLLSAIDIVQ = /1716Div18PLLSAIDIVQ = /1817Div19PLLSAIDIVQ = /1918Div20PLLSAIDIVQ = /2019Div21PLLSAIDIVQ = /2120Div22PLLSAIDIVQ = /2221Div23PLLSAIDIVQ = /2322Div24PLLSAIDIVQ = /2423Div25PLLSAIDIVQ = /2524Div26PLLSAIDIVQ = /2625Div27PLLSAIDIVQ = /2726Div28PLLSAIDIVQ = /2827Div29PLLSAIDIVQ = /2928Div30PLLSAIDIVQ = /3029Div31PLLSAIDIVQ = /3130Div32PLLSAIDIVQ = /3231 PLLSAIDIVR division factor for LCD_CLK 16 2 PLLSAIDIVRread-writeDiv2PLLSAIDIVR = /20Div4PLLSAIDIVR = /41Div8PLLSAIDIVR = /82Div16PLLSAIDIVR = /163 SAI1ASRC SAI1-A clock source selection 20 2 SAI1ASRCread-writePLLSAISAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ0PLLI2SSAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ1I2S_CKINSAI1-A clock frequency = Alternate function input frequency2 SAI1BSRC SAI1-B clock source selection 22 2 SAI1BSRCread-writePLLSAISAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ0PLLI2SSAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ1I2S_CKINSAI1-B clock frequency = Alternate function input frequency2 TIMPRE Timers clocks prescalers selection 24 1 TIMPREread-writeMul2If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx0Mul4If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx1 PLLSAICFGR PLLSAICFGR RCC PLL configuration register 0x88 0x20 read-write 0x24003000 PLLSAIR PLLSAI division factor for LCD clock 28 3 27 PLLSAIQ PLLSAI division factor for SAI1 clock 24 4 215 PLLSAIN PLLSAI division factor for VCO 6 9 50432 GPIOK General-purpose I/Os GPIO 0x40022800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000000 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER0read-writeInputInput mode (reset state)0OutputGeneral purpose output mode1AlternateAlternate function mode2AnalogAnalog mode3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OT0read-writePushPullOutput push-pull (reset state)0OpenDrainOutput open-drain1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR0read-writeLowSpeedLow speed0MediumSpeedMedium speed1HighSpeedHigh speed2VeryHighSpeedVery high speed3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR0read-writeFloatingNo pull-up, pull-down0PullUpPull-up1PullDownPull-down2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 IDR0read-writeHighInput is logic high1LowInput is logic low0 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 ODR0read-writeHighSet output to logic high1LowSet output to logic low0 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BR0WwriteResetResets the corresponding ODRx bit1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 BS0WwriteSetSets the corresponding ODRx bit1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCKKread-writeNotActivePort configuration lock key not active0ActivePort configuration lock key active1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK10read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK0read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL0read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF8AF88AF9AF99AF10AF1010AF11AF1111AF12AF1212AF13AF1313AF14AF1414AF15AF1515 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH8read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF8AF88AF9AF99AF10AF1010AF11AF1111AF12AF1212AF13AF1313AF14AF1414AF15AF1515 GPIOJ 0x40022400 GPIOI 0x40022000 GPIOH 0x40021C00 GPIOG 0x40021800 GPIOF 0x40021400 GPIOE 0x40021000 GPIOD 0X40020C00 GPIOC 0x40020800 GPIOB General-purpose I/Os GPIO 0x40020400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000280 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER0read-writeInputInput mode (reset state)0OutputGeneral purpose output mode1AlternateAlternate function mode2AnalogAnalog mode3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OT0read-writePushPullOutput push-pull (reset state)0OpenDrainOutput open-drain1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR0read-writeLowSpeedLow speed0MediumSpeedMedium speed1HighSpeedHigh speed2VeryHighSpeedVery high speed3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR0read-writeFloatingNo pull-up, pull-down0PullUpPull-up1PullDownPull-down2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 IDR0read-writeHighInput is logic high1LowInput is logic low0 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 ODR0read-writeHighSet output to logic high1LowSet output to logic low0 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BR0WwriteResetResets the corresponding ODRx bit1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 BS0WwriteSetSets the corresponding ODRx bit1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCKKread-writeNotActivePort configuration lock key not active0ActivePort configuration lock key active1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK10read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK0read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL0read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF8AF88AF9AF99AF10AF1010AF11AF1111AF12AF1212AF13AF1313AF14AF1414AF15AF1515 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH8read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF8AF88AF9AF99AF10AF1010AF11AF1111AF12AF1212AF13AF1313AF14AF1414AF15AF1515 GPIOA General-purpose I/Os GPIO 0x40020000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xA8000000 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 MODER0read-writeInputInput mode (reset state)0OutputGeneral purpose output mode1AlternateAlternate function mode2AnalogAnalog mode3 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OT0read-writePushPullOutput push-pull (reset state)0OpenDrainOutput open-drain1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 OSPEEDR0read-writeLowSpeedLow speed0MediumSpeedMedium speed1HighSpeedHigh speed2VeryHighSpeedVery high speed3 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR0read-writeFloatingNo pull-up, pull-down0PullUpPull-up1PullDownPull-down2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 IDR0read-writeHighInput is logic high1LowInput is logic low0 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 ODR0read-writeHighSet output to logic high1LowSet output to logic low0 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BR0WwriteResetResets the corresponding ODRx bit1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 BS0WwriteSetSets the corresponding ODRx bit1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCKKread-writeNotActivePort configuration lock key not active0ActivePort configuration lock key active1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK10read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 LCK0read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRL0read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF8AF88AF9AF99AF10AF1010AF11AF1111AF12AF1212AF13AF1313AF14AF1414AF15AF1515 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 AFRH8read-writeAF0AF00AF1AF11AF2AF22AF3AF33AF4AF44AF5AF55AF6AF66AF7AF77AF8AF88AF9AF99AF10AF1010AF11AF1111AF12AF1212AF13AF1313AF14AF1414AF15AF1515 SYSCFG System configuration controller SYSCFG 0x40013800 0x0 0x400 registers MEMRM MEMRM memory remap register 0x0 0x20 read-write 0x00000000 MEM_MODE Memory mapping selection 0 3 FB_MODE Flash bank mode selection 8 1 SWP_FMC FMC memory mapping swap 10 2 PMC PMC peripheral mode configuration register 0x4 0x20 read-write 0x00000000 MII_RMII_SEL Ethernet PHY interface selection 23 1 ADC1DC2 ADC1DC2 16 1 ADC2DC2 ADC2DC2 17 1 ADC3DC2 ADC3DC2 18 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x0000 EXTI3 EXTI x configuration (x = 0 to 3) 12 4 EXTI2 EXTI x configuration (x = 0 to 3) 8 4 EXTI1 EXTI x configuration (x = 0 to 3) 4 4 EXTI0 EXTI x configuration (x = 0 to 3) 0 4 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x0000 EXTI7 EXTI x configuration (x = 4 to 7) 12 4 EXTI6 EXTI x configuration (x = 4 to 7) 8 4 EXTI5 EXTI x configuration (x = 4 to 7) 4 4 EXTI4 EXTI x configuration (x = 4 to 7) 0 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x0000 EXTI11 EXTI x configuration (x = 8 to 11) 12 4 EXTI10 EXTI10 8 4 EXTI9 EXTI x configuration (x = 8 to 11) 4 4 EXTI8 EXTI x configuration (x = 8 to 11) 0 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x0000 EXTI15 EXTI x configuration (x = 12 to 15) 12 4 EXTI14 EXTI x configuration (x = 12 to 15) 8 4 EXTI13 EXTI x configuration (x = 12 to 15) 4 4 EXTI12 EXTI x configuration (x = 12 to 15) 0 4 CMPCR CMPCR Compensation cell control register 0x20 0x20 read-only 0x00000000 READY READY 8 1 CMP_PD Compensation cell power-down 0 1 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 35 SPI1 SPI1 global interrupt 35 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 BIDIMODE Bidirectional data mode enable 15 1 BIDIMODEread-writeUnidirectional2-line unidirectional data mode selected0Bidirectional1-line bidirectional data mode selected1 BIDIOE Output enable in bidirectional mode 14 1 BIDIOEread-writeOutputDisabledOutput disabled (receive-only mode)0OutputEnabledOutput enabled (transmit-only mode)1 CRCEN Hardware CRC calculation enable 13 1 CRCENread-writeDisabledCRC calculation disabled0EnabledCRC calculation enabled1 CRCNEXT CRC transfer next 12 1 CRCNEXTread-writeTxBufferNext transmit value is from Tx buffer0CRCNext transmit value is from Tx CRC register1 DFF Data frame format 11 1 DFFread-writeEightBit8-bit data frame format is selected for transmission/reception0SixteenBit16-bit data frame format is selected for transmission/reception1 RXONLY Receive only 10 1 RXONLYread-writeFullDuplexFull duplex (Transmit and receive)0OutputDisabledOutput disabled (Receive-only mode)1 SSM Software slave management 9 1 SSMread-writeDisabledSoftware slave management disabled0EnabledSoftware slave management enabled1 SSI Internal slave select 8 1 SSIread-writeSlaveSelected0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored0SlaveNotSelected1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored1 LSBFIRST Frame format 7 1 LSBFIRSTread-writeMSBFirstData is transmitted/received with the MSB first0LSBFirstData is transmitted/received with the LSB first1 SPE SPI enable 6 1 SPEread-writeDisabledPeripheral disabled0EnabledPeripheral enabled1 BR Baud rate control 3 3 BRread-writeDiv2f_PCLK / 20Div4f_PCLK / 41Div8f_PCLK / 82Div16f_PCLK / 163Div32f_PCLK / 324Div64f_PCLK / 645Div128f_PCLK / 1286Div256f_PCLK / 2567 MSTR Master selection 2 1 MSTRread-writeSlaveSlave configuration0MasterMaster configuration1 CPOL Clock polarity 1 1 CPOLread-writeIdleLowCK to 0 when idle0IdleHighCK to 1 when idle1 CPHA Clock phase 0 1 CPHAread-writeFirstEdgeThe first clock transition is the first data capture edge0SecondEdgeThe second clock transition is the first data capture edge1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TXEIE Tx buffer empty interrupt enable 7 1 TXEIEread-writeMaskedTXE interrupt masked0NotMaskedTXE interrupt not masked1 RXNEIE RX buffer not empty interrupt enable 6 1 RXNEIEread-writeMaskedRXE interrupt masked0NotMaskedRXE interrupt not masked1 ERRIE Error interrupt enable 5 1 ERRIEread-writeMaskedError interrupt masked0NotMaskedError interrupt not masked1 FRF Frame format 4 1 FRFread-writeMotorolaSPI Motorola mode0TISPI TI mode1 SSOE SS output enable 2 1 SSOEread-writeDisabledSS output is disabled in master mode0EnabledSS output is enabled in master mode1 TXDMAEN Tx buffer DMA enable 1 1 TXDMAENread-writeDisabledTx buffer DMA disabled0EnabledTx buffer DMA enabled1 RXDMAEN Rx buffer DMA enable 0 1 RXDMAENread-writeDisabledRx buffer DMA disabled0EnabledRx buffer DMA enabled1 SR SR status register 0x8 0x20 0x0002 FRE TI frame format error 8 1 read-only FRERreadNoErrorNo frame format error0ErrorA frame format error occurred1 BSY Busy flag 7 1 read-only BSYRreadNotBusySPI not busy0BusySPI busy1 OVR Overrun flag 6 1 read-only OVRRreadNoOverrunNo overrun occurred0OverrunOverrun occurred1 MODF Mode fault 5 1 read-only MODFRreadNoFaultNo mode fault occurred0FaultMode fault occurred1 CRCERR CRC error flag 4 1 read-write CRCERRread-writeMatchCRC value received matches the SPIx_RXCRCR value0NoMatchCRC value received does not match the SPIx_RXCRCR value1 UDR Underrun flag 3 1 read-only UDRRreadNoUnderrunNo underrun occurred0UnderrunUnderrun occurred1 CHSIDE Channel side 2 1 read-only CHSIDEread-writeLeftChannel left has to be transmitted or has been received0RightChannel right has to be transmitted or has been received1 TXE Transmit buffer empty 1 1 read-only TXEread-writeNotEmptyTx buffer not empty0EmptyTx buffer empty1 RXNE Receive buffer not empty 0 1 read-only RXNEread-writeEmptyRx buffer empty0NotEmptyRx buffer not empty1 DR DR data register 0xC 0x20 read-write 0x0000 DR Data register 0 16 065535 CRCPR CRCPR CRC polynomial register 0x10 0x20 read-write 0x0007 CRCPOLY CRC polynomial register 0 16 065535 RXCRCR RXCRCR RX CRC register 0x14 0x20 read-only 0x0000 RxCRC Rx CRC register 0 16 065535 TXCRCR TXCRCR TX CRC register 0x18 0x20 read-only 0x0000 TxCRC Tx CRC register 0 16 065535 I2SCFGR I2SCFGR I2S configuration register 0x1C 0x20 read-write 0x0000 I2SMOD I2S mode selection 11 1 I2SMODread-writeSPIModeSPI mode is selected0I2SModeI2S mode is selected1 I2SE I2S Enable 10 1 I2SEread-writeDisabledI2S peripheral is disabled0EnabledI2S peripheral is enabled1 I2SCFG I2S configuration mode 8 2 I2SCFGread-writeSlaveTxSlave - transmit0SlaveRxSlave - receive1MasterTxMaster - transmit2MasterRxMaster - receive3 PCMSYNC PCM frame synchronization 7 1 PCMSYNCread-writeShortShort frame synchronisation0LongLong frame synchronisation1 I2SSTD I2S standard selection 4 2 I2SSTDread-writePhilipsI2S Philips standard0MSBMSB justified standard1LSBLSB justified standard2PCMPCM standard3 CKPOL Steady state clock polarity 3 1 CKPOLread-writeIdleLowI2S clock inactive state is low level0IdleHighI2S clock inactive state is high level1 DATLEN Data length to be transferred 1 2 DATLENread-writeSixteenBit16-bit data length0TwentyFourBit24-bit data length1ThirtyTwoBit32-bit data length2 CHLEN Channel length (number of bits per audio channel) 0 1 CHLENread-writeSixteenBit16-bit wide0ThirtyTwoBit32-bit wide1 I2SPR I2SPR I2S prescaler register 0x20 0x20 read-write 00000010 MCKOE Master clock output enable 9 1 MCKOEread-writeDisabledMaster clock output is disabled0EnabledMaster clock output is enabled1 ODD Odd factor for the prescaler 8 1 ODDread-writeEvenReal divider value is I2SDIV * 20OddReal divider value is (I2SDIV * 2) + 11 I2SDIV I2S Linear prescaler 0 8 2255 SPI2 0x40003800 SPI2 SPI2 global interrupt 36 SPI2 SPI2 global interrupt 36 SPI3 0x40003C00 SPI3 SPI3 global interrupt 51 SPI3 SPI3 global interrupt 51 I2S2ext 0x40003400 I2S3ext 0x40004000 SPI4 0x40013400 SPI4 SPI 4 global interrupt 84 SPI4 SPI 4 global interrupt 84 SPI5 0x40015000 SPI5 SPI 5 global interrupt 85 SPI5 SPI 5 global interrupt 85 SPI6 0x40015400 SPI6 SPI 6 global interrupt 86 SPI6 SPI 6 global interrupt 86 SDIO Secure digital input/output interface SDIO 0x40012C00 0x0 0x400 registers SDIO SDIO global interrupt 49 SDIO SDIO global interrupt 49 POWER POWER power control register 0x0 0x20 read-write 0x00000000 PWRCTRL PWRCTRL 0 2 PWRCTRLread-writePowerOffPower off0PowerOnPower on3 CLKCR CLKCR SDI clock control register 0x4 0x20 read-write 0x00000000 HWFC_EN HW Flow Control enable 14 1 HWFC_ENread-writeDisabledHW Flow Control is disabled0EnabledHW Flow Control is enabled1 NEGEDGE SDIO_CK dephasing selection bit 13 1 NEGEDGEread-writeRisingSDIO_CK generated on the rising edge0FallingSDIO_CK generated on the falling edge1 WIDBUS Wide bus mode enable bit 11 2 WIDBUSread-writeBusWidth11 lane wide bus0BusWidth44 lane wide bus1BusWidth88 lane wide bus2 BYPASS Clock divider bypass enable bit 10 1 BYPASSread-writeDisabledSDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal.0EnabledSDIOCLK directly drives the SDIO_CK output signal1 PWRSAV Power saving configuration bit 9 1 PWRSAVread-writeDisabledSDIO_CK is only enabled when the bus is active1EnabledSDIO_CK clock is always enabled0 CLKEN Clock enable bit 8 1 CLKENread-writeDisabledDisable clock0EnabledEnable clock1 CLKDIV Clock divide factor 0 8 0255 ARG ARG argument register 0x8 0x20 read-write 0x00000000 CMDARG Command argument 0 32 04294967295 CMD CMD command register 0xC 0x20 read-write 0x00000000 CE_ATACMD CE-ATA command 14 1 CE_ATACMDread-writeDisabledCE-ATA command disabled0EnabledCE-ATA command enabled1 nIEN not Interrupt Enable 13 1 nIENread-writeDisabledInterrupts to the CE-ATA not disabled0EnabledInterrupt to the CE-ATA are disabled1 ENCMDcompl Enable CMD completion 12 1 ENCMDcomplread-writeDisabledCommand complete signal disabled0EnabledCommand complete signal enabled1 SDIOSuspend SD I/O suspend command 11 1 SDIOSuspendread-writeDisabledNext command is not a SDIO suspend command0EnabledNext command send is a SDIO suspend command1 CPSMEN Command path state machine (CPSM) Enable bit 10 1 CPSMENread-writeDisabledCommand path state machine disabled0EnabledCommand path state machine enabled1 WAITPEND CPSM Waits for ends of data transfer (CmdPend internal signal). 9 1 WAITPENDread-writeDisabledDon't wait for data end0EnabledWait for end of data transfer signal before sending command1 WAITINT CPSM waits for interrupt request 8 1 WAITINTread-writeDisabledDon't wait for interrupt request0EnabledWait for interrupt request1 WAITRESP Wait for response bits 6 2 WAITRESPread-writeNoResponseNo response0ShortResponseShort response1NoResponse2No reponse2LongResponseLong reponse3 CMDINDEX Command index 0 6 063 RESPCMD RESPCMD command response register 0x10 0x20 read-only 0x00000000 RESPCMD Response command index 0 6 063 RESP1 RESP1 response 1..4 register 0x14 0x20 read-only 0x00000000 CARDSTATUS1 see Table 132. 0 32 04294967295 RESP2 RESP2 response 1..4 register 0x18 0x20 read-only 0x00000000 CARDSTATUS2 see Table 132. 0 32 04294967295 RESP3 RESP3 response 1..4 register 0x1C 0x20 read-only 0x00000000 CARDSTATUS3 see Table 132. 0 32 04294967295 RESP4 RESP4 response 1..4 register 0x20 0x20 read-only 0x00000000 CARDSTATUS4 see Table 132. 0 32 04294967295 DTIMER DTIMER data timer register 0x24 0x20 read-write 0x00000000 DATATIME Data timeout period 0 32 04294967295 DLEN DLEN data length register 0x28 0x20 read-write 0x00000000 DATALENGTH Data length value 0 25 033554431 DCTRL DCTRL data control register 0x2C 0x20 read-write 0x00000000 SDIOEN SD I/O enable functions 11 1 SDIOENread-writeDisabledSDIO operations disabled0EnabledSDIO operations enabled1 RWMOD Read wait mode 10 1 RWMODread-writeD2Read wait control stopping using SDIO_D20CkRead wait control using SDIO_CK1 RWSTOP Read wait stop 9 1 RWSTOPread-writeDisabledRead wait in progress if RWSTART is enabled0EnabledEnable for read wait stop if RWSTART is enabled1 RWSTART Read wait start 8 1 RWSTARTread-writeDisabledDon't start read wait operation0EnabledRead wait operation starts1 DBLOCKSIZE Data block size 4 4 015 DMAEN DMA enable bit 3 1 DMAENread-writeDisabledDma disabled0EnabledDma enabled1 DTMODE Data transfer mode selection 1: Stream or SDIO multibyte data transfer. 2 1 DTMODEread-writeBlockModeBloack data transfer0StreamModeStream or SDIO multibyte data transfer1 DTDIR Data transfer direction selection 1 1 DTDIRread-writeControllerToCardFrom controller to card0CardToControllerFrom card to controller1 DTEN DTEN 0 1 DTENread-writeDisabledDisabled0EnabledStart transfer1 DCOUNT DCOUNT data counter register 0x30 0x20 read-only 0x00000000 DATACOUNT Data count value 0 25 033554431 STA STA status register 0x34 0x20 read-only 0x00000000 CEATAEND CE-ATA command completion signal received for CMD61 23 1 CEATAENDread-writeNotReceivedCompletion signal not received0ReceivedCE-ATA command completion signal received for CMD611 SDIOIT SDIO interrupt received 22 1 SDIOITread-writeNotReceivedSDIO interrupt not receieved0ReceivedSDIO interrupt received1 RXDAVL Data available in receive FIFO 21 1 RXDAVLread-writeNotAvailableData not available in receive FIFO0AvailableData available in receive FIFO1 TXDAVL Data available in transmit FIFO 20 1 TXDAVLread-writeNotAvailableData not available in transmit FIFO0AvailableData available in transmit FIFO1 RXFIFOE Receive FIFO empty 19 1 RXFIFOEread-writeNotEmptyReceive FIFO not empty0EmptyReceive FIFO empty1 TXFIFOE Transmit FIFO empty 18 1 TXFIFOEread-writeNotEmptyTransmit FIFO not empty0EmptyTransmit FIFO empty. When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words.1 RXFIFOF Receive FIFO full 17 1 RXFIFOFread-writeNotFullTransmit FIFO not full0FullReceive FIFO full. When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full.1 TXFIFOF Transmit FIFO full 16 1 TXFIFOFread-writeNotFullTransmit FIFO not full0FullTransmit FIFO full1 RXFIFOHF Receive FIFO half full: there are at least 8 words in the FIFO 15 1 RXFIFOHFread-writeNotHalfFullReceive FIFO not half full0HalfFullReceive FIFO half full. At least 8 words in the FIFO1 TXFIFOHE Transmit FIFO half empty: at least 8 words can be written into the FIFO 14 1 TXFIFOHEread-writeNotHalfEmptyTransmit FIFO not half empty0HalfEmptyTransmit FIFO half empty. At least 8 words can be written into the FIFO1 RXACT Data receive in progress 13 1 RXACTread-writeNotInProgressData receive not in progress0InProgressData receive in progress1 TXACT Data transmit in progress 12 1 TXACTread-writeNotInProgressData transmit is not in progress0InProgressData transmit in progress1 CMDACT Command transfer in progress 11 1 CMDACTread-writeNotInProgressCommand transfer not in progress0InProgressCommand tranfer in progress1 DBCKEND Data block sent/received (CRC check passed) 10 1 DBCKENDread-writeNotTransferredData block not sent/received (CRC check failed)0TransferredData block sent/received (CRC check passed)1 STBITERR Start bit not detected on all data signals in wide bus mode 9 1 STBITERRread-writeDetectedNo start bit detected error0NotDetectedStart bit not detected error1 DATAEND Data end (data counter, SDIDCOUNT, is zero) 8 1 DATAENDread-writeDoneData end (DCOUNT, is zero)1NotDoneNot done0 CMDSENT Command sent (no response required) 7 1 CMDSENTread-writeNotSentCommand not sent0SentCommand sent (no response required)1 CMDREND Command response received (CRC check passed) 6 1 CMDRENDread-writeNotDoneCommand not done0DoneCommand response received (CRC check passed)1 RXOVERR Received FIFO overrun error 5 1 RXOVERRread-writeNoOverrunNo FIFO overrun error0OverrunReceive FIFO overrun error1 TXUNDERR Transmit FIFO underrun error 4 1 TXUNDERRread-writeNoUnderrunNo transmit FIFO underrun error0UnderrunTransmit FIFO underrun error1 DTIMEOUT Data timeout 3 1 DTIMEOUTread-writeNoTimeoutNo data timeout0TimeoutData timeout1 CTIMEOUT Command response timeout 2 1 CTIMEOUTread-writeNoTimeoutNo Command timeout0TimeoutCommand timeout1 DCRCFAIL Data block sent/received (CRC check failed) 1 1 DCRCFAILread-writeNotFailedNo Data block sent/received crc check fail0FailedData block sent/received crc failed1 CCRCFAIL Command response received (CRC check failed) 0 1 CCRCFAILread-writeNotFailedCommand response received, crc check passed0FailedCommand response received, crc check failed1 ICR ICR interrupt clear register 0x38 0x20 read-write 0x00000000 CEATAENDC CEATAEND flag clear bit 23 1 SDIOITC SDIOIT flag clear bit 22 1 DBCKENDC DBCKEND flag clear bit 10 1 STBITERRC STBITERR flag clear bit 9 1 DATAENDC DATAEND flag clear bit 8 1 CMDSENTC CMDSENT flag clear bit 7 1 CMDRENDC CMDREND flag clear bit 6 1 RXOVERRC RXOVERR flag clear bit 5 1 TXUNDERRC TXUNDERR flag clear bit 4 1 DTIMEOUTC DTIMEOUT flag clear bit 3 1 CTIMEOUTC CTIMEOUT flag clear bit 2 1 DCRCFAILC DCRCFAIL flag clear bit 1 1 CCRCFAILC CCRCFAIL flag clear bit 0 1 CCRCFAILCWwriteClearClear flag1 MASK MASK mask register 0x3C 0x20 read-write 0x00000000 CEATAENDIE CE-ATA command completion signal received interrupt enable 23 1 SDIOITIE SDIO mode interrupt received interrupt enable 22 1 RXDAVLIE Data available in Rx FIFO interrupt enable 21 1 TXDAVLIE Data available in Tx FIFO interrupt enable 20 1 RXFIFOEIE Rx FIFO empty interrupt enable 19 1 TXFIFOEIE Tx FIFO empty interrupt enable 18 1 RXFIFOFIE Rx FIFO full interrupt enable 17 1 TXFIFOFIE Tx FIFO full interrupt enable 16 1 RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 RXACTIE Data receive acting interrupt enable 13 1 TXACTIE Data transmit acting interrupt enable 12 1 CMDACTIE Command acting interrupt enable 11 1 DBCKENDIE Data block end interrupt enable 10 1 STBITERRIE Start bit error interrupt enable 9 1 DATAENDIE Data end interrupt enable 8 1 CMDSENTIE Command sent interrupt enable 7 1 CMDRENDIE Command response received interrupt enable 6 1 RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 DTIMEOUTIE Data timeout interrupt enable 3 1 CTIMEOUTIE Command timeout interrupt enable 2 1 DCRCFAILIE Data CRC fail interrupt enable 1 1 CCRCFAILIE Command CRC fail interrupt enable 0 1 CCRCFAILIEread-writeDisabledInterrupt disabled0EnabledInterrupt enabled1 FIFOCNT FIFOCNT FIFO counter register 0x48 0x20 read-only 0x00000000 FIFOCOUNT Remaining number of words to be written to or read from the FIFO. 0 24 016777215 FIFO FIFO data FIFO register 0x80 0x20 read-write 0x00000000 FIFOData Receive and transmit FIFO data 0 32 04294967295 ADC1 Analog-to-digital converter ADC 0x40012000 0x0 0x51 registers SR SR status register 0x0 0x20 read-write 0x00000000 OVR Overrun 5 1 OVRread-writeNoOverrunNo overrun occurred0OverrunOverrun occurred1 STRT Regular channel start flag 4 1 STRTread-writeNotStartedNo regular channel conversion started0StartedRegular channel conversion has started1 JSTRT Injected channel start flag 3 1 JSTRTread-writeNotStartedNo injected channel conversion started0StartedInjected channel conversion has started1 JEOC Injected channel end of conversion 2 1 JEOCread-writeNotCompleteConversion is not complete0CompleteConversion complete1 EOC Regular channel end of conversion 1 1 EOCread-writeNotCompleteConversion is not complete0CompleteConversion complete1 AWD Analog watchdog flag 0 1 AWDread-writeNoEventNo analog watchdog event occurred0EventAnalog watchdog event occurred1 CR1 CR1 control register 1 0x4 0x20 read-write 0x00000000 OVRIE Overrun interrupt enable 26 1 OVRIEread-writeDisabledOverrun interrupt disabled0EnabledOverrun interrupt enabled1 RES Resolution 24 2 RESread-writeTwelveBit12-bit (15 ADCCLK cycles)0TenBit10-bit (13 ADCCLK cycles)1EightBit8-bit (11 ADCCLK cycles)2SixBit6-bit (9 ADCCLK cycles)3 AWDEN Analog watchdog enable on regular channels 23 1 AWDENread-writeDisabledAnalog watchdog disabled on regular channels0EnabledAnalog watchdog enabled on regular channels1 JAWDEN Analog watchdog enable on injected channels 22 1 JAWDENread-writeDisabledAnalog watchdog disabled on injected channels0EnabledAnalog watchdog enabled on injected channels1 DISCNUM Discontinuous mode channel count 13 3 07 JDISCEN Discontinuous mode on injected channels 12 1 JDISCENread-writeDisabledDiscontinuous mode on injected channels disabled0EnabledDiscontinuous mode on injected channels enabled1 DISCEN Discontinuous mode on regular channels 11 1 DISCENread-writeDisabledDiscontinuous mode on regular channels disabled0EnabledDiscontinuous mode on regular channels enabled1 JAUTO Automatic injected group conversion 10 1 JAUTOread-writeDisabledAutomatic injected group conversion disabled0EnabledAutomatic injected group conversion enabled1 AWDSGL Enable the watchdog on a single channel in scan mode 9 1 AWDSGLread-writeAllChannelsAnalog watchdog enabled on all channels0SingleChannelAnalog watchdog enabled on a single channel1 SCAN Scan mode 8 1 SCANread-writeDisabledScan mode disabled0EnabledScan mode enabled1 JEOCIE Interrupt enable for injected channels 7 1 JEOCIEread-writeDisabledJEOC interrupt disabled0EnabledJEOC interrupt enabled1 AWDIE Analog watchdog interrupt enable 6 1 AWDIEread-writeDisabledAnalogue watchdog interrupt disabled0EnabledAnalogue watchdog interrupt enabled1 EOCIE Interrupt enable for EOC 5 1 EOCIEread-writeDisabledEOC interrupt disabled0EnabledEOC interrupt enabled1 AWDCH Analog watchdog channel select bits 0 5 018 CR2 CR2 control register 2 0x8 0x20 read-write 0x00000000 SWSTART Start conversion of regular channels 30 1 SWSTARTWwriteStartStarts conversion of regular channels1 EXTEN External trigger enable for regular channels 28 2 EXTENread-writeDisabledTrigger detection disabled0RisingEdgeTrigger detection on the rising edge1FallingEdgeTrigger detection on the falling edge2BothEdgesTrigger detection on both the rising and falling edges3 EXTSEL External event select for regular group 24 4 EXTSELread-writeTIM1CC1Timer 1 CC1 event0TIM1CC2Timer 1 CC2 event1TIM1CC3Timer 1 CC3 event2TIM2CC2Timer 2 CC2 event3TIM2CC3Timer 2 CC3 event4TIM2CC4Timer 2 CC4 event5TIM2TRGOTimer 2 TRGO event6 JSWSTART Start conversion of injected channels 22 1 JSWSTARTWwriteStartStarts conversion of injected channels1 JEXTEN External trigger enable for injected channels 20 2 JEXTENread-writeDisabledTrigger detection disabled0RisingEdgeTrigger detection on the rising edge1FallingEdgeTrigger detection on the falling edge2BothEdgesTrigger detection on both the rising and falling edges3 JEXTSEL External event select for injected group 16 4 JEXTSELread-writeTIM1TRGOTimer 1 TRGO event0TIM1CC4Timer 1 CC4 event1TIM2TRGOTimer 2 TRGO event2TIM2CC1Timer 2 CC1 event3TIM3CC4Timer 3 CC4 event4TIM4TRGOTimer 4 TRGO event5TIM8CC4Timer 8 CC4 event7TIM1TRGO2Timer 1 TRGO(2) event8TIM8TRGOTimer 8 TRGO event9TIM8TRGO2Timer 8 TRGO(2) event10TIM3CC3Timer 3 CC3 event11TIM5TRGOTimer 5 TRGO event12TIM3CC1Timer 3 CC1 event13TIM6TRGOTimer 6 TRGO event14 ALIGN Data alignment 11 1 ALIGNread-writeRightRight alignment0LeftLeft alignment1 EOCS End of conversion selection 10 1 EOCSread-writeEachSequenceThe EOC bit is set at the end of each sequence of regular conversions0EachConversionThe EOC bit is set at the end of each regular conversion1 DDS DMA disable selection (for single ADC mode) 9 1 DDSread-writeSingleNo new DMA request is issued after the last transfer0ContinuousDMA requests are issued as long as data are converted and DMA=11 DMA Direct memory access mode (for single ADC mode) 8 1 DMAread-writeDisabledDMA mode disabled0EnabledDMA mode enabled1 CONT Continuous conversion 1 1 CONTread-writeSingleSingle conversion mode0ContinuousContinuous conversion mode1 ADON A/D Converter ON / OFF 0 1 ADONread-writeDisabledDisable ADC conversion and go to power down mode0EnabledEnable ADC1 SMPR1 SMPR1 sample time register 1 0xC 0x20 read-write 0x00000000 SMP18 Channel 18 sampling time selection 24 3 SMP17Channel 17 sampling time selection213 SMP16Channel 16 sampling time selection183 SMP15Channel 15 sampling time selection153 SMP14Channel 14 sampling time selection123 SMP13Channel 13 sampling time selection93 SMP12Channel 12 sampling time selection63 SMP11Channel 11 sampling time selection33 SMP10Channel 10 sampling time selection03SMP10read-writeCycles33 cycles0Cycles1515 cycles1Cycles2828 cycles2Cycles5656 cycles3Cycles8484 cycles4Cycles112112 cycles5Cycles144144 cycles6Cycles480480 cycles7 SMPR2 SMPR2 sample time register 2 0x10 0x20 read-write 0x00000000 SMP9 Channel 9 sampling time selection 27 3 SMP8Channel 8 sampling time selection243 SMP7Channel 7 sampling time selection213 SMP6Channel 6 sampling time selection183 SMP5Channel 5 sampling time selection153 SMP4Channel 4 sampling time selection123 SMP3Channel 3 sampling time selection93 SMP2Channel 2 sampling time selection63 SMP1Channel 1 sampling time selection33 SMP0Channel 0 sampling time selection03SMP0read-writeCycles33 cycles0Cycles1515 cycles1Cycles2828 cycles2Cycles5656 cycles3Cycles8484 cycles4Cycles112112 cycles5Cycles144144 cycles6Cycles480480 cycles7 40x41,2,3,4JOFR%s JOFR1 injected channel data offset register x 0x14 0x20 read-write 0x00000000 JOFFSET Data offset for injected channel x 0 12 04095 HTR HTR watchdog higher threshold register 0x24 0x20 read-write 0x00000FFF HT Analog watchdog higher threshold 0 12 04095 LTR LTR watchdog lower threshold register 0x28 0x20 read-write 0x00000000 LT Analog watchdog lower threshold 0 12 04095 SQR1 SQR1 regular sequence register 1 0x2C 0x20 read-write 0x00000000 L Regular channel sequence length 20 4 015 SQ16 16th conversion in regular sequence 15 5 018 SQ15 15th conversion in regular sequence 10 5 018 SQ14 14th conversion in regular sequence 5 5 018 SQ13 13th conversion in regular sequence 0 5 018 SQR2 SQR2 regular sequence register 2 0x30 0x20 read-write 0x00000000 SQ12 12th conversion in regular sequence 25 5 018 SQ11 11th conversion in regular sequence 20 5 018 SQ10 10th conversion in regular sequence 15 5 018 SQ9 9th conversion in regular sequence 10 5 018 SQ8 8th conversion in regular sequence 5 5 018 SQ7 7th conversion in regular sequence 0 5 018 SQR3 SQR3 regular sequence register 3 0x34 0x20 read-write 0x00000000 SQ6 6th conversion in regular sequence 25 5 018 SQ5 5th conversion in regular sequence 20 5 018 SQ4 4th conversion in regular sequence 15 5 018 SQ3 3rd conversion in regular sequence 10 5 018 SQ2 2nd conversion in regular sequence 5 5 018 SQ1 1st conversion in regular sequence 0 5 018 JSQR JSQR injected sequence register 0x38 0x20 read-write 0x00000000 JL Injected sequence length 20 2 03 JSQ4 4th conversion in injected sequence 15 5 018 JSQ3 3rd conversion in injected sequence 10 5 018 JSQ2 2nd conversion in injected sequence 5 5 018 JSQ1 1st conversion in injected sequence 0 5 018 40x41,2,3,4JDR%s JDR1 injected data register x 0x3C 0x20 read-only 0x00000000 JDATA Injected data 0 16 DR DR regular data register 0x4C 0x20 read-only 0x00000000 DATA Regular data 0 16 ADC2 0x40012100 ADC ADC2 global interrupts 18 ADC ADC2 global interrupts 18 ADC3 0x40012200 USART6 0x40011400 USART6 USART6 global interrupt 71 USART6 USART6 global interrupt 71 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40011000 0x0 0x400 registers USART1 USART1 global interrupt 37 USART1 USART1 global interrupt 37 SR SR Status register 0x0 0x20 0x00C00000 CTS CTS flag 9 1 read-write LBD LIN break detection flag 8 1 read-write TXE Transmit data register empty 7 1 read-only TC Transmission complete 6 1 read-write RXNE Read data register not empty 5 1 read-write IDLE IDLE line detected 4 1 read-only ORE Overrun error 3 1 read-only NF Noise detected flag 2 1 read-only FE Framing error 1 1 read-only PE Parity error 0 1 read-only DR DR Data register 0x4 0x20 read-write 0x00000000 DR Data value 0 9 0511 BRR BRR Baud rate register 0x8 0x20 read-write 0x0000 DIV_Mantissa mantissa of USARTDIV 4 12 04095 DIV_Fraction fraction of USARTDIV 0 4 015 CR1 CR1 Control register 1 0xC 0x20 read-write 0x0000 OVER8 Oversampling mode 15 1 OVER8read-writeOversample16Oversampling by 160Oversample8Oversampling by 81 UE USART enable 13 1 UEread-writeDisabledUSART prescaler and outputs disabled0EnabledUSART enabled1 M Word length 12 1 Mread-writeM88 data bits0M99 data bits1 WAKE Wakeup method 11 1 WAKEread-writeIdleLineUSART wakeup on idle line0AddressMarkUSART wakeup on address mark1 PCE Parity control enable 10 1 PCEread-writeDisabledParity control disabled0EnabledParity control enabled1 PS Parity selection 9 1 PSread-writeEvenEven parity0OddOdd parity1 PEIE PE interrupt enable 8 1 PEIEread-writeDisabledPE interrupt disabled0EnabledPE interrupt enabled1 TXEIE TXE interrupt enable 7 1 TXEIEread-writeDisabledTXE interrupt disabled0EnabledTXE interrupt enabled1 TCIE Transmission complete interrupt enable 6 1 TCIEread-writeDisabledTC interrupt disabled0EnabledTC interrupt enabled1 RXNEIE RXNE interrupt enable 5 1 RXNEIEread-writeDisabledRXNE interrupt disabled0EnabledRXNE interrupt enabled1 IDLEIE IDLE interrupt enable 4 1 IDLEIEread-writeDisabledIDLE interrupt disabled0EnabledIDLE interrupt enabled1 TE Transmitter enable 3 1 TEread-writeDisabledTransmitter disabled0EnabledTransmitter enabled1 RE Receiver enable 2 1 REread-writeDisabledReceiver disabled0EnabledReceiver enabled1 RWU Receiver wakeup 1 1 RWUread-writeActiveReceiver in active mode0MuteReceiver in mute mode1 SBK Send break 0 1 SBKread-writeNoBreakNo break character is transmitted0BreakBreak character transmitted1 CR2 CR2 Control register 2 0x10 0x20 read-write 0x0000 LINEN LIN mode enable 14 1 LINENread-writeDisabledLIN mode disabled0EnabledLIN mode enabled1 STOP STOP bits 12 2 STOPread-writeStop11 stop bit0Stop0p50.5 stop bits1Stop22 stop bits2Stop1p51.5 stop bits3 CLKEN Clock enable 11 1 CLKENread-writeDisabledCK pin disabled0EnabledCK pin enabled1 CPOL Clock polarity 10 1 CPOLread-writeLowSteady low value on CK pin outside transmission window0HighSteady high value on CK pin outside transmission window1 CPHA Clock phase 9 1 CPHAread-writeFirstThe first clock transition is the first data capture edge0SecondThe second clock transition is the first data capture edge1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDIEread-writeDisabledLIN break detection interrupt disabled0EnabledLIN break detection interrupt enabled1 LBDL lin break detection length 5 1 LBDLread-writeLBDL1010-bit break detection0LBDL1111-bit break detection1 ADD Address of the USART node 0 4 015 CR3 CR3 Control register 3 0x14 0x20 read-write 0x0000 ONEBIT One sample bit method enable 11 1 ONEBITread-writeSample3Three sample bit method0Sample1One sample bit method1 CTSIE CTS interrupt enable 10 1 CTSIEread-writeDisabledCTS interrupt disabled0EnabledCTS interrupt enabled1 CTSE CTS enable 9 1 CTSEread-writeDisabledCTS hardware flow control disabled0EnabledCTS hardware flow control enabled1 RTSE RTS enable 8 1 RTSEread-writeDisabledRTS hardware flow control disabled0EnabledRTS hardware flow control enabled1 DMAT DMA enable transmitter 7 1 DMATread-writeDisabledDMA mode is disabled for transmission0EnabledDMA mode is enabled for transmission1 DMAR DMA enable receiver 6 1 DMARread-writeDisabledDMA mode is disabled for reception0EnabledDMA mode is enabled for reception1 SCEN Smartcard mode enable 5 1 SCENread-writeDisabledSmartcard mode disabled0EnabledSmartcard mode enabled1 NACK Smartcard NACK enable 4 1 NACKread-writeDisabledNACK transmission in case of parity error is disabled0EnabledNACK transmission during parity error is enabled1 HDSEL Half-duplex selection 3 1 HDSELread-writeFullDuplexHalf duplex mode is not selected0HalfDuplexHalf duplex mode is selected1 IRLP IrDA low-power 2 1 IRLPread-writeNormalNormal mode0LowPowerLow-power mode1 IREN IrDA mode enable 1 1 IRENread-writeDisabledIrDA disabled0EnabledIrDA enabled1 EIE Error interrupt enable 0 1 EIEread-writeDisabledError interrupt disabled0EnabledError interrupt enabled1 GTPR GTPR Guard time and prescaler register 0x18 0x20 read-write 0x0000 GT Guard time value 8 8 PSC Prescaler value 0 8 USART2 0x40004400 USART2 USART2 global interrupt 38 USART2 USART2 global interrupt 38 USART3 0x40004800 USART3 USART3 global interrupt 39 USART3 USART3 global interrupt 39 UART7 0x40007800 UART7 UART 7 global interrupt 82 UART7 UART 7 global interrupt 82 UART8 0x40007C00 UART8 UART 8 global interrupt 83 UART8 UART 8 global interrupt 83 DAC Digital-to-analog converter DAC 0x40007400 0x0 0x400 registers TIM6_DAC TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt 54 TIM6_DAC TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt 54 CR CR control register 0x0 0x20 read-write 0x00000000 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable 29 1 DMAEN2 DAC channel2 DMA enable 28 1 MAMP2 DAC channel2 mask/amplitude selector 24 4 015 WAVE2 DAC channel2 noise/triangle wave generation enable 22 2 WAVE2read-writeDisabledWave generation disabled0NoiseNoise wave generation enabled1TriangleTriangle wave generation enabled2 TSEL2 DAC channel2 trigger selection 19 3 TSEL2read-writeTIM6_TRGOTimer 6 TRGO event0TIM8_TRGOTimer 8 TRGO event1TIM7_TRGOTimer 7 TRGO event2TIM5_TRGOTimer 5 TRGO event3TIM2_TRGOTimer 2 TRGO event4TIM4_TRGOTimer 4 TRGO event5EXTI9EXTI line96SOFTWARESoftware trigger7 TEN2 DAC channel2 trigger enable 18 1 BOFF2 DAC channel2 output buffer disable 17 1 EN2 DAC channel2 enable 16 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable 13 1 DMAUDRIE1read-writeDisabledDAC channel X DMA Underrun Interrupt disabled0EnabledDAC channel X DMA Underrun Interrupt enabled1 DMAEN1 DAC channel1 DMA enable 12 1 DMAEN1read-writeDisabledDAC channel X DMA mode disabled0EnabledDAC channel X DMA mode enabled1 MAMP1 DAC channel1 mask/amplitude selector 8 4 015 WAVE1 DAC channel1 noise/triangle wave generation enable 6 2 WAVE1read-writeDisabledWave generation disabled0NoiseNoise wave generation enabled1TriangleTriangle wave generation enabled2 TSEL1 DAC channel1 trigger selection 3 3 TSEL1read-writeTIM6_TRGOTimer 6 TRGO event0TIM3_TRGOTimer 3 TRGO event1TIM7_TRGOTimer 7 TRGO event2TIM15_TRGOTimer 15 TRGO event3TIM2_TRGOTimer 2 TRGO event4EXTI9EXTI line96SOFTWARESoftware trigger7 TEN1 DAC channel1 trigger enable 2 1 TEN1read-writeDisabledDAC channel X trigger disabled0EnabledDAC channel X trigger enabled1 BOFF1 DAC channel1 output buffer disable 1 1 BOFF1read-writeEnabledDAC channel X output buffer enabled0DisabledDAC channel X output buffer disabled1 EN1 DAC channel1 enable 0 1 EN1read-writeDisabledDAC channel X disabled0EnabledDAC channel X enabled1 SWTRIGR SWTRIGR software trigger register 0x4 0x20 write-only 0x00000000 SWTRIG2 DAC channel2 software trigger 1 1 SWTRIG1 DAC channel1 software trigger 0 1 SWTRIG1read-writeDisabledDAC channel X software trigger disabled0EnabledDAC channel X software trigger enabled1 DHR12R1 DHR12R1 channel1 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data 0 12 04095 DHR12L1 DHR12L1 channel1 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data 4 12 04095 DHR8R1 DHR8R1 channel1 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data 0 8 0255 DHR12R2 DHR12R2 channel2 12-bit right aligned data holding register 0x14 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit right-aligned data 0 12 04095 DHR12L2 DHR12L2 channel2 12-bit left aligned data holding register 0x18 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit left-aligned data 4 12 04095 DHR8R2 DHR8R2 channel2 8-bit right-aligned data holding register 0x1C 0x20 read-write 0x00000000 DACC2DHR DAC channel2 8-bit right-aligned data 0 8 0255 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit right-aligned data 16 12 04095 DACC1DHR DAC channel1 12-bit right-aligned data 0 12 04095 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit left-aligned data 20 12 04095 DACC1DHR DAC channel1 12-bit left-aligned data 4 12 04095 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 DACC2DHR DAC channel2 8-bit right-aligned data 8 8 0255 DACC1DHR DAC channel1 8-bit right-aligned data 0 8 0255 DOR1 DOR1 channel1 data output register 0x2C 0x20 read-only 0x00000000 DACC1DOR DAC channel1 data output 0 12 DOR2 DOR2 channel2 data output register 0x30 0x20 read-only 0x00000000 DACC2DOR DAC channel2 data output 0 12 SR SR status register 0x34 0x20 read-write 0x00000000 DMAUDR2 DAC channel2 DMA underrun flag 29 1 DMAUDR1 DAC channel1 DMA underrun flag 13 1 DMAUDR1read-writeNoUnderrunNo DMA underrun error condition occurred for DAC channel X0UnderrunDMA underrun error condition occurred for DAC channel X1 PWR Power control PWR 0x40007000 0x0 0x400 registers PVD PVD through EXTI line detection interrupt 1 PVD PVD through EXTI line detection interrupt 1 CR CR power control register 0x0 0x20 read-write 0x0000C000 LPDS Low-power deep sleep 0 1 PDDS Power down deepsleep 1 1 CWUF Clear wakeup flag 2 1 CSBF Clear standby flag 3 1 PVDE Power voltage detector enable 4 1 PLS PVD level selection 5 3 DBP Disable backup domain write protection 8 1 FPDS Flash power down in Stop mode 9 1 LPLVDS Low-Power Regulator Low Voltage in deepsleep 10 1 MRLVDS Main regulator low voltage in deepsleep mode 11 1 VOS Regulator voltage scaling output selection 14 2 ODEN Over-drive enable 16 1 ODSWEN Over-drive switching enabled 17 1 UDEN Under-drive enable in stop mode 18 2 CSR CSR power control/status register 0x4 0x20 0x00000000 WUF Wakeup flag 0 1 read-only SBF Standby flag 1 1 read-only PVDO PVD output 2 1 read-only BRR Backup regulator ready 3 1 read-only EWUP Enable WKUP pin 8 1 read-write BRE Backup regulator enable 9 1 read-write VOSRDY Regulator voltage scaling output selection ready bit 14 1 read-write ODRDY Over-drive mode ready 16 1 read-only ODSWRDY Over-drive mode switching ready 17 1 read-only UDRDY Under-drive ready flag 18 2 read-write IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x20 write-only 0x00000000 KEY Key value (write only, read 0000h) 0 16 KEYread-writeEnableEnable access to PR, RLR and WINR registers (0x5555)21845ResetReset the watchdog value (0xAAAA)43690StartStart the watchdog (0xCCCC)52428 PR PR Prescaler register 0x4 0x20 read-write 0x00000000 PR Prescaler divider 0 3 PRread-writeDivideBy4Divider /40DivideBy8Divider /81DivideBy16Divider /162DivideBy32Divider /323DivideBy64Divider /644DivideBy128Divider /1285DivideBy256Divider /2566DivideBy256bisDivider /2567 RLR RLR Reload register 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 04095 SR SR Status register 0xC 0x20 read-only 0x00000000 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 WWDG Window Watchdog interrupt 0 CR CR Control register 0x0 0x20 read-write 0x7F WDGA Activation bit 7 1 WDGAread-writeDisabledWatchdog disabled0EnabledWatchdog enabled1 T 7-bit counter (MSB to LSB) 0 7 0127 CFR CFR Configuration register 0x4 0x20 read-write 0x7F EWI Early wakeup interrupt 9 1 EWIWwriteEnableinterrupt occurs whenever the counter reaches the value 0x401 W 7-bit window value 0 7 0127 WDGTBTimer base72WDGTBread-writeDiv1Counter clock (PCLK1 div 4096) div 10Div2Counter clock (PCLK1 div 4096) div 21Div4Counter clock (PCLK1 div 4096) div 42Div8Counter clock (PCLK1 div 4096) div 83 SR SR Status register 0x8 0x20 read-write 0x00 EWIF Early wakeup interrupt flag 0 1 EWIFRreadPendingThe EWI Interrupt Service Routine has been triggered1FinishedThe EWI Interrupt Service Routine has been serviced0 EWIFWwriteFinishedThe EWI Interrupt Service Routine has been serviced0 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC_WKUP RTC Wakeup interrupt through the EXTI line 3 RTC_WKUP RTC Wakeup interrupt through the EXTI line 3 RTC_Alarm RTC Alarms (A and B) through EXTI line interrupt 41 RTC_Alarm RTC Alarms (A and B) through EXTI line interrupt 41 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 PMread-writeAMAM or 24-hour format0PMPM1 HT Hour tens in BCD format 20 2 03 HU Hour units in BCD format 16 4 015 MNT Minute tens in BCD format 12 3 07 MNU Minute units in BCD format 8 4 015 ST Second tens in BCD format 4 3 07 SU Second units in BCD format 0 4 015 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 015 YU Year units in BCD format 16 4 015 WDU Week day units 13 3 17 MT Month tens in BCD format 12 1 01 MU Month units in BCD format 8 4 015 DT Date tens in BCD format 4 2 03 DU Date units in BCD format 0 4 015 CR CR control register 0x8 0x20 read-write 0x00000000 COE Calibration output enable 23 1 COEread-writeDisabledCalibration output disabled0EnabledCalibration output enabled1 OSEL Output selection 21 2 OSELread-writeDisabledOutput disabled0AlarmAAlarm A output enabled1AlarmBAlarm B output enabled2WakeupWakeup output enabled3 POL Output polarity 20 1 POLread-writeHighThe pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])0LowThe pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])1 BKP Backup 18 1 BKPread-writeDST_Not_ChangedDaylight Saving Time change has not been performed0DST_ChangedDaylight Saving Time change has been performed1 SUB1H Subtract 1 hour (winter time change) 17 1 SUB1HWwriteSub1Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode1 ADD1H Add 1 hour (summer time change) 16 1 ADD1HWwriteAdd1Adds 1 hour to the current time. This can be used for summer time change outside initialization mode1 TSIE Time-stamp interrupt enable 15 1 TSIEread-writeDisabledTime-stamp Interrupt disabled0EnabledTime-stamp Interrupt enabled1 WUTIE Wakeup timer interrupt enable 14 1 WUTIEread-writeDisabledWakeup timer interrupt disabled0EnabledWakeup timer interrupt enabled1 ALRBIE Alarm B interrupt enable 13 1 ALRBIEread-writeDisabledAlarm B Interrupt disabled0EnabledAlarm B Interrupt enabled1 ALRAIE Alarm A interrupt enable 12 1 ALRAIEread-writeDisabledAlarm A interrupt disabled0EnabledAlarm A interrupt enabled1 TSE Time stamp enable 11 1 TSEread-writeDisabledTimestamp disabled0EnabledTimestamp enabled1 WUTE Wakeup timer enable 10 1 WUTEread-writeDisabledWakeup timer disabled0EnabledWakeup timer enabled1 ALRBE Alarm B enable 9 1 ALRBEread-writeDisabledAlarm B disabled0EnabledAlarm B enabled1 ALRAE Alarm A enable 8 1 ALRAEread-writeDisabledAlarm A disabled0EnabledAlarm A enabled1 DCE Coarse digital calibration enable 7 1 FMT Hour format 6 1 FMTread-writeTwenty_Four_Hour24 hour/day format0AM_PMAM/PM hour format1 REFCKON Reference clock detection enable (50 or 60 Hz) 4 1 REFCKONread-writeDisabledRTC_REFIN detection disabled0EnabledRTC_REFIN detection enabled1 TSEDGE Time-stamp event active edge 3 1 TSEDGEread-writeRisingEdgeRTC_TS input rising edge generates a time-stamp event0FallingEdgeRTC_TS input falling edge generates a time-stamp event1 WUCKSEL Wakeup clock selection 0 3 WUCKSELread-writeDiv16RTC/16 clock is selected0Div8RTC/8 clock is selected1Div4RTC/4 clock is selected2Div2RTC/2 clock is selected3ClockSpareck_spre (usually 1 Hz) clock is selected4ClockSpareWithOffsetck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value6 BYPSHADBypass the shadow registers51read-writeBYPSHADread-writeShadowRegCalendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles0BypassShadowRegCalendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters1 COSELCalibration output selection191read-writeCOSELread-writeCalFreq_512HzCalibration output is 512 Hz (with default prescaler setting)0CalFreq_1HzCalibration output is 1 Hz (with default prescaler setting)1 ISR ISR initialization and status register 0xC 0x20 0x00000007 ALRAWF Alarm A write flag 0 1 read-only ALRAWFRreadUpdateNotAllowedAlarm update not allowed0UpdateAllowedAlarm update allowed1 ALRBWF Alarm B write flag 1 1 read-only WUTWF Wakeup timer write flag 2 1 read-only WUTWFRreadUpdateNotAllowedWakeup timer configuration update not allowed0UpdateAllowedWakeup timer configuration update allowed1 SHPF Shift operation pending 3 1 read-write SHPFRreadNoShiftPendingNo shift operation is pending0ShiftPendingA shift operation is pending1 INITS Initialization status flag 4 1 read-only INITSRreadNotInitalizedCalendar has not been initialized0InitalizedCalendar has been initialized1 RSF Registers synchronization flag 5 1 read-write RSFRreadNotSyncedCalendar shadow registers not yet synchronized0SyncedCalendar shadow registers synchronized1 RSFWwriteClearThis flag is cleared by software by writing 00 INITF Initialization flag 6 1 read-only INITFRreadNotAllowedCalendar registers update is not allowed0AllowedCalendar registers update is allowed1 INIT Initialization mode 7 1 read-write INITread-writeFreeRunningModeFree running mode0InitModeInitialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.1 ALRAF Alarm A flag 8 1 read-write ALRAFRreadMatchThis flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)1 ALRAFWwriteClearThis flag is cleared by software by writing 00 ALRBF Alarm B flag 9 1 read-write ALRBFRreadMatchThis flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)1 ALRBFWwriteClearThis flag is cleared by software by writing 00 WUTF Wakeup timer flag 10 1 read-write WUTFRreadZeroThis flag is set by hardware when the wakeup auto-reload counter reaches 01 WUTFWwriteClearThis flag is cleared by software by writing 00 TSF Time-stamp flag 11 1 read-write TSFRreadTimestampEventThis flag is set by hardware when a time-stamp event occurs1 TSFWwriteClearThis flag is cleared by software by writing 00 TSOVF Time-stamp overflow flag 12 1 read-write TSOVFRreadOverflowThis flag is set by hardware when a time-stamp event occurs while TSF is already set1 TSOVFWwriteClearThis flag is cleared by software by writing 00 TAMP1F Tamper detection flag 13 1 read-write TAMP1FRreadTamperedThis flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input1 TAMP1FWwriteClearFlag cleared by software writing 00 TAMP2F TAMPER2 detection flag 14 1 read-write RECALPF Recalibration pending Flag 16 1 read-only RECALPFRreadPendingThe RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 01 PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 0127 PREDIV_S Synchronous prescaler factor 0 15 032767 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 065535 CALIBR CALIBR calibration register 0x18 0x20 read-write 0x00000000 DCS Digital calibration sign 7 1 DC Digital calibration 0 5 ALRMAR ALRMAR alarm A register 0x1C 0x20 read-write 0x00000000 MSK4 Alarm A date mask 31 1 WDSEL Week day selection 30 1 WDSELread-writeDateUnitsDU[3:0] represents the date units0WeekDayDU[3:0] represents the week day. DT[1:0] is don’t care.1 DT Date tens in BCD format 28 2 03 DU Date units or day in BCD format 24 4 015 MSK3 Alarm A hours mask 23 1 PM AM/PM notation 22 1 PMread-writeAMAM or 24-hour format0PMPM1 HT Hour tens in BCD format 20 2 03 HU Hour units in BCD format 16 4 015 MSK2 Alarm A minutes mask 15 1 MNT Minute tens in BCD format 12 3 07 MNU Minute units in BCD format 8 4 015 MSK1 Alarm A seconds mask 7 1 MSK1read-writeMaskAlarm set if the date/day match0NotMaskDate/day don’t care in Alarm comparison1 ST Second tens in BCD format 4 3 07 SU Second units in BCD format 0 4 015 ALRMBR ALRMBR alarm B register 0x20 0x20 read-write 0x00000000 MSK4 Alarm B date mask 31 1 WDSEL Week day selection 30 1 WDSELread-writeDateUnitsDU[3:0] represents the date units0WeekDayDU[3:0] represents the week day. DT[1:0] is don’t care.1 DT Date tens in BCD format 28 2 03 DU Date units or day in BCD format 24 4 015 MSK3 Alarm B hours mask 23 1 PM AM/PM notation 22 1 PMread-writeAMAM or 24-hour format0PMPM1 HT Hour tens in BCD format 20 2 03 HU Hour units in BCD format 16 4 015 MSK2 Alarm B minutes mask 15 1 MNT Minute tens in BCD format 12 3 07 MNU Minute units in BCD format 8 4 015 MSK1 Alarm B seconds mask 7 1 MSK1read-writeMaskAlarm set if the date/day match0NotMaskDate/day don’t care in Alarm comparison1 ST Second tens in BCD format 4 3 07 SU Second units in BCD format 0 4 015 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 0255 SSR SSR sub second register 0x28 0x20 read-only 0x00000000 SS Sub second value 0 16 065535 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 ADD1SWwriteAdd1Add one second to the clock/calendar1 SUBFS Subtract a fraction of a second 0 15 032767 TSTR TSTR time stamp time register 0x30 0x20 read-only 0x00000000 ALARMOUTTYPE AFO_ALARM output type 18 1 TSINSEL TIMESTAMP mapping 17 1 TAMP1INSEL TAMPER1 mapping 16 1 TAMPIE Tamper interrupt enable 2 1 TAMP1TRG Active level for tamper 1 1 1 TAMP1E Tamper 1 detection enable 0 1 TSDR TSDR time stamp date register 0x34 0x20 read-only 0x00000000 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 TSSSR TSSSR timestamp sub second register 0x38 0x20 read-only 0x00000000 SS Sub second value 0 16 CALR CALR calibration register 0x3C 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALPread-writeNoChangeNo RTCCLK pulses are added0IncreaseFreqOne RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)1 CALW8 Use an 8-second calibration cycle period 14 1 CALW8read-writeEight_SecondWhen CALW8 is set to ‘1’, the 8-second calibration cycle period is selected1 CALW16 Use a 16-second calibration cycle period 13 1 CALW16read-writeSixteen_SecondWhen CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=11 CALM Calibration minus 0 9 0511 TAFCR TAFCR tamper and alternate function configuration register 0x40 0x20 read-write 0x00000000 ALARMOUTTYPE AFO_ALARM output type 18 1 TSINSEL TIMESTAMP mapping 17 1 TAMP1INSEL TAMPER1 mapping 16 1 TAMPPUDIS TAMPER pull-up disable 15 1 TAMPPRCH Tamper precharge duration 13 2 TAMPFLT Tamper filter count 11 2 TAMPFREQ Tamper sampling frequency 8 3 TAMPTS Activate timestamp on tamper detection event 7 1 TAMP2TRG Active level for tamper 2 4 1 TAMP2E Tamper 2 detection enable 3 1 TAMPIE Tamper interrupt enable 2 1 TAMP1TRG Active level for tamper 1 1 1 TAMP1E Tamper 1 detection enable 0 1 ALRMASSR ALRMASSR alarm A sub second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 015 SS Sub seconds value 0 15 032767 ALRMBSSR ALRMBSSR alarm B sub second register 0x48 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 015 SS Sub seconds value 0 15 032767 200x40,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19BKP%sR BKP0R backup register 0x50 0x20 read-write 0x00000000 BKP BKP 0 32 04294967295 UART4 Universal synchronous asynchronous receiver transmitter USART 0x40004C00 0x0 0x400 registers UART4 UART4 global interrupt 52 UART4 UART4 global interrupt 52 SR SR Status register 0x0 0x20 0x00C00000 LBD LIN break detection flag 8 1 read-write TXE Transmit data register empty 7 1 read-only TC Transmission complete 6 1 read-write RXNE Read data register not empty 5 1 read-write IDLE IDLE line detected 4 1 read-only ORE Overrun error 3 1 read-only NF Noise detected flag 2 1 read-only FE Framing error 1 1 read-only PE Parity error 0 1 read-only DR DR Data register 0x4 0x20 read-write 0x00000000 DR Data value 0 9 0511 BRR BRR Baud rate register 0x8 0x20 read-write 0x0000 DIV_Mantissa mantissa of USARTDIV 4 12 04095 DIV_Fraction fraction of USARTDIV 0 4 015 CR1 CR1 Control register 1 0xC 0x20 read-write 0x0000 OVER8 Oversampling mode 15 1 OVER8read-writeOversample16Oversampling by 160Oversample8Oversampling by 81 UE USART enable 13 1 UEread-writeDisabledUSART prescaler and outputs disabled0EnabledUSART enabled1 M Word length 12 1 Mread-writeM88 data bits0M99 data bits1 WAKE Wakeup method 11 1 WAKEread-writeIdleLineUSART wakeup on idle line0AddressMarkUSART wakeup on address mark1 PCE Parity control enable 10 1 PCEread-writeDisabledParity control disabled0EnabledParity control enabled1 PS Parity selection 9 1 PSread-writeEvenEven parity0OddOdd parity1 PEIE PE interrupt enable 8 1 PEIEread-writeDisabledPE interrupt disabled0EnabledPE interrupt enabled1 TXEIE TXE interrupt enable 7 1 TXEIEread-writeDisabledTXE interrupt disabled0EnabledTXE interrupt enabled1 TCIE Transmission complete interrupt enable 6 1 TCIEread-writeDisabledTC interrupt disabled0EnabledTC interrupt enabled1 RXNEIE RXNE interrupt enable 5 1 RXNEIEread-writeDisabledRXNE interrupt disabled0EnabledRXNE interrupt enabled1 IDLEIE IDLE interrupt enable 4 1 IDLEIEread-writeDisabledIDLE interrupt disabled0EnabledIDLE interrupt enabled1 TE Transmitter enable 3 1 TEread-writeDisabledTransmitter disabled0EnabledTransmitter enabled1 RE Receiver enable 2 1 REread-writeDisabledReceiver disabled0EnabledReceiver enabled1 RWU Receiver wakeup 1 1 RWUread-writeActiveReceiver in active mode0MuteReceiver in mute mode1 SBK Send break 0 1 SBKread-writeNoBreakNo break character is transmitted0BreakBreak character transmitted1 CR2 CR2 Control register 2 0x10 0x20 read-write 0x0000 LINEN LIN mode enable 14 1 LINENread-writeDisabledLIN mode disabled0EnabledLIN mode enabled1 STOP STOP bits 12 2 STOPread-writeStop11 stop bit0Stop22 stop bits2 LBDIE LIN break detection interrupt enable 6 1 LBDIEread-writeDisabledLIN break detection interrupt disabled0EnabledLIN break detection interrupt enabled1 LBDL lin break detection length 5 1 LBDLread-writeLBDL1010-bit break detection0LBDL1111-bit break detection1 ADD Address of the USART node 0 4 015 CR3 CR3 Control register 3 0x14 0x20 read-write 0x0000 ONEBIT One sample bit method enable 11 1 ONEBITread-writeSample3Three sample bit method0Sample1One sample bit method1 DMAT DMA enable transmitter 7 1 DMATread-writeDisabledDMA mode is disabled for transmission0EnabledDMA mode is enabled for transmission1 DMAR DMA enable receiver 6 1 DMARread-writeDisabledDMA mode is disabled for reception0EnabledDMA mode is enabled for reception1 HDSEL Half-duplex selection 3 1 HDSELread-writeFullDuplexHalf duplex mode is not selected0HalfDuplexHalf duplex mode is selected1 IRLP IrDA low-power 2 1 IRLPread-writeNormalNormal mode0LowPowerLow-power mode1 IREN IrDA mode enable 1 1 IRENread-writeDisabledIrDA disabled0EnabledIrDA enabled1 EIE Error interrupt enable 0 1 EIEread-writeDisabledError interrupt disabled0EnabledError interrupt enabled1 UART5 0x40005000 UART5 UART5 global interrupt 53 UART5 UART5 global interrupt 53 ADC_Common Common ADC registers ADC 0x40012300 0x0 0xD registers CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 OVR3 Overrun flag of ADC3 21 1 STRT3 Regular channel Start flag of ADC 3 20 1 JSTRT3 Injected channel Start flag of ADC 3 19 1 JEOC3 Injected channel end of conversion of ADC 3 18 1 EOC3 End of conversion of ADC 3 17 1 AWD3 Analog watchdog flag of ADC 3 16 1 OVR2 Overrun flag of ADC 2 13 1 STRT2 Regular channel Start flag of ADC 2 12 1 JSTRT2 Injected channel Start flag of ADC 2 11 1 JEOC2 Injected channel end of conversion of ADC 2 10 1 EOC2 End of conversion of ADC 2 9 1 AWD2 Analog watchdog flag of ADC 2 8 1 OVR1 Overrun flag of ADC 1 5 1 OVR1read-writeNoOverrunNo overrun occurred0OverrunOverrun occurred1 STRT1 Regular channel Start flag of ADC 1 4 1 STRT1read-writeNotStartedNo regular channel conversion started0StartedRegular channel conversion has started1 JSTRT1 Injected channel Start flag of ADC 1 3 1 JSTRT1read-writeNotStartedNo injected channel conversion started0StartedInjected channel conversion has started1 JEOC1 Injected channel end of conversion of ADC 1 2 1 JEOC1read-writeNotCompleteConversion is not complete0CompleteConversion complete1 EOC1 End of conversion of ADC 1 1 1 EOC1read-writeNotCompleteConversion is not complete0CompleteConversion complete1 AWD1 Analog watchdog flag of ADC 1 0 1 AWD1read-writeNoEventNo analog watchdog event occurred0EventAnalog watchdog event occurred1 CCR CCR ADC common control register 0x4 0x20 read-write 0x00000000 TSVREFE Temperature sensor and VREFINT enable 23 1 TSVREFEread-writeDisabledTemperature sensor and V_REFINT channel disabled0EnabledTemperature sensor and V_REFINT channel enabled1 VBATE VBAT enable 22 1 VBATEread-writeDisabledV_BAT channel disabled0EnabledV_BAT channel enabled1 ADCPRE ADC prescaler 16 2 ADCPREread-writeDiv2PCLK2 divided by 20Div4PCLK2 divided by 41Div6PCLK2 divided by 62Div8PCLK2 divided by 83 DMA Direct memory access mode for multi ADC mode 14 2 DMAread-writeDisabledDMA mode disabled0Mode1DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)1Mode2DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)2Mode3DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)3 DDS DMA disable selection for multi-ADC mode 13 1 DDSread-writeSingleNo new DMA request is issued after the last transfer0ContinuousDMA requests are issued as long as data are converted and DMA=01, 10 or 111 DELAY Delay between 2 sampling phases 8 4 015 MULTI Multi ADC mode selection 0 5 MULTIread-writeIndependentAll the ADCs independent: independent mode0DualRJDual ADC1 and ADC2, combined regular and injected simultaneous mode1DualRADual ADC1 and ADC2, combined regular and alternate trigger mode2DualJDual ADC1 and ADC2, injected simultaneous mode only5DualRDual ADC1 and ADC2, regular simultaneous mode only6DualIDual ADC1 and ADC2, interleaved mode only7DualADual ADC1 and ADC2, alternate trigger mode only9TripleRJTriple ADC, regular and injected simultaneous mode17TripleRATriple ADC, regular and alternate trigger mode18TripleJTriple ADC, injected simultaneous mode only21TripleRTriple ADC, regular simultaneous mode only22TripleITriple ADC, interleaved mode only23TripleATriple ADC, alternate trigger mode only24 CDR CDR ADC common regular data register for dual and triple modes 0x8 0x20 read-only 0x00000000 DATA2 2nd data item of a pair of regular conversions 16 16 DATA1 1st data item of a pair of regular conversions 0 16 TIM1 Advanced-timers TIM 0x40010000 0x0 0x400 registers TIM1_BRK_TIM9 TIM1 Break interrupt and TIM9 global interrupt 24 TIM1_BRK_TIM9 TIM1 Break interrupt and TIM9 global interrupt 24 TIM1_UP_TIM10 TIM1 Update interrupt and TIM10 global interrupt 25 TIM1_UP_TIM10 TIM1 Update interrupt and TIM10 global interrupt 25 TIM1_TRG_COM_TIM11 TIM1 Trigger and Commutation interrupts and TIM11 global interrupt 26 TIM1_TRG_COM_TIM11 TIM1 Trigger and Commutation interrupts and TIM11 global interrupt 26 TIM1_CC TIM1 Capture Compare interrupt 27 TIM1_CC TIM1 Capture Compare interrupt 27 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 CKDread-writeDiv1t_DTS = t_CK_INT0Div2t_DTS = 2 × t_CK_INT1Div4t_DTS = 4 × t_CK_INT2 ARPE Auto-reload preload enable 7 1 ARPEread-writeDisabledTIMx_APRR register is not buffered0EnabledTIMx_APRR register is buffered1 CMS Center-aligned mode selection 5 2 CMSread-writeEdgeAlignedThe counter counts up or down depending on the direction bit0CenterAligned1The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.1CenterAligned2The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.2CenterAligned3The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.3 DIR Direction 4 1 DIRread-writeUpCounter used as upcounter0DownCounter used as downcounter1 OPM One-pulse mode 3 1 OPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 URS Update request source 2 1 URSread-writeAnyEventAny of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request0CounterOnlyOnly counter overflow/underflow generates an update interrupt or DMA request1 UDIS Update disable 1 1 UDISread-writeEnabledUpdate event enabled0DisabledUpdate event disabled1 CEN Counter enable 0 1 CENread-writeDisabledCounter disabled0EnabledCounter enabled1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 TI1Sread-writeNormalThe TIMx_CH1 pin is connected to TI1 input0XORThe TIMx_CH1, CH2, CH3 pins are connected to TI1 input1 MMS Master mode selection 4 3 MMSread-writeResetThe UG bit from the TIMx_EGR register is used as trigger output0EnableThe counter enable signal, CNT_EN, is used as trigger output1UpdateThe update event is selected as trigger output2ComparePulseThe trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred3CompareOC1OC1REF signal is used as trigger output4CompareOC2OC2REF signal is used as trigger output5CompareOC3OC3REF signal is used as trigger output6CompareOC4OC4REF signal is used as trigger output7 CCDS Capture/compare DMA selection 3 1 CCDSread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ETPread-writeNotInvertedETR is noninverted, active at high level or rising edge0InvertedETR is inverted, active at low level or falling edge1 ECE External clock enable 14 1 ECEread-writeDisabledExternal clock mode 2 disabled0EnabledExternal clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.1 ETPS External trigger prescaler 12 2 ETPSread-writeDiv1Prescaler OFF0Div2ETRP frequency divided by 21Div4ETRP frequency divided by 42Div8ETRP frequency divided by 83 ETF External trigger filter 8 4 ETFread-writeNoFilterNo filter, sampling is done at fDTS0FCK_INT_N2fSAMPLING=fCK_INT, N=21FCK_INT_N4fSAMPLING=fCK_INT, N=42FCK_INT_N8fSAMPLING=fCK_INT, N=83FDTS_Div2_N6fSAMPLING=fDTS/2, N=64FDTS_Div2_N8fSAMPLING=fDTS/2, N=85FDTS_Div4_N6fSAMPLING=fDTS/4, N=66FDTS_Div4_N8fSAMPLING=fDTS/4, N=87FDTS_Div8_N6fSAMPLING=fDTS/8, N=68FDTS_Div8_N8fSAMPLING=fDTS/8, N=89FDTS_Div16_N5fSAMPLING=fDTS/16, N=510FDTS_Div16_N6fSAMPLING=fDTS/16, N=611FDTS_Div16_N8fSAMPLING=fDTS/16, N=812FDTS_Div32_N5fSAMPLING=fDTS/32, N=513FDTS_Div32_N6fSAMPLING=fDTS/32, N=614FDTS_Div32_N8fSAMPLING=fDTS/32, N=815 MSM Master/Slave mode 7 1 MSMread-writeNoSyncNo action0SyncThe effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.1 TS Trigger selection 4 3 TSread-writeITR0Internal Trigger 0 (ITR0)0ITR1Internal Trigger 1 (ITR1)1ITR2Internal Trigger 2 (ITR2)2TI1F_EDTI1 Edge Detector (TI1F_ED)4TI1FP1Filtered Timer Input 1 (TI1FP1)5TI2FP2Filtered Timer Input 2 (TI2FP2)6ETRFExternal Trigger input (ETRF)7 SMS Slave mode selection 0 3 SMSread-writeDisabledSlave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.0Encoder_Mode_1Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.1Encoder_Mode_2Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.2Encoder_Mode_3Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.3Reset_ModeReset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.4Gated_ModeGated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.5Trigger_ModeTrigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.6Ext_Clock_ModeExternal Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.7 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 TDEread-writeDisabledTrigger DMA request disabled0EnabledTrigger DMA request enabled1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1DEread-writeDisabledCCx DMA request disabled0EnabledCCx DMA request enabled1 UDE Update DMA request enable 8 1 UDEread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 TIE Trigger interrupt enable 6 1 TIEread-writeDisabledTrigger interrupt disabled0EnabledTrigger interrupt enabled1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC1IEread-writeDisabledCCx interrupt disabled0EnabledCCx interrupt enabled1 UIE Update interrupt enable 0 1 UIEread-writeDisabledUpdate interrupt disabled0EnabledUpdate interrupt enabled1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC1OFRreadOvercaptureThe counter value has been captured in TIMx_CCRx register while CCxIF flag was already set1 CC1OFWwriteClearClear flag0 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 TIFRreadNoTriggerNo trigger event occurred0TriggerTrigger interrupt pending1 TIFWwriteClearClear flag0 COMIF COM interrupt flag 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1IFRreadMatchIf CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.1 CC1IFWwriteClearClear flag0 UIF Update interrupt flag 0 1 UIFread-writeClearNo update occurred0UpdatePendingUpdate interrupt pending.1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 TGWwriteTriggerThe TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 CC1GWwriteTriggerIf CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.1 UG Update generation 0 1 UGread-writeUpdateRe-initializes the timer counter and generates an update of the registers.1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE Output Compare 2 clear enable 15 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2PEread-writeDisabledPreload register on CCR2 disabled. New values written to CCR2 are taken into account immediately0EnabledPreload register on CCR2 enabled. Preload value is loaded into active register on each update event1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 CC2Sread-writeOutputCC2 channel is configured as output0 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1Mread-writeFrozenThe comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register1InactiveOnMatchSet channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register2ToggleOCyREF toggles when TIMx_CNT=TIMx_CCRy3ForceInactiveOCyREF is forced low4ForceActiveOCyREF is forced high5PwmMode1In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active6PwmMode2Inversely to PwmMode17 OC1PE Output Compare 1 preload enable 3 1 OC1PEread-writeDisabledPreload register on CCR1 disabled. New values written to CCR1 are taken into account immediately0EnabledPreload register on CCR1 enabled. Preload value is loaded into active register on each update event1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CC1Sread-writeOutputCC1 channel is configured as output0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 015 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 CC2Sread-writeTI2CC2 channel is configured as input, IC2 is mapped on TI21TI1CC2 channel is configured as input, IC2 is mapped on TI12TRCCC2 channel is configured as input, IC2 is mapped on TRC3 IC1F Input capture 1 filter 4 4 IC1Fread-writeNoFilterNo filter, sampling is done at fDTS0FCK_INT_N2fSAMPLING=fCK_INT, N=21FCK_INT_N4fSAMPLING=fCK_INT, N=42FCK_INT_N8fSAMPLING=fCK_INT, N=83FDTS_Div2_N6fSAMPLING=fDTS/2, N=64FDTS_Div2_N8fSAMPLING=fDTS/2, N=85FDTS_Div4_N6fSAMPLING=fDTS/4, N=66FDTS_Div4_N8fSAMPLING=fDTS/4, N=87FDTS_Div8_N6fSAMPLING=fDTS/8, N=68FDTS_Div8_N8fSAMPLING=fDTS/8, N=89FDTS_Div16_N5fSAMPLING=fDTS/16, N=510FDTS_Div16_N6fSAMPLING=fDTS/16, N=611FDTS_Div16_N8fSAMPLING=fDTS/16, N=812FDTS_Div32_N5fSAMPLING=fDTS/32, N=513FDTS_Div32_N6fSAMPLING=fDTS/32, N=614FDTS_Div32_N8fSAMPLING=fDTS/32, N=815 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CC1Sread-writeTI1CC1 channel is configured as input, IC1 is mapped on TI11TI2CC1 channel is configured as input, IC1 is mapped on TI22TRCCC1 channel is configured as input, IC1 is mapped on TRC3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4PEread-writeDisabledPreload register on CCR4 disabled. New values written to CCR4 are taken into account immediately0EnabledPreload register on CCR4 enabled. Preload value is loaded into active register on each update event1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 CC4Sread-writeOutputCC4 channel is configured as output0 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3Mread-writeFrozenThe comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register1InactiveOnMatchSet channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register2ToggleOCyREF toggles when TIMx_CNT=TIMx_CCRy3ForceInactiveOCyREF is forced low4ForceActiveOCyREF is forced high5PwmMode1In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active6PwmMode2Inversely to PwmMode17 OC3PE Output compare 3 preload enable 3 1 OC3PEread-writeDisabledPreload register on CCR3 disabled. New values written to CCR3 are taken into account immediately0EnabledPreload register on CCR3 enabled. Preload value is loaded into active register on each update event1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CC3Sread-writeOutputCC3 channel is configured as output0 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 015 IC4PSC Input capture 4 prescaler 10 2 03 CC4S Capture/Compare 4 selection 8 2 CC4Sread-writeTI4CC4 channel is configured as input, IC4 is mapped on TI41TI3CC4 channel is configured as input, IC4 is mapped on TI32TRCCC4 channel is configured as input, IC4 is mapped on TRC3 IC3F Input capture 3 filter 4 4 015 IC3PSC Input capture 3 prescaler 2 2 03 CC3S Capture/compare 3 selection 0 2 CC3Sread-writeTI3CC3 channel is configured as input, IC3 is mapped on TI31TI4CC3 channel is configured as input, IC3 is mapped on TI42TRCCC3 channel is configured as input, IC3 is mapped on TRC3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 065535 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 065535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 065535 40x41,2,3,4CCR%s CCR1 capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 065535 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 018 DBA DMA base address 0 5 031 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 MOE Main output enable 15 1 MOEread-writeDisabledIdleOC/OCN are disabled or forced idle depending on OSSI0EnabledOC/OCN are enabled if CCxE/CCxNE are set1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSRread-writeDisabledWhen inactive, OC/OCN outputs are disabled0IdleLevelWhen inactive, OC/OCN outputs are enabled with their inactive level1 OSSI Off-state selection for Idle mode 10 1 OSSIread-writeDisabledWhen inactive, OC/OCN outputs are disabled0IdleLevelWhen inactive, OC/OCN outputs are forced to idle level1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 TIM8 0x40010400 TIM8_BRK_TIM12 TIM8 Break interrupt and TIM12 global interrupt 43 TIM8_BRK_TIM12 TIM8 Break interrupt and TIM12 global interrupt 43 TIM8_CC TIM8 Capture Compare interrupt 46 TIM8_CC TIM8 Capture Compare interrupt 46 TIM2 General purpose timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 28 TIM2 TIM2 global interrupt 28 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 CKDread-writeDiv1t_DTS = t_CK_INT0Div2t_DTS = 2 × t_CK_INT1Div4t_DTS = 4 × t_CK_INT2 ARPE Auto-reload preload enable 7 1 ARPEread-writeDisabledTIMx_APRR register is not buffered0EnabledTIMx_APRR register is buffered1 CMS Center-aligned mode selection 5 2 CMSread-writeEdgeAlignedThe counter counts up or down depending on the direction bit0CenterAligned1The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.1CenterAligned2The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.2CenterAligned3The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.3 DIR Direction 4 1 DIRread-writeUpCounter used as upcounter0DownCounter used as downcounter1 OPM One-pulse mode 3 1 OPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 URS Update request source 2 1 URSread-writeAnyEventAny of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request0CounterOnlyOnly counter overflow/underflow generates an update interrupt or DMA request1 UDIS Update disable 1 1 UDISread-writeEnabledUpdate event enabled0DisabledUpdate event disabled1 CEN Counter enable 0 1 CENread-writeDisabledCounter disabled0EnabledCounter enabled1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 TI1Sread-writeNormalThe TIMx_CH1 pin is connected to TI1 input0XORThe TIMx_CH1, CH2, CH3 pins are connected to TI1 input1 MMS Master mode selection 4 3 MMSread-writeResetThe UG bit from the TIMx_EGR register is used as trigger output0EnableThe counter enable signal, CNT_EN, is used as trigger output1UpdateThe update event is selected as trigger output2ComparePulseThe trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred3CompareOC1OC1REF signal is used as trigger output4CompareOC2OC2REF signal is used as trigger output5CompareOC3OC3REF signal is used as trigger output6CompareOC4OC4REF signal is used as trigger output7 CCDS Capture/compare DMA selection 3 1 CCDSread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ETPread-writeNotInvertedETR is noninverted, active at high level or rising edge0InvertedETR is inverted, active at low level or falling edge1 ECE External clock enable 14 1 ECEread-writeDisabledExternal clock mode 2 disabled0EnabledExternal clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.1 ETPS External trigger prescaler 12 2 ETPSread-writeDiv1Prescaler OFF0Div2ETRP frequency divided by 21Div4ETRP frequency divided by 42Div8ETRP frequency divided by 83 ETF External trigger filter 8 4 ETFread-writeNoFilterNo filter, sampling is done at fDTS0FCK_INT_N2fSAMPLING=fCK_INT, N=21FCK_INT_N4fSAMPLING=fCK_INT, N=42FCK_INT_N8fSAMPLING=fCK_INT, N=83FDTS_Div2_N6fSAMPLING=fDTS/2, N=64FDTS_Div2_N8fSAMPLING=fDTS/2, N=85FDTS_Div4_N6fSAMPLING=fDTS/4, N=66FDTS_Div4_N8fSAMPLING=fDTS/4, N=87FDTS_Div8_N6fSAMPLING=fDTS/8, N=68FDTS_Div8_N8fSAMPLING=fDTS/8, N=89FDTS_Div16_N5fSAMPLING=fDTS/16, N=510FDTS_Div16_N6fSAMPLING=fDTS/16, N=611FDTS_Div16_N8fSAMPLING=fDTS/16, N=812FDTS_Div32_N5fSAMPLING=fDTS/32, N=513FDTS_Div32_N6fSAMPLING=fDTS/32, N=614FDTS_Div32_N8fSAMPLING=fDTS/32, N=815 MSM Master/Slave mode 7 1 MSMread-writeNoSyncNo action0SyncThe effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.1 TS Trigger selection 4 3 TSread-writeITR0Internal Trigger 0 (ITR0)0ITR1Internal Trigger 1 (ITR1)1ITR2Internal Trigger 2 (ITR2)2TI1F_EDTI1 Edge Detector (TI1F_ED)4TI1FP1Filtered Timer Input 1 (TI1FP1)5TI2FP2Filtered Timer Input 2 (TI2FP2)6ETRFExternal Trigger input (ETRF)7 SMS Slave mode selection 0 3 SMSread-writeDisabledSlave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.0Encoder_Mode_1Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.1Encoder_Mode_2Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.2Encoder_Mode_3Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.3Reset_ModeReset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.4Gated_ModeGated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.5Trigger_ModeTrigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.6Ext_Clock_ModeExternal Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.7 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 TDEread-writeDisabledTrigger DMA request disabled0EnabledTrigger DMA request enabled1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1DEread-writeDisabledCCx DMA request disabled0EnabledCCx DMA request enabled1 UDE Update DMA request enable 8 1 UDEread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 TIE Trigger interrupt enable 6 1 TIEread-writeDisabledTrigger interrupt disabled0EnabledTrigger interrupt enabled1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC1IEread-writeDisabledCCx interrupt disabled0EnabledCCx interrupt enabled1 UIE Update interrupt enable 0 1 UIEread-writeDisabledUpdate interrupt disabled0EnabledUpdate interrupt enabled1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC1OFRreadOvercaptureThe counter value has been captured in TIMx_CCRx register while CCxIF flag was already set1 CC1OFWwriteClearClear flag0 TIF Trigger interrupt flag 6 1 TIFRreadNoTriggerNo trigger event occurred0TriggerTrigger interrupt pending1 TIFWwriteClearClear flag0 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1IFRreadMatchIf CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.1 CC1IFWwriteClearClear flag0 UIF Update interrupt flag 0 1 UIFread-writeClearNo update occurred0UpdatePendingUpdate interrupt pending.1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 TGWwriteTriggerThe TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 CC1GWwriteTriggerIf CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.1 UG Update generation 0 1 UGread-writeUpdateRe-initializes the timer counter and generates an update of the registers.1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE OC2CE 15 1 OC2M OC2M 12 3 OC2PE OC2PE 11 1 OC2PEread-writeDisabledPreload register on CCR2 disabled. New values written to CCR2 are taken into account immediately0EnabledPreload register on CCR2 enabled. Preload value is loaded into active register on each update event1 OC2FE OC2FE 10 1 CC2S CC2S 8 2 CC2Sread-writeOutputCC2 channel is configured as output0 OC1CE OC1CE 7 1 OC1M OC1M 4 3 OC1Mread-writeFrozenThe comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register1InactiveOnMatchSet channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register2ToggleOCyREF toggles when TIMx_CNT=TIMx_CCRy3ForceInactiveOCyREF is forced low4ForceActiveOCyREF is forced high5PwmMode1In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active6PwmMode2Inversely to PwmMode17 OC1PE OC1PE 3 1 OC1PEread-writeDisabledPreload register on CCR1 disabled. New values written to CCR1 are taken into account immediately0EnabledPreload register on CCR1 enabled. Preload value is loaded into active register on each update event1 OC1FE OC1FE 2 1 CC1S CC1S 0 2 CC1Sread-writeOutputCC1 channel is configured as output0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 015 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 CC2Sread-writeTI2CC2 channel is configured as input, IC2 is mapped on TI21TI1CC2 channel is configured as input, IC2 is mapped on TI12TRCCC2 channel is configured as input, IC2 is mapped on TRC3 IC1F Input capture 1 filter 4 4 IC1Fread-writeNoFilterNo filter, sampling is done at fDTS0FCK_INT_N2fSAMPLING=fCK_INT, N=21FCK_INT_N4fSAMPLING=fCK_INT, N=42FCK_INT_N8fSAMPLING=fCK_INT, N=83FDTS_Div2_N6fSAMPLING=fDTS/2, N=64FDTS_Div2_N8fSAMPLING=fDTS/2, N=85FDTS_Div4_N6fSAMPLING=fDTS/4, N=66FDTS_Div4_N8fSAMPLING=fDTS/4, N=87FDTS_Div8_N6fSAMPLING=fDTS/8, N=68FDTS_Div8_N8fSAMPLING=fDTS/8, N=89FDTS_Div16_N5fSAMPLING=fDTS/16, N=510FDTS_Div16_N6fSAMPLING=fDTS/16, N=611FDTS_Div16_N8fSAMPLING=fDTS/16, N=812FDTS_Div32_N5fSAMPLING=fDTS/32, N=513FDTS_Div32_N6fSAMPLING=fDTS/32, N=614FDTS_Div32_N8fSAMPLING=fDTS/32, N=815 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CC1Sread-writeTI1CC1 channel is configured as input, IC1 is mapped on TI11TI2CC1 channel is configured as input, IC1 is mapped on TI22TRCCC1 channel is configured as input, IC1 is mapped on TRC3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE O24CE 15 1 OC4M OC4M 12 3 OC4PE OC4PE 11 1 OC4PEread-writeDisabledPreload register on CCR4 disabled. New values written to CCR4 are taken into account immediately0EnabledPreload register on CCR4 enabled. Preload value is loaded into active register on each update event1 OC4FE OC4FE 10 1 CC4S CC4S 8 2 CC4Sread-writeOutputCC4 channel is configured as output0 OC3CE OC3CE 7 1 OC3M OC3M 4 3 OC3Mread-writeFrozenThe comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register1InactiveOnMatchSet channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register2ToggleOCyREF toggles when TIMx_CNT=TIMx_CCRy3ForceInactiveOCyREF is forced low4ForceActiveOCyREF is forced high5PwmMode1In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active6PwmMode2Inversely to PwmMode17 OC3PE OC3PE 3 1 OC3PEread-writeDisabledPreload register on CCR3 disabled. New values written to CCR3 are taken into account immediately0EnabledPreload register on CCR3 enabled. Preload value is loaded into active register on each update event1 OC3FE OC3FE 2 1 CC3S CC3S 0 2 CC3Sread-writeOutputCC3 channel is configured as output0 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 015 IC4PSC Input capture 4 prescaler 10 2 03 CC4S Capture/Compare 4 selection 8 2 CC4Sread-writeTI4CC4 channel is configured as input, IC4 is mapped on TI41TI3CC4 channel is configured as input, IC4 is mapped on TI32TRCCC4 channel is configured as input, IC4 is mapped on TRC3 IC3F Input capture 3 filter 4 4 015 IC3PSC Input capture 3 prescaler 2 2 03 CC3S Capture/compare 3 selection 0 2 CC3Sread-writeTI3CC3 channel is configured as input, IC3 is mapped on TI31TI4CC3 channel is configured as input, IC3 is mapped on TI42TRCCC3 channel is configured as input, IC3 is mapped on TRC3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNTCounter value03204294967295 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 065535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARRAuto-reload value03204294967295 40x41,2,3,4CCR%s CCR1 capture/compare register 0x34 0x20 read-write 0x00000000 CCRCapture/Compare value03204294967295 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 018 DBA DMA base address 0 5 031 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 OR OR TIM5 option register 0x50 0x20 read-write 0x0000 ITR1_RMP Timer Input 4 remap 10 2 TIM3 General purpose timers TIM 0x40000400 0x0 0x400 registers TIM3 TIM3 global interrupt 29 TIM3 TIM3 global interrupt 29 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 CKDread-writeDiv1t_DTS = t_CK_INT0Div2t_DTS = 2 × t_CK_INT1Div4t_DTS = 4 × t_CK_INT2 ARPE Auto-reload preload enable 7 1 ARPEread-writeDisabledTIMx_APRR register is not buffered0EnabledTIMx_APRR register is buffered1 CMS Center-aligned mode selection 5 2 CMSread-writeEdgeAlignedThe counter counts up or down depending on the direction bit0CenterAligned1The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.1CenterAligned2The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.2CenterAligned3The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.3 DIR Direction 4 1 DIRread-writeUpCounter used as upcounter0DownCounter used as downcounter1 OPM One-pulse mode 3 1 OPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 URS Update request source 2 1 URSread-writeAnyEventAny of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request0CounterOnlyOnly counter overflow/underflow generates an update interrupt or DMA request1 UDIS Update disable 1 1 UDISread-writeEnabledUpdate event enabled0DisabledUpdate event disabled1 CEN Counter enable 0 1 CENread-writeDisabledCounter disabled0EnabledCounter enabled1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 TI1Sread-writeNormalThe TIMx_CH1 pin is connected to TI1 input0XORThe TIMx_CH1, CH2, CH3 pins are connected to TI1 input1 MMS Master mode selection 4 3 MMSread-writeResetThe UG bit from the TIMx_EGR register is used as trigger output0EnableThe counter enable signal, CNT_EN, is used as trigger output1UpdateThe update event is selected as trigger output2ComparePulseThe trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred3CompareOC1OC1REF signal is used as trigger output4CompareOC2OC2REF signal is used as trigger output5CompareOC3OC3REF signal is used as trigger output6CompareOC4OC4REF signal is used as trigger output7 CCDS Capture/compare DMA selection 3 1 CCDSread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ETPread-writeNotInvertedETR is noninverted, active at high level or rising edge0InvertedETR is inverted, active at low level or falling edge1 ECE External clock enable 14 1 ECEread-writeDisabledExternal clock mode 2 disabled0EnabledExternal clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.1 ETPS External trigger prescaler 12 2 ETPSread-writeDiv1Prescaler OFF0Div2ETRP frequency divided by 21Div4ETRP frequency divided by 42Div8ETRP frequency divided by 83 ETF External trigger filter 8 4 ETFread-writeNoFilterNo filter, sampling is done at fDTS0FCK_INT_N2fSAMPLING=fCK_INT, N=21FCK_INT_N4fSAMPLING=fCK_INT, N=42FCK_INT_N8fSAMPLING=fCK_INT, N=83FDTS_Div2_N6fSAMPLING=fDTS/2, N=64FDTS_Div2_N8fSAMPLING=fDTS/2, N=85FDTS_Div4_N6fSAMPLING=fDTS/4, N=66FDTS_Div4_N8fSAMPLING=fDTS/4, N=87FDTS_Div8_N6fSAMPLING=fDTS/8, N=68FDTS_Div8_N8fSAMPLING=fDTS/8, N=89FDTS_Div16_N5fSAMPLING=fDTS/16, N=510FDTS_Div16_N6fSAMPLING=fDTS/16, N=611FDTS_Div16_N8fSAMPLING=fDTS/16, N=812FDTS_Div32_N5fSAMPLING=fDTS/32, N=513FDTS_Div32_N6fSAMPLING=fDTS/32, N=614FDTS_Div32_N8fSAMPLING=fDTS/32, N=815 MSM Master/Slave mode 7 1 MSMread-writeNoSyncNo action0SyncThe effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.1 TS Trigger selection 4 3 TSread-writeITR0Internal Trigger 0 (ITR0)0ITR1Internal Trigger 1 (ITR1)1ITR2Internal Trigger 2 (ITR2)2TI1F_EDTI1 Edge Detector (TI1F_ED)4TI1FP1Filtered Timer Input 1 (TI1FP1)5TI2FP2Filtered Timer Input 2 (TI2FP2)6ETRFExternal Trigger input (ETRF)7 SMS Slave mode selection 0 3 SMSread-writeDisabledSlave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.0Encoder_Mode_1Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.1Encoder_Mode_2Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.2Encoder_Mode_3Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.3Reset_ModeReset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.4Gated_ModeGated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.5Trigger_ModeTrigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.6Ext_Clock_ModeExternal Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.7 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 TDEread-writeDisabledTrigger DMA request disabled0EnabledTrigger DMA request enabled1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1DEread-writeDisabledCCx DMA request disabled0EnabledCCx DMA request enabled1 UDE Update DMA request enable 8 1 UDEread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 TIE Trigger interrupt enable 6 1 TIEread-writeDisabledTrigger interrupt disabled0EnabledTrigger interrupt enabled1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC1IEread-writeDisabledCCx interrupt disabled0EnabledCCx interrupt enabled1 UIE Update interrupt enable 0 1 UIEread-writeDisabledUpdate interrupt disabled0EnabledUpdate interrupt enabled1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC1OFRreadOvercaptureThe counter value has been captured in TIMx_CCRx register while CCxIF flag was already set1 CC1OFWwriteClearClear flag0 TIF Trigger interrupt flag 6 1 TIFRreadNoTriggerNo trigger event occurred0TriggerTrigger interrupt pending1 TIFWwriteClearClear flag0 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1IFRreadMatchIf CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.1 CC1IFWwriteClearClear flag0 UIF Update interrupt flag 0 1 UIFread-writeClearNo update occurred0UpdatePendingUpdate interrupt pending.1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 TGWwriteTriggerThe TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 CC1GWwriteTriggerIf CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.1 UG Update generation 0 1 UGread-writeUpdateRe-initializes the timer counter and generates an update of the registers.1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE OC2CE 15 1 OC2M OC2M 12 3 OC2PE OC2PE 11 1 OC2PEread-writeDisabledPreload register on CCR2 disabled. New values written to CCR2 are taken into account immediately0EnabledPreload register on CCR2 enabled. Preload value is loaded into active register on each update event1 OC2FE OC2FE 10 1 CC2S CC2S 8 2 CC2Sread-writeOutputCC2 channel is configured as output0 OC1CE OC1CE 7 1 OC1M OC1M 4 3 OC1Mread-writeFrozenThe comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register1InactiveOnMatchSet channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register2ToggleOCyREF toggles when TIMx_CNT=TIMx_CCRy3ForceInactiveOCyREF is forced low4ForceActiveOCyREF is forced high5PwmMode1In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active6PwmMode2Inversely to PwmMode17 OC1PE OC1PE 3 1 OC1PEread-writeDisabledPreload register on CCR1 disabled. New values written to CCR1 are taken into account immediately0EnabledPreload register on CCR1 enabled. Preload value is loaded into active register on each update event1 OC1FE OC1FE 2 1 CC1S CC1S 0 2 CC1Sread-writeOutputCC1 channel is configured as output0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 015 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 CC2Sread-writeTI2CC2 channel is configured as input, IC2 is mapped on TI21TI1CC2 channel is configured as input, IC2 is mapped on TI12TRCCC2 channel is configured as input, IC2 is mapped on TRC3 IC1F Input capture 1 filter 4 4 IC1Fread-writeNoFilterNo filter, sampling is done at fDTS0FCK_INT_N2fSAMPLING=fCK_INT, N=21FCK_INT_N4fSAMPLING=fCK_INT, N=42FCK_INT_N8fSAMPLING=fCK_INT, N=83FDTS_Div2_N6fSAMPLING=fDTS/2, N=64FDTS_Div2_N8fSAMPLING=fDTS/2, N=85FDTS_Div4_N6fSAMPLING=fDTS/4, N=66FDTS_Div4_N8fSAMPLING=fDTS/4, N=87FDTS_Div8_N6fSAMPLING=fDTS/8, N=68FDTS_Div8_N8fSAMPLING=fDTS/8, N=89FDTS_Div16_N5fSAMPLING=fDTS/16, N=510FDTS_Div16_N6fSAMPLING=fDTS/16, N=611FDTS_Div16_N8fSAMPLING=fDTS/16, N=812FDTS_Div32_N5fSAMPLING=fDTS/32, N=513FDTS_Div32_N6fSAMPLING=fDTS/32, N=614FDTS_Div32_N8fSAMPLING=fDTS/32, N=815 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CC1Sread-writeTI1CC1 channel is configured as input, IC1 is mapped on TI11TI2CC1 channel is configured as input, IC1 is mapped on TI22TRCCC1 channel is configured as input, IC1 is mapped on TRC3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE O24CE 15 1 OC4M OC4M 12 3 OC4PE OC4PE 11 1 OC4PEread-writeDisabledPreload register on CCR4 disabled. New values written to CCR4 are taken into account immediately0EnabledPreload register on CCR4 enabled. Preload value is loaded into active register on each update event1 OC4FE OC4FE 10 1 CC4S CC4S 8 2 CC4Sread-writeOutputCC4 channel is configured as output0 OC3CE OC3CE 7 1 OC3M OC3M 4 3 OC3Mread-writeFrozenThe comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register1InactiveOnMatchSet channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register2ToggleOCyREF toggles when TIMx_CNT=TIMx_CCRy3ForceInactiveOCyREF is forced low4ForceActiveOCyREF is forced high5PwmMode1In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active6PwmMode2Inversely to PwmMode17 OC3PE OC3PE 3 1 OC3PEread-writeDisabledPreload register on CCR3 disabled. New values written to CCR3 are taken into account immediately0EnabledPreload register on CCR3 enabled. Preload value is loaded into active register on each update event1 OC3FE OC3FE 2 1 CC3S CC3S 0 2 CC3Sread-writeOutputCC3 channel is configured as output0 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 015 IC4PSC Input capture 4 prescaler 10 2 03 CC4S Capture/Compare 4 selection 8 2 CC4Sread-writeTI4CC4 channel is configured as input, IC4 is mapped on TI41TI3CC4 channel is configured as input, IC4 is mapped on TI32TRCCC4 channel is configured as input, IC4 is mapped on TRC3 IC3F Input capture 3 filter 4 4 015 IC3PSC Input capture 3 prescaler 2 2 03 CC3S Capture/compare 3 selection 0 2 CC3Sread-writeTI3CC3 channel is configured as input, IC3 is mapped on TI31TI4CC3 channel is configured as input, IC3 is mapped on TI42TRCCC3 channel is configured as input, IC3 is mapped on TRC3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H High counter value 16 16 CNT Counter value 0 16 065535 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 065535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR_H High Auto-reload value 16 16 ARR Auto-reload value 0 16 065535 40x41,2,3,4CCR%s CCR1 capture/compare register 0x34 0x20 read-write 0x00000000 CCR1_H High Capture/Compare 1 value 16 16 CCR Capture/Compare value 0 16 065535 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 018 DBA DMA base address 0 5 031 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 TIM4 0x40000800 TIM4 TIM4 global interrupt 30 TIM4 TIM4 global interrupt 30 TIM5 General-purpose-timers TIM 0x40000C00 0x0 0x400 registers TIM5 TIM5 global interrupt 50 TIM5 TIM5 global interrupt 50 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 CKDread-writeDiv1t_DTS = t_CK_INT0Div2t_DTS = 2 × t_CK_INT1Div4t_DTS = 4 × t_CK_INT2 ARPE Auto-reload preload enable 7 1 ARPEread-writeDisabledTIMx_APRR register is not buffered0EnabledTIMx_APRR register is buffered1 CMS Center-aligned mode selection 5 2 CMSread-writeEdgeAlignedThe counter counts up or down depending on the direction bit0CenterAligned1The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.1CenterAligned2The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.2CenterAligned3The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.3 DIR Direction 4 1 DIRread-writeUpCounter used as upcounter0DownCounter used as downcounter1 OPM One-pulse mode 3 1 OPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 URS Update request source 2 1 URSread-writeAnyEventAny of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request0CounterOnlyOnly counter overflow/underflow generates an update interrupt or DMA request1 UDIS Update disable 1 1 UDISread-writeEnabledUpdate event enabled0DisabledUpdate event disabled1 CEN Counter enable 0 1 CENread-writeDisabledCounter disabled0EnabledCounter enabled1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 TI1Sread-writeNormalThe TIMx_CH1 pin is connected to TI1 input0XORThe TIMx_CH1, CH2, CH3 pins are connected to TI1 input1 MMS Master mode selection 4 3 MMSread-writeResetThe UG bit from the TIMx_EGR register is used as trigger output0EnableThe counter enable signal, CNT_EN, is used as trigger output1UpdateThe update event is selected as trigger output2ComparePulseThe trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred3CompareOC1OC1REF signal is used as trigger output4CompareOC2OC2REF signal is used as trigger output5CompareOC3OC3REF signal is used as trigger output6CompareOC4OC4REF signal is used as trigger output7 CCDS Capture/compare DMA selection 3 1 CCDSread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ETPread-writeNotInvertedETR is noninverted, active at high level or rising edge0InvertedETR is inverted, active at low level or falling edge1 ECE External clock enable 14 1 ECEread-writeDisabledExternal clock mode 2 disabled0EnabledExternal clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.1 ETPS External trigger prescaler 12 2 ETPSread-writeDiv1Prescaler OFF0Div2ETRP frequency divided by 21Div4ETRP frequency divided by 42Div8ETRP frequency divided by 83 ETF External trigger filter 8 4 ETFread-writeNoFilterNo filter, sampling is done at fDTS0FCK_INT_N2fSAMPLING=fCK_INT, N=21FCK_INT_N4fSAMPLING=fCK_INT, N=42FCK_INT_N8fSAMPLING=fCK_INT, N=83FDTS_Div2_N6fSAMPLING=fDTS/2, N=64FDTS_Div2_N8fSAMPLING=fDTS/2, N=85FDTS_Div4_N6fSAMPLING=fDTS/4, N=66FDTS_Div4_N8fSAMPLING=fDTS/4, N=87FDTS_Div8_N6fSAMPLING=fDTS/8, N=68FDTS_Div8_N8fSAMPLING=fDTS/8, N=89FDTS_Div16_N5fSAMPLING=fDTS/16, N=510FDTS_Div16_N6fSAMPLING=fDTS/16, N=611FDTS_Div16_N8fSAMPLING=fDTS/16, N=812FDTS_Div32_N5fSAMPLING=fDTS/32, N=513FDTS_Div32_N6fSAMPLING=fDTS/32, N=614FDTS_Div32_N8fSAMPLING=fDTS/32, N=815 MSM Master/Slave mode 7 1 MSMread-writeNoSyncNo action0SyncThe effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.1 TS Trigger selection 4 3 TSread-writeITR0Internal Trigger 0 (ITR0)0ITR1Internal Trigger 1 (ITR1)1ITR2Internal Trigger 2 (ITR2)2TI1F_EDTI1 Edge Detector (TI1F_ED)4TI1FP1Filtered Timer Input 1 (TI1FP1)5TI2FP2Filtered Timer Input 2 (TI2FP2)6ETRFExternal Trigger input (ETRF)7 SMS Slave mode selection 0 3 SMSread-writeDisabledSlave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.0Encoder_Mode_1Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.1Encoder_Mode_2Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.2Encoder_Mode_3Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.3Reset_ModeReset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.4Gated_ModeGated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.5Trigger_ModeTrigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.6Ext_Clock_ModeExternal Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.7 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 TDEread-writeDisabledTrigger DMA request disabled0EnabledTrigger DMA request enabled1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 CC1DEread-writeDisabledCCx DMA request disabled0EnabledCCx DMA request enabled1 UDE Update DMA request enable 8 1 UDEread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 TIE Trigger interrupt enable 6 1 TIEread-writeDisabledTrigger interrupt disabled0EnabledTrigger interrupt enabled1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 CC1IEread-writeDisabledCCx interrupt disabled0EnabledCCx interrupt enabled1 UIE Update interrupt enable 0 1 UIEread-writeDisabledUpdate interrupt disabled0EnabledUpdate interrupt enabled1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 CC1OFRreadOvercaptureThe counter value has been captured in TIMx_CCRx register while CCxIF flag was already set1 CC1OFWwriteClearClear flag0 TIF Trigger interrupt flag 6 1 TIFRreadNoTriggerNo trigger event occurred0TriggerTrigger interrupt pending1 TIFWwriteClearClear flag0 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 CC1IFRreadMatchIf CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.1 CC1IFWwriteClearClear flag0 UIF Update interrupt flag 0 1 UIFread-writeClearNo update occurred0UpdatePendingUpdate interrupt pending.1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 TGWwriteTriggerThe TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 CC1GWwriteTriggerIf CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.1 UG Update generation 0 1 UGread-writeUpdateRe-initializes the timer counter and generates an update of the registers.1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE OC2CE 15 1 OC2M OC2M 12 3 OC2PE OC2PE 11 1 OC2PEread-writeDisabledPreload register on CCR2 disabled. New values written to CCR2 are taken into account immediately0EnabledPreload register on CCR2 enabled. Preload value is loaded into active register on each update event1 OC2FE OC2FE 10 1 CC2S CC2S 8 2 CC2Sread-writeOutputCC2 channel is configured as output0 OC1CE OC1CE 7 1 OC1M OC1M 4 3 OC1Mread-writeFrozenThe comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register1InactiveOnMatchSet channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register2ToggleOCyREF toggles when TIMx_CNT=TIMx_CCRy3ForceInactiveOCyREF is forced low4ForceActiveOCyREF is forced high5PwmMode1In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active6PwmMode2Inversely to PwmMode17 OC1PE OC1PE 3 1 OC1PEread-writeDisabledPreload register on CCR1 disabled. New values written to CCR1 are taken into account immediately0EnabledPreload register on CCR1 enabled. Preload value is loaded into active register on each update event1 OC1FE OC1FE 2 1 CC1S CC1S 0 2 CC1Sread-writeOutputCC1 channel is configured as output0 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 015 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 CC2Sread-writeTI2CC2 channel is configured as input, IC2 is mapped on TI21TI1CC2 channel is configured as input, IC2 is mapped on TI12TRCCC2 channel is configured as input, IC2 is mapped on TRC3 IC1F Input capture 1 filter 4 4 IC1Fread-writeNoFilterNo filter, sampling is done at fDTS0FCK_INT_N2fSAMPLING=fCK_INT, N=21FCK_INT_N4fSAMPLING=fCK_INT, N=42FCK_INT_N8fSAMPLING=fCK_INT, N=83FDTS_Div2_N6fSAMPLING=fDTS/2, N=64FDTS_Div2_N8fSAMPLING=fDTS/2, N=85FDTS_Div4_N6fSAMPLING=fDTS/4, N=66FDTS_Div4_N8fSAMPLING=fDTS/4, N=87FDTS_Div8_N6fSAMPLING=fDTS/8, N=68FDTS_Div8_N8fSAMPLING=fDTS/8, N=89FDTS_Div16_N5fSAMPLING=fDTS/16, N=510FDTS_Div16_N6fSAMPLING=fDTS/16, N=611FDTS_Div16_N8fSAMPLING=fDTS/16, N=812FDTS_Div32_N5fSAMPLING=fDTS/32, N=513FDTS_Div32_N6fSAMPLING=fDTS/32, N=614FDTS_Div32_N8fSAMPLING=fDTS/32, N=815 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CC1Sread-writeTI1CC1 channel is configured as input, IC1 is mapped on TI11TI2CC1 channel is configured as input, IC1 is mapped on TI22TRCCC1 channel is configured as input, IC1 is mapped on TRC3 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE O24CE 15 1 OC4M OC4M 12 3 OC4PE OC4PE 11 1 OC4PEread-writeDisabledPreload register on CCR4 disabled. New values written to CCR4 are taken into account immediately0EnabledPreload register on CCR4 enabled. Preload value is loaded into active register on each update event1 OC4FE OC4FE 10 1 CC4S CC4S 8 2 CC4Sread-writeOutputCC4 channel is configured as output0 OC3CE OC3CE 7 1 OC3M OC3M 4 3 OC3Mread-writeFrozenThe comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register1InactiveOnMatchSet channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register2ToggleOCyREF toggles when TIMx_CNT=TIMx_CCRy3ForceInactiveOCyREF is forced low4ForceActiveOCyREF is forced high5PwmMode1In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active6PwmMode2Inversely to PwmMode17 OC3PE OC3PE 3 1 OC3PEread-writeDisabledPreload register on CCR3 disabled. New values written to CCR3 are taken into account immediately0EnabledPreload register on CCR3 enabled. Preload value is loaded into active register on each update event1 OC3FE OC3FE 2 1 CC3S CC3S 0 2 CC3Sread-writeOutputCC3 channel is configured as output0 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 015 IC4PSC Input capture 4 prescaler 10 2 03 CC4S Capture/Compare 4 selection 8 2 CC4Sread-writeTI4CC4 channel is configured as input, IC4 is mapped on TI41TI3CC4 channel is configured as input, IC4 is mapped on TI32TRCCC4 channel is configured as input, IC4 is mapped on TRC3 IC3F Input capture 3 filter 4 4 015 IC3PSC Input capture 3 prescaler 2 2 03 CC3S Capture/compare 3 selection 0 2 CC3Sread-writeTI3CC3 channel is configured as input, IC3 is mapped on TI31TI4CC3 channel is configured as input, IC3 is mapped on TI42TRCCC3 channel is configured as input, IC3 is mapped on TRC3 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNTCounter value03204294967295 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 065535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARRAuto-reload value03204294967295 40x41,2,3,4CCR%s CCR1 capture/compare register 0x34 0x20 read-write 0x00000000 CCRCapture/Compare value03204294967295 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 018 DBA DMA base address 0 5 031 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 OR OR TIM5 option register 0x50 0x20 read-write 0x0000 IT4_RMP Timer Input 4 remap 6 2 TIM9 General purpose timers TIM 0x40014000 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 CKDread-writeDiv1t_DTS = t_CK_INT0Div2t_DTS = 2 × t_CK_INT1Div4t_DTS = 4 × t_CK_INT2 ARPE Auto-reload preload enable 7 1 ARPEread-writeDisabledTIMx_APRR register is not buffered0EnabledTIMx_APRR register is buffered1 OPM One-pulse mode 3 1 OPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 URS Update request source 2 1 URSread-writeAnyEventAny of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request0CounterOnlyOnly counter overflow/underflow generates an update interrupt or DMA request1 UDIS Update disable 1 1 UDISread-writeEnabledUpdate event enabled0DisabledUpdate event disabled1 CEN Counter enable 0 1 CENread-writeDisabledCounter disabled0EnabledCounter enabled1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS Master mode selection 4 3 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TIE Trigger interrupt enable 6 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 UIEread-writeDisabledUpdate interrupt disabled0EnabledUpdate interrupt enabled1 SR SR status register 0x10 0x20 read-write 0x0000 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 UIFread-writeClearNo update occurred0UpdatePendingUpdate interrupt pending.1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 UGread-writeUpdateRe-initializes the timer counter and generates an update of the registers.1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1M Output Compare 1 mode 4 3 OC1Mread-writeFrozenThe comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register1InactiveOnMatchSet channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register2ToggleOCyREF toggles when TIMx_CNT=TIMx_CCRy3ForceInactiveOCyREF is forced low4ForceActiveOCyREF is forced high5PwmMode1In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active6PwmMode2Inversely to PwmMode17 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 3 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 3 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 065535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 20x41,2CCR%s CCR1 capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 TIM12 0x40001800 TIM10 General-purpose-timers TIM 0x40014400 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 CKDread-writeDiv1t_DTS = t_CK_INT0Div2t_DTS = 2 × t_CK_INT1Div4t_DTS = 4 × t_CK_INT2 ARPE Auto-reload preload enable 7 1 ARPEread-writeDisabledTIMx_APRR register is not buffered0EnabledTIMx_APRR register is buffered1 URS Update request source 2 1 URSread-writeAnyEventAny of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request0CounterOnlyOnly counter overflow/underflow generates an update interrupt or DMA request1 UDIS Update disable 1 1 UDISread-writeEnabledUpdate event enabled0DisabledUpdate event disabled1 CEN Counter enable 0 1 CENread-writeDisabledCounter disabled0EnabledCounter enabled1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 UIEread-writeDisabledUpdate interrupt disabled0EnabledUpdate interrupt enabled1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 UIFread-writeClearNo update occurred0UpdatePendingUpdate interrupt pending.1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 UGread-writeUpdateRe-initializes the timer counter and generates an update of the registers.1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC1M Output Compare 1 mode 4 3 OC1Mread-writeFrozenThe comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register1InactiveOnMatchSet channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register2ToggleOCyREF toggles when TIMx_CNT=TIMx_CCRy3ForceInactiveOCyREF is forced low4ForceActiveOCyREF is forced high5PwmMode1In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active6PwmMode2Inversely to PwmMode17 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 065535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 10x01-1CCR%s CCR1 capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 TIM13 0x40001C00 TIM8_UP_TIM13 TIM8 Update interrupt and TIM13 global interrupt 44 TIM8_UP_TIM13 TIM8 Update interrupt and TIM13 global interrupt 44 TIM8_UP_TIM13 TIM8 Update interrupt and TIM13 global interrupt 44 TIM8_UP_TIM13 TIM8 Update interrupt and TIM13 global interrupt 44 TIM14 0x40002000 TIM8_TRG_COM_TIM14 TIM8 Trigger and Commutation interrupts and TIM14 global interrupt 45 TIM8_TRG_COM_TIM14 TIM8 Trigger and Commutation interrupts and TIM14 global interrupt 45 TIM11 General-purpose-timers TIM 0x40014800 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 CKDread-writeDiv1t_DTS = t_CK_INT0Div2t_DTS = 2 × t_CK_INT1Div4t_DTS = 4 × t_CK_INT2 ARPE Auto-reload preload enable 7 1 ARPEread-writeDisabledTIMx_APRR register is not buffered0EnabledTIMx_APRR register is buffered1 URS Update request source 2 1 URSread-writeAnyEventAny of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request0CounterOnlyOnly counter overflow/underflow generates an update interrupt or DMA request1 UDIS Update disable 1 1 UDISread-writeEnabledUpdate event enabled0DisabledUpdate event disabled1 CEN Counter enable 0 1 CENread-writeDisabledCounter disabled0EnabledCounter enabled1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 UIEread-writeDisabledUpdate interrupt disabled0EnabledUpdate interrupt enabled1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 UIFread-writeClearNo update occurred0UpdatePendingUpdate interrupt pending.1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 UGread-writeUpdateRe-initializes the timer counter and generates an update of the registers.1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC1M Output Compare 1 mode 4 3 OC1Mread-writeFrozenThe comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register1InactiveOnMatchSet channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register2ToggleOCyREF toggles when TIMx_CNT=TIMx_CCRy3ForceInactiveOCyREF is forced low4ForceActiveOCyREF is forced high5PwmMode1In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active6PwmMode2Inversely to PwmMode17 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 065535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 10x01-1CCR%s CCR1 capture/compare register 0x34 0x20 read-write 0x00000000 CCR Capture/Compare value 0 16 OR OR option register 0x50 0x20 read-write 0x00000000 RMP Input 1 remapping capability 0 2 TIM6 Basic timers TIM 0x40001000 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 ARPE Auto-reload preload enable 7 1 ARPEread-writeDisabledTIMx_APRR register is not buffered0EnabledTIMx_APRR register is buffered1 OPM One-pulse mode 3 1 OPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 URS Update request source 2 1 URSread-writeAnyEventAny of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request0CounterOnlyOnly counter overflow/underflow generates an update interrupt or DMA request1 UDIS Update disable 1 1 UDISread-writeEnabledUpdate event enabled0DisabledUpdate event disabled1 CEN Counter enable 0 1 CENread-writeDisabledCounter disabled0EnabledCounter enabled1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS Master mode selection 4 3 MMSread-writeResetUse UG bit from TIMx_EGR register0EnableUse CNT bit from TIMx_CEN register1UpdateUse the update event2 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UDE Update DMA request enable 8 1 UDEread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 UIE Update interrupt enable 0 1 UIEread-writeDisabledUpdate interrupt disabled0EnabledUpdate interrupt enabled1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag 0 1 UIFread-writeClearNo update occurred0UpdatePendingUpdate interrupt pending.1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation 0 1 UGread-writeUpdateRe-initializes the timer counter and generates an update of the registers.1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Low counter value 0 16 065535 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 065535 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Low Auto-reload value 0 16 065535 TIM7 0x40001400 TIM7 TIM7 global interrupt 55 TIM7 TIM7 global interrupt 55 Ethernet_MAC Ethernet: media access control (MAC) Ethernet 0x40028000 0x0 0x61 registers ETH Ethernet global interrupt 61 ETH Ethernet global interrupt 61 ETH_WKUP Ethernet Wakeup through EXTI line interrupt 62 ETH_WKUP Ethernet Wakeup through EXTI line interrupt 62 MACCR MACCR Ethernet MAC configuration register 0x0 0x20 read-write 0x0008000 RE Receiver enable 2 1 REread-writeDisabledMAC receive state machine is disabled after the completion of the reception of the current frame0EnabledMAC receive state machine is enabled1 TE Transmitter enable 3 1 TEread-writeDisabledMAC transmit state machine is disabled after completion of the transmission of the current frame0EnabledMAC transmit state machine is enabled1 DC Deferral check 4 1 DCread-writeDisabledMAC defers until CRS signal goes inactive0EnabledDeferral check function enabled1 BL Back-off limit 5 2 BLread-writeBL10For retransmission n, wait up to 2^min(n, 10) time slots0BL8For retransmission n, wait up to 2^min(n, 8) time slots1BL4For retransmission n, wait up to 2^min(n, 4) time slots2BL1For retransmission n, wait up to 2^min(n, 1) time slots3 APCS Automatic pad/CRC stripping 7 1 APCSread-writeDisabledMAC passes all incoming frames unmodified0StripMAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes1 RD Retry disable 9 1 RDread-writeEnabledMAC attempts retries based on the settings of BL0DisabledMAC attempts only 1 transmission1 IPCO IPv4 checksum offload 10 1 IPCOread-writeDisabledIPv4 checksum offload disabled0OffloadIPv4 checksums are checked in received frames1 DM Duplex mode 11 1 DMread-writeHalfDuplexMAC operates in half-duplex mode0FullDuplexMAC operates in full-duplex mode1 LM Loopback mode 12 1 LMread-writeNormalNormal mode0LoopbackMAC operates in loopback mode at the MII1 ROD Receive own disable 13 1 RODread-writeEnabledMAC receives all packets from PHY while transmitting0DisabledMAC disables reception of frames in half-duplex mode1 FES Fast Ethernet speed 14 1 FESread-writeFES1010 Mbit/s0FES100100 Mbit/s1 CSD Carrier sense disable 16 1 CSDread-writeEnabledErrors generated due to loss of carrier0DisabledNo error generated due to loss of carrier1 IFG Interframe gap 17 3 IFGread-writeIFG9696 bit times0IFG8888 bit times1IFG8080 bit times2IFG7272 bit times3IFG6464 bit times4IFG5656 bit times5IFG4848 bit times6IFG4040 bit times7 JD Jabber disable 22 1 JDread-writeEnabledJabber enabled, transmit frames up to 2048 bytes0DisabledJabber disabled, transmit frames up to 16384 bytes1 WD Watchdog disable 23 1 WDread-writeEnabledWatchdog enabled, receive frames limited to 2048 bytes0DisabledWatchdog disabled, receive frames may be up to to 16384 bytes1 CSTF CRC stripping for type frames 25 1 CSTFread-writeDisabledCRC not stripped0EnabledCRC stripped1 MACFFR MACFFR Ethernet MAC frame filter register 0x4 0x20 read-write 0x00000000 PM Promiscuous mode 0 1 PMread-writeDisabledNormal address filtering0EnabledAddress filters pass all incoming frames regardless of their destination or source address1 HU Hash unicast 1 1 HUread-writePerfectMAC performs a perfect destination address filtering for unicast frames0HashMAC performs destination address filtering of received unicast frames according to the hash table1 HM Hash multicast 2 1 HMread-writePerfectMAC performs a perfect destination address filtering for multicast frames0HashMAC performs destination address filtering of received multicast frames according to the hash table1 DAIF Destination address unique filtering 3 1 DAIFread-writeNormalNormal filtering of frames0InvertAddress check block operates in inverse filtering mode for the DA address comparison1 PAM Pass all multicast 4 1 PAMread-writeDisabledFiltering of multicast frames depends on HM0EnabledAll received frames with a multicast destination address are passed1 BFD Broadcast frames disable 5 1 BFDread-writeEnabledAddress filters pass all received broadcast frames0DisabledAddress filters filter all incoming broadcast frames1 PCF Pass control frames 6 2 PCFread-writePreventAllMAC prevents all control frames from reaching the application0ForwardAllExceptPauseMAC forwards all control frames to application except Pause1ForwardAllMAC forwards all control frames to application even if they fail the address filter2ForwardAllFilteredMAC forwards control frames that pass the address filter3 SAIF Source address inverse filtering 7 1 SAIFread-writeNormalSource address filter operates normally0InvertSource address filter operation inverted1 SAF Source address filter 8 1 SAFread-writeDisabledSource address ignored0EnabledMAC drops frames that fail the source address filter1 HPF Hash or perfect filter 9 1 HPFread-writeHashOnlyIf HM or HU is set, only frames that match the Hash filter are passed0HashOrPerfectIf HM or HU is set, frames that match either the perfect filter or the hash filter are passed1 RA Receive all 31 1 RAread-writeDisabledMAC receiver passes on to the application only those frames that have passed the SA/DA address file0EnabledMAC receiver passes oll received frames on to the application1 MACHTHR MACHTHR Ethernet MAC hash table high register 0x8 0x20 read-write 0x00000000 HTH Upper 32 bits of hash table 0 32 04294967295 MACHTLR MACHTLR Ethernet MAC hash table low register 0xC 0x20 read-write 0x00000000 HTL Lower 32 bits of hash table 0 32 04294967295 MACMIIAR MACMIIAR Ethernet MAC MII address register 0x10 0x20 read-write 0x00000000 MB MII busy 0 1 MBread-writeBusyThis bit is set to 1 by the application to indicate that a read or write access is in progress1 MW MII write 1 1 MWread-writeReadRead operation0WriteWrite operation1 CR Clock range 2 3 CRread-writeCR_60_10060-100MHz HCLK/420CR_100_150100-150 MHz HCLK/621CR_20_3520-35MHz HCLK/162CR_35_6035-60MHz HCLK/163CR_150_168150-168MHz HCLK/1024 MR MII register - select the desired MII register in the PHY device 6 5 031 PA PHY address - select which of possible 32 PHYs is being accessed 11 5 031 MACMIIDR MACMIIDR Ethernet MAC MII data register 0x14 0x20 read-write 0x00000000 MD MII data read from/written to the PHY 0 16 065535 MACFCR MACFCR Ethernet MAC flow control register 0x18 0x20 read-write 0x00000000 FCB Flow control busy/back pressure activate 0 1 FCBread-writePauseOrBackPressureIn full duplex, initiate a Pause control frame. In half duplex, assert back pressure1DisableBackPressureIn half duplex only, deasserts back pressure0 TFCE Transmit flow control enable 1 1 TFCEread-writeDisabledIn full duplex, flow control is disabled. In half duplex, back pressure is disabled0EnabledIn full duplex, flow control is enabled. In half duplex, back pressure is enabled1 RFCE Receive flow control enable 2 1 RFCEread-writeDisabledPause frames are not decoded0EnabledMAC decodes received Pause frames and disables its transmitted for a specified time1 UPFD Unicast pause frame detect 3 1 UPFDread-writeDisabledMAC detects only a Pause frame with the multicast address specified in the 802.3x standard0EnabledMAC additionally detects Pause frames with the station's unicast address1 PLT Pause low threshold 4 2 PLTread-writePLT4Pause time minus 4 slot times0PLT28Pause time minus 28 slot times1PLT144Pause time minus 144 slot times2PLT256Pause time minus 256 slot times3 ZQPD Zero-quanta pause disable 7 1 ZQPDread-writeEnabledNormal operation with automatic zero-quanta pause control frame generation0DisabledAutomatic generation of zero-quanta pause control frames is disabled1 PT Pause time 16 16 065535 MACVLANTR MACVLANTR Ethernet MAC VLAN tag register 0x1C 0x20 read-write 0x00000000 VLANTI VLAN tag identifier (for receive frames) 0 16 065535 VLANTC 12-bit VLAN tag comparison 16 1 VLANTCread-writeVLANTC16Full 16 bit VLAN identifiers are used for comparison and filtering0VLANTC1212 bit VLAN identifies are used for comparison and filtering1 MACPMTCSR MACPMTCSR Ethernet MAC PMT control and status register 0x2C 0x20 read-write 0x00000000 PD Power down 0 1 PDread-writeEnabledAll received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received1 MPE Magic packet enable 1 1 MPEread-writeDisabledNo power management event generated due to Magic Packet reception0EnabledEnable generation of a power management event due to Magic Packet reception1 WFE Wakeup frame enable 2 1 WFEread-writeDisabledNo power management event generated due to wakeup frame reception0EnabledEnable generation of a power management event due to wakeup frame reception1 MPR Magic packet received 5 1 WFR Wakeup frame received 6 1 GU Global unicast 9 1 GUread-writeDisabledNormal operation0EnabledAny unicast packet filtered by the MAC address recognition may be a wakeup frame1 WFFRPR Wakeup frame filter register pointer reset 31 1 WFFRPRread-writeResetReset wakeup frame filter register point to 0b000. Automatically cleared1 MACDBGR MACDBGR Ethernet MAC debug register 0x34 0x20 read-only 0x00000000 TFFTx FIFO full251 TFNETx FIFO not empty241 TFWATx FIFO write active221 TFRSTx FIFO read status202 MTPMAC transmitter in pause191 MTFCSMAC transmit frame controller status172 MMTEAMAC MII transmit engine active161 RFFLRx FIFO fill level82 RFRCSRx FIFO read controller status52 RFWRARx FIFO write controller active41 MSFRWCSMAC small FIFO read/write controllers status12 MMRPEAMAC MII receive protocol engine active01 MACSR MACSR Ethernet MAC interrupt status register 0x38 0x20 0x00000000 PMTS PMT status 3 1 read-only MMCS MMC status 4 1 read-only MMCRS MMC receive status 5 1 read-only MMCTS MMC transmit status 6 1 read-only TSTS Time stamp trigger status 9 1 read-write MACIMR MACIMR Ethernet MAC interrupt mask register 0x3C 0x20 read-write 0x00000000 PMTIM PMT interrupt mask 3 1 PMTIMread-writeUnmaskedPMT Status interrupt generation enabled0MaskedPMT Status interrupt generation disabled1 TSTIM Time stamp trigger interrupt mask 9 1 TSTIMread-writeUnmaskedTime stamp interrupt generation enabled0MaskedTime stamp interrupt generation disabled1 MACA0HR MACA0HR Ethernet MAC address 0 high register 0x40 0x20 0x0010FFFF MACA0H MAC address0 high 0 16 read-write 065535 MO Always 1 31 1 read-only MACA0LR MACA0LR Ethernet MAC address 0 low register 0x44 0x20 read-write 0xFFFFFFFF MACA0L 0 0 32 04294967295 MACA1HR MACA1HR Ethernet MAC address 1 high register 0x48 0x20 read-write 0x0000FFFF MACA1H MACA1H 0 16 065535 MBC MBC 24 6 063 SA SA 30 1 SAread-writeDestinationThis address is used for comparison with DA fields of the received frame0SourceThis address is used for comparison with SA fields of received frames1 AE AE 31 1 AEread-writeDisabledAddress filters ignore this address0EnabledAddress filters use this address1 MACA1LR MACA1LR Ethernet MAC address1 low register 0x4C 0x20 read-write 0xFFFFFFFF MACA1L MACA1LR 0 32 04294967295 MACA2HR MACA2HR Ethernet MAC address 2 high register 0x50 0x20 read-write 0x0000FFFF MACA2H MAC2AH 0 16 065535 MBC MBC 24 6 063 SA SA 30 1 SAread-writeDestinationThis address is used for comparison with DA fields of the received frame0SourceThis address is used for comparison with SA fields of received frames1 AE AE 31 1 AEread-writeDisabledAddress filters ignore this address0EnabledAddress filters use this address1 MACA2LR MACA2LR Ethernet MAC address 2 low register 0x54 0x20 read-write 0xFFFFFFFF MACA2L MACA2L 0 32 04294967295 MACA3HR MACA3HR Ethernet MAC address 3 high register 0x58 0x20 read-write 0x0000FFFF MACA3H MACA3H 0 16 065535 MBC MBC 24 6 063 SA SA 30 1 SAread-writeDestinationThis address is used for comparison with DA fields of the received frame0SourceThis address is used for comparison with SA fields of received frames1 AE AE 31 1 AEread-writeDisabledAddress filters ignore this address0EnabledAddress filters use this address1 MACA3LR MACA3LR Ethernet MAC address 3 low register 0x5C 0x20 read-write 0xFFFFFFFF MACA3L MBCA3L 0 32 04294967295 Ethernet_MMC Ethernet: MAC management counters Ethernet 0x40028100 0x0 0x400 registers MMCCR MMCCR Ethernet MMC control register 0x0 0x20 read-write 0x00000000 CR Counter reset 0 1 CRread-writeResetReset all counters. Cleared automatically1 CSR Counter stop rollover 1 1 CSRread-writeDisabledCounters roll over to zero after reaching the maximum value0EnabledCounters do not roll over to zero after reaching the maximum value1 ROR Reset on read 2 1 RORread-writeDisabledMMC counters do not reset on read0EnabledMMC counters reset to zero after read1 MCF MMC counter freeze 3 1 MCFread-writeUnfrozenAll MMC counters update normally0FrozenAll MMC counters frozen to their current value1 MCP MMC counter preset 4 1 MCPread-writePresetMMC counters will be preset to almost full or almost half. Cleared automatically1 MCFHP MMC counter Full-Half preset 5 1 MCFHPread-writeAlmostHalfWhen MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF00AlmostFullWhen MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF01 MMCRIR MMCRIR Ethernet MMC receive interrupt register 0x4 0x20 read-write 0x00000000 RFCES Received frames CRC error status 5 1 RFAES Received frames alignment error status 6 1 RGUFS Received good Unicast frames status 17 1 MMCTIR MMCTIR Ethernet MMC transmit interrupt register 0x8 0x20 read-only 0x00000000 TGFSCS Transmitted good frames single collision status 14 1 TGFMSCS Transmitted good frames more than single collision status 15 1 TGFS Transmitted good frames status 21 1 MMCRIMR MMCRIMR Ethernet MMC receive interrupt mask register 0xC 0x20 read-write 0x00000000 RFCEM Received frame CRC error mask 5 1 RFCEMread-writeUnmaskedReceived-crc-error counter half-full interrupt enabled0MaskedReceived-crc-error counter half-full interrupt disabled1 RFAEM Received frames alignment error mask 6 1 RFAEMread-writeUnmaskedReceived-alignment-error counter half-full interrupt enabled0MaskedReceived-alignment-error counter half-full interrupt disabled1 RGUFM Received good Unicast frames mask 17 1 RGUFMread-writeUnmaskedReceived-good-unicast counter half-full interrupt enabled0MaskedReceived-good-unicast counter half-full interrupt disabled1 MMCTIMR MMCTIMR Ethernet MMC transmit interrupt mask register 0x10 0x20 read-write 0x00000000 TGFSCM Transmitted good frames single collision mask 14 1 TGFSCMread-writeUnmaskedTransmitted-good-single-collision half-full interrupt enabled0MaskedTransmitted-good-single-collision half-full interrupt disabled1 TGFMSCM Transmitted good frames more than single collision mask 15 1 TGFMSCMread-writeUnmaskedTransmitted-good-multiple-collision half-full interrupt enabled0MaskedTransmitted-good-multiple-collision half-full interrupt disabled1 TGFM Transmitted good frames mask 16 1 TGFMread-writeUnmaskedTransmitted-good counter half-full interrupt enabled0MaskedTransmitted-good counter half-full interrupt disabled1 MMCTGFSCCR MMCTGFSCCR Ethernet MMC transmitted good frames after a single collision counter 0x4C 0x20 read-only 0x00000000 TGFSCC Transmitted good frames single collision counter 0 32 MMCTGFMSCCR MMCTGFMSCCR Ethernet MMC transmitted good frames after more than a single collision 0x50 0x20 read-only 0x00000000 TGFMSCC TGFMSCC 0 32 MMCTGFCR MMCTGFCR Ethernet MMC transmitted good frames counter register 0x68 0x20 read-only 0x00000000 TGFC HTL 0 32 MMCRFCECR MMCRFCECR Ethernet MMC received frames with CRC error counter register 0x94 0x20 read-only 0x00000000 RFCFC RFCFC 0 32 MMCRFAECR MMCRFAECR Ethernet MMC received frames with alignment error counter register 0x98 0x20 read-only 0x00000000 RFAEC RFAEC 0 32 MMCRGUFCR MMCRGUFCR MMC received good unicast frames counter register 0xC4 0x20 read-only 0x00000000 RGUFC RGUFC 0 32 Ethernet_PTP Ethernet: Precision time protocol Ethernet 0x40028700 0x0 0x400 registers PTPTSCR PTPTSCR Ethernet PTP time stamp control register 0x0 0x20 read-write 0x00002000 TSE TSE 0 1 TSFCU TSFCU 1 1 TSPTPPSV2E TSPTPPSV2E 10 1 TSSPTPOEFE TSSPTPOEFE 11 1 TSSIPV6FE TSSIPV6FE 12 1 TSSIPV4FE TSSIPV4FE 13 1 TSSEME TSSEME 14 1 TSSMRME TSSMRME 15 1 TSCNT TSCNT 16 2 TSPFFMAE TSPFFMAE 18 1 TSSTI TSSTI 2 1 TSSTU TSSTU 3 1 TSITE TSITE 4 1 TTSARU TTSARU 5 1 TSSARFE TSSARFE 8 1 TSSSR TSSSR 9 1 PTPSSIR PTPSSIR Ethernet PTP subsecond increment register 0x4 0x20 read-write 0x00000000 STSSI STSSI 0 8 PTPTSHR PTPTSHR Ethernet PTP time stamp high register 0x8 0x20 read-only 0x00000000 STS STS 0 32 PTPTSLR PTPTSLR Ethernet PTP time stamp low register 0xC 0x20 read-only 0x00000000 STSS STSS 0 31 STPNS STPNS 31 1 PTPTSHUR PTPTSHUR Ethernet PTP time stamp high update register 0x10 0x20 read-write 0x00000000 TSUS TSUS 0 32 PTPTSLUR PTPTSLUR Ethernet PTP time stamp low update register 0x14 0x20 read-write 0x00000000 TSUSS TSUSS 0 31 TSUPNS TSUSS 31 1 PTPTSAR PTPTSAR Ethernet PTP time stamp addend register 0x18 0x20 read-write 0x00000000 TSA TSA 0 32 PTPTTHR PTPTTHR Ethernet PTP target time high register 0x1C 0x20 read-write 0x00000000 TTSH 0 0 32 PTPTTLR PTPTTLR Ethernet PTP target time low register 0x20 0x20 read-write 0x00000000 TTSL TTSL 0 32 PTPTSSR PTPTSSR Ethernet PTP time stamp status register 0x28 0x20 read-only 0x00000000 TSSO TSSO 0 1 TSTTR TSTTR 1 1 PTPPPSCR PTPPPSCR Ethernet PTP PPS control register 0x2C 0x20 read-only 0x00000000 TSSO TSSO 0 1 TSTTR TSTTR 1 1 Ethernet_DMA Ethernet: DMA controller operation Ethernet 0x40029000 0x0 0x400 registers DMABMR DMABMR Ethernet DMA bus mode register 0x0 0x20 read-write 0x00002101 SR Software reset 0 1 SRread-writeResetReset all MAC subsystem internal registers and logic. Cleared automatically1 DA DMA arbitration 1 1 DAread-writeRoundRobinRound-robin with Rx:Tx priority given by PM0RxPriorityRx has priority over Tx1 DSL Descriptor skip length 2 5 031 EDFE Enhanced descriptor format enable 7 1 EDFEread-writeDisabledNormal descriptor format0EnabledEnhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload1 PBL Programmable burst length 8 6 PBLread-writePBL1Maximum of 1 beat per DMA transaction1PBL2Maximum of 2 beats per DMA transaction2PBL4Maximum of 4 beats per DMA transaction4PBL8Maximum of 8 beats per DMA transaction8PBL16Maximum of 16 beats per DMA transaction16PBL32Maximum of 32 beats per DMA transaction32 PM Rx-Tx priority ratio 14 2 PMread-writeOneToOneRxDMA priority over TxDMA is 1:10TwoToOneRxDMA priority over TxDMA is 2:11ThreeToOneRxDMA priority over TxDMA is 3:12FourToOneRxDMA priority over TxDMA is 4:13 FB Fixed burst 16 1 FBread-writeVariableAHB uses SINGLE and INCR burst transfers0FixedAHB uses only fixed burst transfers1 RDP Rx DMA PBL 17 6 RDPread-writeRDP11 beat per RxDMA transaction1RDP22 beats per RxDMA transaction2RDP44 beats per RxDMA transaction4RDP88 beats per RxDMA transaction8RDP1616 beats per RxDMA transaction16RDP3232 beats per RxDMA transaction32 USP Use separate PBL 23 1 USPread-writeCombinedPBL value used for both Rx and Tx DMA0SeparateRxDMA uses RDP value, TxDMA uses PBL value1 FPM 4xPBL mode 24 1 FPMread-writex1PBL values used as-is0x4PBL values multiplied by 41 AAB Address-aligned beats 25 1 AABread-writeUnalignedBursts are not aligned0AlignedAlign bursts to start address LS bits. First burst alignment depends on FB bit1 MB Mixed burst 26 1 MBread-writeNormalFixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below0MixedIf FB is low, start all bursts greater than 16 with INCR (undefined burst)1 DMATPDR DMATPDR Ethernet DMA transmit poll demand register 0x4 0x20 read-write 0x00000000 TPD Transmit poll demand 0 32 TPDread-writePollPoll the transmit descriptor list0 DMARPDR DMARPDR EHERNET DMA receive poll demand register 0x8 0x20 read-write 0x00000000 RPD Receive poll demand 0 32 RPDread-writePollPoll the receive descriptor list0 DMARDLAR DMARDLAR Ethernet DMA receive descriptor list address register 0xC 0x20 read-write 0x00000000 SRL Start of receive list 0 32 DMATDLAR DMATDLAR Ethernet DMA transmit descriptor list address register 0x10 0x20 read-write 0x00000000 STL Start of transmit list 0 32 DMASR DMASR Ethernet DMA status register 0x14 0x20 0x00000000 TS Transmit status 0 1 read-write TPSS Transmit process stopped status 1 1 read-write TBUS Transmit buffer unavailable status 2 1 read-write TJTS Transmit jabber timeout status 3 1 read-write ROS Receive overflow status 4 1 read-write TUS Transmit underflow status 5 1 read-write RS Receive status 6 1 read-write RBUS Receive buffer unavailable status 7 1 read-write RPSS Receive process stopped status 8 1 read-write PWTS PWTS 9 1 read-write ETS Early transmit status 10 1 read-write FBES Fatal bus error status 13 1 read-write ERS Early receive status 14 1 read-write AIS Abnormal interrupt summary 15 1 read-write NIS Normal interrupt summary 16 1 read-write RPS Receive process state 17 3 read-only RPSread-writeStoppedStopped, reset or Stop Receive command issued0RunningFetchingRunning, fetching receive transfer descriptor1RunningWaitingRunning, waiting for receive packet3SuspendedSuspended, receive descriptor unavailable4RunningWritingRunning, writing data to host memory buffer7 TPS Transmit process state 20 3 read-only TPSread-writeStoppedStopped, Reset or Stop Transmit command issued0RunningFetchingRunning, fetching transmit transfer descriptor1RunningWaitingRunning, waiting for status2RunningReadingRunning, reading data from host memory buffer3SuspendedSuspended, transmit descriptor unavailable or transmit buffer underflow6RunningRunning, closing transmit descriptor7 EBS Error bits status 23 3 read-only MMCS MMC status 27 1 read-only PMTS PMT status 28 1 read-only TSTS Time stamp trigger status 29 1 read-only DMAOMR DMAOMR Ethernet DMA operation mode register 0x18 0x20 read-write 0x00000000 SR Start/stop receive 1 1 SRread-writeStoppedReception is stopped after transfer of the current frame0StartedReception is placed in the Running state1 OSF Operate on second frame 2 1 RTC Receive threshold control 3 2 RTCread-writeRTC6464 bytes0RTC3232 bytes1RTC9696 bytes2RTC128128 bytes3 FUGF Forward undersized good frames 6 1 FUGFread-writeDropRx FIFO drops all frames of less than 64 bytes0ForwardRx FIFO forwards undersized frames1 FEF Forward error frames 7 1 FEFread-writeDropRx FIFO drops frames with error status0ForwardAll frames except runt error frames are forwarded to the DMA1 ST Start/stop transmission 13 1 STread-writeStoppedTransmission is placed in the Stopped state0StartedTransmission is placed in Running state1 TTC Transmit threshold control 14 3 TTCread-writeTTC6464 bytes0TTC128128 bytes1TTC192192 bytes2TTC256256 bytes3TTC4040 bytes4TTC3232 bytes5TTC2424 bytes6TTC1616 bytes7 FTF Flush transmit FIFO 20 1 FTFread-writeFlushTransmit FIFO controller logic is reset to its default values. Cleared automatically1 TSF Transmit store and forward 21 1 TSFread-writeCutThroughTransmission starts when the frame size in the Tx FIFO exceeds TTC threshold0StoreForwardTransmission starts when a full frame is in the Tx FIFO1 DFRF Disable flushing of received frames 24 1 RSF Receive store and forward 25 1 RSFread-writeCutThroughRx FIFO operates in cut-through mode, subject to RTC bits0StoreForwardFrames are read from Rx FIFO after complete frame has been written1 DTCEFD Dropping of TCP/IP checksum error frames disable 26 1 DTCEFDread-writeEnabledDrop frames with errors only in the receive checksum offload engine0DisabledDo not drop frames that only have errors in the receive checksum offload engine1 DMAIER DMAIER Ethernet DMA interrupt enable register 0x1C 0x20 read-write 0x00000000 TIE Transmit interrupt enable 0 1 TPSIE Transmit process stopped interrupt enable 1 1 TBUIE Transmit buffer unavailable interrupt enable 2 1 TJTIE Transmit jabber timeout interrupt enable 3 1 ROIE Receive overflow interrupt enable 4 1 TUIE Transmit underflow interrupt enable 5 1 RIE Receive interrupt enable 6 1 RBUIE Receive buffer unavailable interrupt enable 7 1 RPSIE Receive process stopped interrupt enable 8 1 RWTIE Receive watchdog timeout interrupt enable 9 1 ETIE Early transmit interrupt enable 10 1 FBEIE Fatal bus error interrupt enable 13 1 ERIE Early receive interrupt enable 14 1 AISE Abnormal interrupt summary enable 15 1 NISE Normal interrupt summary enable 16 1 DMAMFBOCR DMAMFBOCR Ethernet DMA missed frame and buffer overflow counter register 0x20 0x20 read-write 0x00000000 MFC Missed frames by the controller 0 16 OMFC Overflow bit for missed frame counter 16 1 MFA Missed frames by the application 17 11 OFOC Overflow bit for FIFO overflow counter 28 1 DMARSWTR DMARSWTR Ethernet DMA receive status watchdog timer register 0x24 0x20 read-write 0x00000000 RSWTC Receive status watchdog timer count 0 8 0255 DMACHTDR DMACHTDR Ethernet DMA current host transmit descriptor register 0x48 0x20 read-only 0x00000000 HTDAP Host transmit descriptor address pointer 0 32 DMACHRDR DMACHRDR Ethernet DMA current host receive descriptor register 0x4C 0x20 read-only 0x00000000 HRDAP Host receive descriptor address pointer 0 32 DMACHTBAR DMACHTBAR Ethernet DMA current host transmit buffer address register 0x50 0x20 read-only 0x00000000 HTBAP Host transmit buffer address pointer 0 32 DMACHRBAR DMACHRBAR Ethernet DMA current host receive buffer address register 0x54 0x20 read-only 0x00000000 HRBAP Host receive buffer address pointer 0 32 CRC Cryptographic processor CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data Register 0 32 04294967295 IDR IDR Independent Data register 0x4 0x20 read-write 0x00000000 IDR Independent Data register 0 8 0255 CR CR Control register 0x8 0x20 write-only 0x00000000 RESET Control regidter 0 1 RESETWwriteResetResets the CRC calculation unit and sets the data register to 0xFFFF FFFF1 OTG_FS_GLOBAL USB on the go full speed USB_OTG_FS 0x50000000 0x0 0x400 registers OTG_FS_WKUP USB On-The-Go FS Wakeup through EXTI line interrupt 42 OTG_FS_WKUP USB On-The-Go FS Wakeup through EXTI line interrupt 42 OTG_FS USB On The Go FS global interrupt 67 OTG_FS USB On The Go FS global interrupt 67 GOTGCTL GOTGCTL OTG_FS control and status register (OTG_FS_GOTGCTL) 0x0 0x20 0x00000800 SRQSCS Session request success 0 1 read-only SRQ Session request 1 1 read-write HNGSCS Host negotiation success 8 1 read-only HNPRQ HNP request 9 1 read-write HSHNPEN Host set HNP enable 10 1 read-write DHNPEN Device HNP enabled 11 1 read-write CIDSTS Connector ID status 16 1 read-only DBCT Long/short debounce time 17 1 read-only ASVLD A-session valid 18 1 read-only BSVLD B-session valid 19 1 read-only GOTGINT GOTGINT OTG_FS interrupt register (OTG_FS_GOTGINT) 0x4 0x20 read-write 0x00000000 SEDET Session end detected 2 1 SRSSCHG Session request success status change 8 1 HNSSCHG Host negotiation success status change 9 1 HNGDET Host negotiation detected 17 1 ADTOCHG A-device timeout change 18 1 DBCDNE Debounce done 19 1 GAHBCFG GAHBCFG OTG_FS AHB configuration register (OTG_FS_GAHBCFG) 0x8 0x20 read-write 0x00000000 GINT Global interrupt mask 0 1 TXFELVL TxFIFO empty level 7 1 PTXFELVL Periodic TxFIFO empty level 8 1 GUSBCFG GUSBCFG OTG_FS USB configuration register (OTG_FS_GUSBCFG) 0xC 0x20 0x00000A00 TOCAL FS timeout calibration 0 3 read-write PHYSEL Full Speed serial transceiver select 6 1 write-only SRPCAP SRP-capable 8 1 read-write HNPCAP HNP-capable 9 1 read-write TRDT USB turnaround time 10 4 read-write FHMOD Force host mode 29 1 read-write FDMOD Force device mode 30 1 read-write CTXPKT Corrupt Tx packet 31 1 read-write GRSTCTL GRSTCTL OTG_FS reset register (OTG_FS_GRSTCTL) 0x10 0x20 0x20000000 CSRST Core soft reset 0 1 read-write HSRST HCLK soft reset 1 1 read-write FCRST Host frame counter reset 2 1 read-write RXFFLSH RxFIFO flush 4 1 read-write TXFFLSH TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write AHBIDL AHB master idle 31 1 read-only GINTSTS GINTSTS OTG_FS core interrupt register (OTG_FS_GINTSTS) 0x14 0x20 0x04000020 CMOD Current mode of operation 0 1 read-only MMIS Mode mismatch interrupt 1 1 read-write OTGINT OTG interrupt 2 1 read-only SOF Start of frame 3 1 read-write RXFLVL RxFIFO non-empty 4 1 read-only NPTXFE Non-periodic TxFIFO empty 5 1 read-only GINAKEFF Global IN non-periodic NAK effective 6 1 read-only GOUTNAKEFF Global OUT NAK effective 7 1 read-only ESUSP Early suspend 10 1 read-write USBSUSP USB suspend 11 1 read-write USBRST USB reset 12 1 read-write ENUMDNE Enumeration done 13 1 read-write ISOODRP Isochronous OUT packet dropped interrupt 14 1 read-write EOPF End of periodic frame interrupt 15 1 read-write IEPINT IN endpoint interrupt 18 1 read-only OEPINT OUT endpoint interrupt 19 1 read-only IISOIXFR Incomplete isochronous IN transfer 20 1 read-write IPXFR_INCOMPISOOUT Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) 21 1 read-write HPRTINT Host port interrupt 24 1 read-only HCINT Host channels interrupt 25 1 read-only PTXFE Periodic TxFIFO empty 26 1 read-only CIDSCHG Connector ID status change 28 1 read-write DISCINT Disconnect detected interrupt 29 1 read-write SRQINT Session request/new session detected interrupt 30 1 read-write WKUPINT Resume/remote wakeup detected interrupt 31 1 read-write GINTMSK GINTMSK OTG_FS interrupt mask register (OTG_FS_GINTMSK) 0x18 0x20 0x00000000 MMISM Mode mismatch interrupt mask 1 1 read-write OTGINT OTG interrupt mask 2 1 read-write SOFM Start of frame mask 3 1 read-write RXFLVLM Receive FIFO non-empty mask 4 1 read-write NPTXFEM Non-periodic TxFIFO empty mask 5 1 read-write GINAKEFFM Global non-periodic IN NAK effective mask 6 1 read-write GONAKEFFM Global OUT NAK effective mask 7 1 read-write ESUSPM Early suspend mask 10 1 read-write USBSUSPM USB suspend mask 11 1 read-write USBRST USB reset mask 12 1 read-write ENUMDNEM Enumeration done mask 13 1 read-write ISOODRPM Isochronous OUT packet dropped interrupt mask 14 1 read-write EOPFM End of periodic frame interrupt mask 15 1 read-write EPMISM Endpoint mismatch interrupt mask 17 1 read-write IEPINT IN endpoints interrupt mask 18 1 read-write OEPINT OUT endpoints interrupt mask 19 1 read-write IISOIXFRM Incomplete isochronous IN transfer mask 20 1 read-write IPXFRM_IISOOXFRM Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) 21 1 read-write PRTIM Host port interrupt mask 24 1 read-only HCIM Host channels interrupt mask 25 1 read-write PTXFEM Periodic TxFIFO empty mask 26 1 read-write CIDSCHGM Connector ID status change mask 28 1 read-write DISCINT Disconnect detected interrupt mask 29 1 read-write SRQIM Session request/new session detected interrupt mask 30 1 read-write WUIM Resume/remote wakeup detected interrupt mask 31 1 read-write GRXSTSR_Device GRXSTSR_Device OTG_FS Receive status debug read(Device mode) 0x1C 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 FRMNUM Frame number 21 4 GRXSTSR_Host GRXSTSR_Host OTG_FS Receive status debug read(Hostmode) FS_GRXSTSR_Device 0x1C 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 FRMNUM Frame number 21 4 GRXFSIZ GRXFSIZ OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) 0x24 0x20 read-write 0x00000200 RXFD RxFIFO depth 0 16 DIEPTXF0 DIEPTXF0 OTG_FS non-periodic transmit FIFO size register (Device mode) 0x28 0x20 read-write 0x00000200 TX0FSA Endpoint 0 transmit RAM start address 0 16 TX0FD Endpoint 0 TxFIFO depth 16 16 HNPTXFSIZ HNPTXFSIZ OTG_FS non-periodic transmit FIFO size register (Host mode) DIEPTXF0 0x28 0x20 read-write 0x00000200 NPTXFSA Non-periodic transmit RAM start address 0 16 NPTXFD Non-periodic TxFIFO depth 16 16 GNPTXSTS GNPTXSTS OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) 0x2C 0x20 read-only 0x00080200 NPTXFSAV Non-periodic TxFIFO space available 0 16 NPTQXSAV Non-periodic transmit request queue space available 16 8 NPTXQTOP Top of the non-periodic transmit request queue 24 7 GCCFG GCCFG OTG_FS general core configuration register (OTG_FS_GCCFG) 0x38 0x20 read-write 0x00000000 PWRDWN Power down 16 1 VBUSASEN Enable the VBUS sensing device 18 1 VBUSBSEN Enable the VBUS sensing device 19 1 SOFOUTEN SOF output enable 20 1 CID CID core ID register 0x3C 0x20 read-write 0x00001000 PRODUCT_ID Product ID field 0 32 HPTXFSIZ HPTXFSIZ OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) 0x100 0x20 read-write 0x02000600 PTXSA Host periodic TxFIFO start address 0 16 PTXFSIZ Host periodic TxFIFO depth 16 16 30x41,2,3DIEPTXF%s DIEPTXF1 OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) 0x104 0x20 read-write 0x02000400 INEPTXSA IN endpoint FIFO2 transmit RAM start address 0 16 INEPTXFD IN endpoint TxFIFO depth 16 16 GRXSTSP_DeviceOTG status read and pop (device mode)3232read-only0STSPHSTStatus phase start271 FRMNUMFrame number214 PKTSTSPacket status174 DPIDData PID152 BCNTByte count411 EPNUMEndpoint number04 GRXSTSP_HostOTG status read and pop (host mode)GRXSTSP_Device3232read-only0PKTSTSPacket status174 DPIDData PID152 BCNTByte count411 CHNUMChannel number04 OTG_FS_HOST USB on the go full speed USB_OTG_FS 0x50000400 0x0 0x400 registers HCFG HCFG OTG_FS host configuration register (OTG_FS_HCFG) 0x0 0x20 0x00000000 FSLSPCS FS/LS PHY clock select 0 2 read-write FSLSS FS- and LS-only support 2 1 read-only HFIR HFIR OTG_FS Host frame interval register 0x4 0x20 read-write 0x0000EA60 FRIVL Frame interval 0 16 HFNUM HFNUM OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) 0x8 0x20 read-only 0x00003FFF FRNUM Frame number 0 16 FTREM Frame time remaining 16 16 HPTXSTS HPTXSTS OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) 0x10 0x20 0x00080100 PTXFSAVL Periodic transmit data FIFO space available 0 16 read-write PTXQSAV Periodic transmit request queue space available 16 8 read-only PTXQTOP Top of the periodic transmit request queue 24 8 read-only HAINT HAINT OTG_FS Host all channels interrupt register 0x14 0x20 read-only 0x00000000 HAINT Channel interrupts 0 16 HAINTMSK HAINTMSK OTG_FS host all channels interrupt mask register 0x18 0x20 read-write 0x00000000 HAINTM Channel interrupt mask 0 16 HPRT HPRT OTG_FS host port control and status register (OTG_FS_HPRT) 0x40 0x20 0x00000000 PCSTS Port connect status 0 1 read-only PCDET Port connect detected 1 1 read-write PENA Port enable 2 1 read-write PENCHNG Port enable/disable change 3 1 read-write POCA Port overcurrent active 4 1 read-only POCCHNG Port overcurrent change 5 1 read-write PRES Port resume 6 1 read-write PSUSP Port suspend 7 1 read-write PRST Port reset 8 1 read-write PLSTS Port line status 10 2 read-only PPWR Port power 12 1 read-write PTCTL Port test control 13 4 read-write PSPD Port speed 17 2 read-only HCCHAR0 HCCHAR0 OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) 0x100 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR1 HCCHAR1 OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1) 0x120 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR2 HCCHAR2 OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2) 0x140 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR3 HCCHAR3 OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3) 0x160 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR4 HCCHAR4 OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4) 0x180 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR5 HCCHAR5 OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5) 0x1A0 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR6 HCCHAR6 OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6) 0x1C0 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR7 HCCHAR7 OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7) 0x1E0 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCINT0 HCINT0 OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) 0x108 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT1 HCINT1 OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1) 0x128 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT2 HCINT2 OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2) 0x148 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT3 HCINT3 OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3) 0x168 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT4 HCINT4 OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4) 0x188 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT5 HCINT5 OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5) 0x1A8 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT6 HCINT6 OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6) 0x1C8 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT7 HCINT7 OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7) 0x1E8 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINTMSK0 HCINTMSK0 OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) 0x10C 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK1 HCINTMSK1 OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1) 0x12C 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK2 HCINTMSK2 OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2) 0x14C 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK3 HCINTMSK3 OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3) 0x16C 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK4 HCINTMSK4 OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4) 0x18C 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK5 HCINTMSK5 OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5) 0x1AC 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK6 HCINTMSK6 OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6) 0x1CC 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK7 HCINTMSK7 OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7) 0x1EC 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCTSIZ0 HCTSIZ0 OTG_FS host channel-0 transfer size register 0x110 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ1 HCTSIZ1 OTG_FS host channel-1 transfer size register 0x130 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ2 HCTSIZ2 OTG_FS host channel-2 transfer size register 0x150 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ3 HCTSIZ3 OTG_FS host channel-3 transfer size register 0x170 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ4 HCTSIZ4 OTG_FS host channel-x transfer size register 0x190 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ5 HCTSIZ5 OTG_FS host channel-5 transfer size register 0x1B0 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ6 HCTSIZ6 OTG_FS host channel-6 transfer size register 0x1D0 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ7 HCTSIZ7 OTG_FS host channel-7 transfer size register 0x1F0 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 OTG_FS_DEVICE USB on the go full speed USB_OTG_FS 0x50000800 0x0 0x400 registers DCFG DCFG OTG_FS device configuration register (OTG_FS_DCFG) 0x0 0x20 read-write 0x02200000 DSPD Device speed 0 2 NZLSOHSK Non-zero-length status OUT handshake 2 1 DAD Device address 4 7 PFIVL Periodic frame interval 11 2 DCTL DCTL OTG_FS device control register (OTG_FS_DCTL) 0x4 0x20 0x00000000 RWUSIG Remote wakeup signaling 0 1 read-write SDIS Soft disconnect 1 1 read-write GINSTS Global IN NAK status 2 1 read-only GONSTS Global OUT NAK status 3 1 read-only TCTL Test control 4 3 read-write SGINAK Set global IN NAK 7 1 read-write CGINAK Clear global IN NAK 8 1 read-write SGONAK Set global OUT NAK 9 1 read-write CGONAK Clear global OUT NAK 10 1 read-write POPRGDNE Power-on programming done 11 1 read-write DSTS DSTS OTG_FS device status register (OTG_FS_DSTS) 0x8 0x20 read-only 0x00000010 SUSPSTS Suspend status 0 1 ENUMSPD Enumerated speed 1 2 EERR Erratic error 3 1 FNSOF Frame number of the received SOF 8 14 DIEPMSK DIEPMSK OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) 0x10 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 TOM Timeout condition mask (Non-isochronous endpoints) 3 1 ITTXFEMSK IN token received when TxFIFO empty mask 4 1 INEPNMM IN token received with EP mismatch mask 5 1 INEPNEM IN endpoint NAK effective mask 6 1 DOEPMSK DOEPMSK OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) 0x14 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 STUPM SETUP phase done mask 3 1 OTEPDM OUT token received when endpoint disabled mask 4 1 DAINT DAINT OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) 0x18 0x20 read-only 0x00000000 IEPINT IN endpoint interrupt bits 0 16 OEPINT OUT endpoint interrupt bits 16 16 DAINTMSK DAINTMSK OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) 0x1C 0x20 read-write 0x00000000 IEPM IN EP interrupt mask bits 0 16 OEPM OUT EP interrupt mask bits 16 16 DVBUSDIS DVBUSDIS OTG_FS device VBUS discharge time register 0x28 0x20 read-write 0x000017D7 VBUSDT Device VBUS discharge time 0 16 DVBUSPULSE DVBUSPULSE OTG_FS device VBUS pulsing time register 0x2C 0x20 read-write 0x000005B8 DVBUSP Device VBUS pulsing time 0 12 DIEPEMPMSK DIEPEMPMSK OTG_FS device IN endpoint FIFO empty interrupt mask register 0x34 0x20 read-write 0x00000000 INEPTXFEM IN EP Tx FIFO empty interrupt mask bits 0 16 DIEPCTL0 DIEPCTL0 OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) 0x100 0x20 0x00000000 MPSIZ Maximum packet size 0 2 read-write USBAEP USB active endpoint 15 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-only STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPDIS Endpoint disable 30 1 read-only EPENA Endpoint enable 31 1 read-write 30x201,2,3DIEPCTL%s DIEPCTL1 OTG device endpoint-1 control register 0x120 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM_SD1PID SODDFRM/SD1PID 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only TXFNUM TXFNUM 22 4 read-write STALL STALL 21 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write DOEPCTL0 DOEPCTL0 device endpoint-0 control register 0x300 0x20 0x00008000 EPENA EPENA 31 1 write-only EPDIS EPDIS 30 1 read-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only STALL STALL 21 1 read-write SNPM SNPM 20 1 read-write EPTYP EPTYP 18 2 read-only NAKSTS NAKSTS 17 1 read-only USBAEP USBAEP 15 1 read-only MPSIZ MPSIZ 0 2 read-only 30x201,2,3DOEPCTL%s DOEPCTL1 device endpoint-1 control register 0x320 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM SODDFRM 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only STALL STALL 21 1 read-write SNPM SNPM 20 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write DIEPINT0 DIEPINT0 device endpoint-x interrupt register 0x108 0x20 0x00000080 TXFE TXFE 7 1 read-only INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write EPDISD EPDISD 1 1 read-write XFRC XFRC 0 1 read-write DIEPINT1 DIEPINT1 device endpoint-1 interrupt register 0x128 0x20 0x00000080 TXFE TXFE 7 1 read-only INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write EPDISD EPDISD 1 1 read-write XFRC XFRC 0 1 read-write DIEPINT2 DIEPINT2 device endpoint-2 interrupt register 0x148 0x20 0x00000080 TXFE TXFE 7 1 read-only INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write EPDISD EPDISD 1 1 read-write XFRC XFRC 0 1 read-write DIEPINT3 DIEPINT3 device endpoint-3 interrupt register 0x168 0x20 0x00000080 TXFE TXFE 7 1 read-only INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write EPDISD EPDISD 1 1 read-write XFRC XFRC 0 1 read-write DOEPINT0 DOEPINT0 device endpoint-0 interrupt register 0x308 0x20 read-write 0x00000080 B2BSTUP B2BSTUP 6 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 EPDISD EPDISD 1 1 XFRC XFRC 0 1 DOEPINT1 DOEPINT1 device endpoint-1 interrupt register 0x328 0x20 read-write 0x00000080 B2BSTUP B2BSTUP 6 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 EPDISD EPDISD 1 1 XFRC XFRC 0 1 DOEPINT2 DOEPINT2 device endpoint-2 interrupt register 0x348 0x20 read-write 0x00000080 B2BSTUP B2BSTUP 6 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 EPDISD EPDISD 1 1 XFRC XFRC 0 1 DOEPINT3 DOEPINT3 device endpoint-3 interrupt register 0x368 0x20 read-write 0x00000080 B2BSTUP B2BSTUP 6 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 EPDISD EPDISD 1 1 XFRC XFRC 0 1 DIEPTSIZ0 DIEPTSIZ0 device endpoint-0 transfer size register 0x110 0x20 read-write 0x00000000 PKTCNT Packet count 19 2 XFRSIZ Transfer size 0 7 DOEPTSIZ0 DOEPTSIZ0 device OUT endpoint-0 transfer size register 0x310 0x20 read-write 0x00000000 STUPCNT SETUP packet count 29 2 PKTCNT Packet count 19 1 XFRSIZ Transfer size 0 7 DIEPTSIZ1 DIEPTSIZ1 device endpoint-1 transfer size register 0x130 0x20 read-write 0x00000000 MCNT Multi count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DIEPTSIZ2 DIEPTSIZ2 device endpoint-2 transfer size register 0x150 0x20 read-write 0x00000000 MCNT Multi count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DIEPTSIZ3 DIEPTSIZ3 device endpoint-3 transfer size register 0x170 0x20 read-write 0x00000000 MCNT Multi count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DTXFSTS0 DTXFSTS0 OTG_FS device IN endpoint transmit FIFO status register 0x118 0x20 read-only 0x00000000 INEPTFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS1 DTXFSTS1 OTG_FS device IN endpoint transmit FIFO status register 0x138 0x20 read-only 0x00000000 INEPTFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS2 DTXFSTS2 OTG_FS device IN endpoint transmit FIFO status register 0x158 0x20 read-only 0x00000000 INEPTFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS3 DTXFSTS3 OTG_FS device IN endpoint transmit FIFO status register 0x178 0x20 read-only 0x00000000 INEPTFSAV IN endpoint TxFIFO space available 0 16 DOEPTSIZ1 DOEPTSIZ1 device OUT endpoint-1 transfer size register 0x330 0x20 read-write 0x00000000 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DOEPTSIZ2 DOEPTSIZ2 device OUT endpoint-2 transfer size register 0x350 0x20 read-write 0x00000000 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DOEPTSIZ3 DOEPTSIZ3 device OUT endpoint-3 transfer size register 0x370 0x20 read-write 0x00000000 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 OTG_FS_PWRCLK USB on the go full speed USB_OTG_FS 0x50000E00 0x0 0x400 registers PCGCCTL PCGCCTL OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) 0x0 0x20 read-write 0x00000000 STPPCLK Stop PHY clock 0 1 GATEHCLK Gate HCLK 1 1 PHYSUSP PHY Suspended 4 1 CAN1 Controller area network CAN 0x40006400 0x0 0x400 registers CAN1_TX CAN1 TX interrupts 19 CAN1_TX CAN1 TX interrupts 19 CAN1_RX0 CAN1 RX0 interrupts 20 CAN1_RX0 CAN1 RX0 interrupts 20 CAN1_RX1 CAN1 RX1 interrupts 21 CAN1_RX1 CAN1 RX1 interrupts 21 CAN1_SCE CAN1 SCE interrupt 22 CAN1_SCE CAN1 SCE interrupt 22 30x100,1,2TX%sCAN Transmit cluster0x180 TIR TI0R TX mailbox identifier register 0x0 0x20 read-write 0x00000000 STID STID 21 11 EXID EXID 3 18 IDE IDE 2 1 IDEread-writeStandardStandard identifier0ExtendedExtended identifier1 RTR RTR 1 1 RTRread-writeDataData frame0RemoteRemote frame1 TXRQ TXRQ 0 1 TDTR TDT0R mailbox data length control and time stamp register 0x4 0x20 read-write 0x00000000 TIME TIME 16 16 TGT TGT 8 1 DLC DLC 0 4 08 TDLR TDL0R mailbox data low register 0x8 0x20 read-write 0x00000000 DATA3 DATA3 24 8 DATA2 DATA2 16 8 DATA1 DATA1 8 8 DATA0 DATA0 0 8 TDHR TDH0R mailbox data high register 0xc 0x20 read-write 0x00000000 DATA7 DATA7 24 8 DATA6 DATA6 16 8 DATA5 DATA5 8 8 DATA4 DATA4 0 8 20x100,1RX%sCAN Receive cluster0x1b0 RIR RI0R receive FIFO mailbox identifier register 0x0 0x20 read-only 0x00000000 STID STID 21 11 EXID EXID 3 18 IDE IDE 2 1 IDEread-writeStandardStandard identifier0ExtendedExtended identifier1 RTR RTR 1 1 RTRread-writeDataData frame0RemoteRemote frame1 RDTR RDT0R mailbox data high register 0x4 0x20 read-only 0x00000000 TIME TIME 16 16 FMI FMI 8 8 DLC DLC 0 4 08 RDLR RDL0R mailbox data high register 0x8 0x20 read-only 0x00000000 DATA3 DATA3 24 8 DATA2 DATA2 16 8 DATA1 DATA1 8 8 DATA0 DATA0 0 8 RDHR RDH0R receive FIFO mailbox data high register 0xc 0x20 read-only 0x00000000 DATA7 DATA7 24 8 DATA6 DATA6 16 8 DATA5 DATA5 8 8 DATA4 DATA4 0 8 280x80,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27FB%sCAN Filter Bank cluster0x240 FR1 F0R1 Filter bank 0 register 1 0x0 0x20 read-write 0x00000000 FBFilter bits032 FR2 F0R2 Filter bank 0 register 2 0x4 0x20 read-write 0x00000000 FBFilter bits032 MCR MCR master control register 0x0 0x20 read-write 0x00010002 DBF DBF 16 1 RESET RESET 15 1 TTCM TTCM 7 1 ABOM ABOM 6 1 AWUM AWUM 5 1 NART NART 4 1 RFLM RFLM 3 1 TXFP TXFP 2 1 SLEEP SLEEP 1 1 INRQ INRQ 0 1 MSR MSR master status register 0x4 0x20 0x00000C02 RX RX 11 1 read-only SAMP SAMP 10 1 read-only RXM RXM 9 1 read-only TXM TXM 8 1 read-only SLAKI SLAKI 4 1 read-write WKUI WKUI 3 1 read-write ERRI ERRI 2 1 read-write SLAK SLAK 1 1 read-only INAK INAK 0 1 read-only TSR TSR transmit status register 0x8 0x20 0x1C000000 LOW2 Lowest priority flag for mailbox 2 31 1 read-only LOW1 Lowest priority flag for mailbox 1 30 1 read-only LOW0 Lowest priority flag for mailbox 0 29 1 read-only TME2 Lowest priority flag for mailbox 2 28 1 read-only TME1 Lowest priority flag for mailbox 1 27 1 read-only TME0 Lowest priority flag for mailbox 0 26 1 read-only CODE CODE 24 2 read-only ABRQ2 ABRQ2 23 1 read-write TERR2 TERR2 19 1 read-write ALST2 ALST2 18 1 read-write TXOK2 TXOK2 17 1 read-write RQCP2 RQCP2 16 1 read-write ABRQ1 ABRQ1 15 1 read-write TERR1 TERR1 11 1 read-write ALST1 ALST1 10 1 read-write TXOK1 TXOK1 9 1 read-write RQCP1 RQCP1 8 1 read-write ABRQ0 ABRQ0 7 1 read-write TERR0 TERR0 3 1 read-write ALST0 ALST0 2 1 read-write TXOK0 TXOK0 1 1 read-write RQCP0 RQCP0 0 1 read-write 20x40,1RF%sR RF0R receive FIFO %s register 0xC 0x20 0x00000000 RFOM RFOM0 5 1 read-write RFOM0WwriteReleaseSet by software to release the output mailbox of the FIFO1 FOVR FOVR0 4 1 read-write FOVR0RreadNoOverrunNo FIFO x overrun0OverrunFIFO x overrun1 FOVR0WwriteClearClear flag1 FULL FULL0 3 1 read-write FULL0RreadNotFullFIFO x is not full0FullFIFO x is full1 FULL0WwriteClearClear flag1 FMP FMP0 0 2 read-only IER IER interrupt enable register 0x14 0x20 read-write 0x00000000 SLKIE SLKIE 17 1 SLKIEread-writeDisabledNo interrupt when SLAKI bit is set0EnabledInterrupt generated when SLAKI bit is set1 WKUIE WKUIE 16 1 WKUIEread-writeDisabledNo interrupt when WKUI is set0EnabledInterrupt generated when WKUI bit is set1 ERRIE ERRIE 15 1 ERRIEread-writeDisabledNo interrupt will be generated when an error condition is pending in the CAN_ESR0EnabledAn interrupt will be generation when an error condition is pending in the CAN_ESR1 LECIE LECIE 11 1 LECIEread-writeDisabledERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection0EnabledERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection1 BOFIE BOFIE 10 1 BOFIEread-writeDisabledERRI bit will not be set when BOFF is set0EnabledERRI bit will be set when BOFF is set1 EPVIE EPVIE 9 1 EPVIEread-writeDisabledERRI bit will not be set when EPVF is set0EnabledERRI bit will be set when EPVF is set1 EWGIE EWGIE 8 1 EWGIEread-writeDisabledERRI bit will not be set when EWGF is set0EnabledERRI bit will be set when EWGF is set1 FOVIE1 FOVIE1 6 1 FOVIE1read-writeDisabledNo interrupt when FOVR is set0EnabledInterrupt generation when FOVR is set1 FFIE1 FFIE1 5 1 FFIE1read-writeDisabledNo interrupt when FULL bit is set0EnabledInterrupt generated when FULL bit is set1 FMPIE1 FMPIE1 4 1 FMPIE1read-writeDisabledNo interrupt generated when state of FMP[1:0] bits are not 00b0EnabledInterrupt generated when state of FMP[1:0] bits are not 00b1 FOVIE0 FOVIE0 3 1 FOVIE0read-writeDisabledNo interrupt when FOVR bit is set0EnabledInterrupt generated when FOVR bit is set1 FFIE0 FFIE0 2 1 FFIE0read-writeDisabledNo interrupt when FULL bit is set0EnabledInterrupt generated when FULL bit is set1 FMPIE0 FMPIE0 1 1 FMPIE0read-writeDisabledNo interrupt generated when state of FMP[1:0] bits are not 000EnabledInterrupt generated when state of FMP[1:0] bits are not 00b1 TMEIE TMEIE 0 1 TMEIEread-writeDisabledNo interrupt when RQCPx bit is set0EnabledInterrupt generated when RQCPx bit is set1 ESR ESR interrupt enable register 0x18 0x20 0x00000000 REC REC 24 8 read-only TEC TEC 16 8 read-only LEC LEC 4 3 read-write LECread-writeNoErrorNo Error0StuffStuff Error1FormForm Error2AckAcknowledgment Error3BitRecessiveBit recessive Error4BitDominantBit dominant Error5CrcCRC Error6CustomSet by software7 BOFF BOFF 2 1 read-only EPVF EPVF 1 1 read-only EWGF EWGF 0 1 read-only BTR BTR bit timing register 0x1C 0x20 read-write 0x00000000 SILM SILM 31 1 SILMread-writeNormalNormal operation0SilentSilent Mode1 LBKM LBKM 30 1 LBKMread-writeDisabledLoop Back Mode disabled0EnabledLoop Back Mode enabled1 SJW SJW 24 2 TS2 TS2 20 3 TS1 TS1 16 4 BRP BRP 0 10 FMR FMR filter master register 0x200 0x20 read-write 0x2A1C0E01 CAN2SB CAN2SB 8 6 FINIT FINIT 0 1 FM1R FM1R filter mode register 0x204 0x20 read-write 0x00000000 FBM0 Filter mode 0 1 FBM1 Filter mode 1 1 FBM2 Filter mode 2 1 FBM3 Filter mode 3 1 FBM4 Filter mode 4 1 FBM5 Filter mode 5 1 FBM6 Filter mode 6 1 FBM7 Filter mode 7 1 FBM8 Filter mode 8 1 FBM9 Filter mode 9 1 FBM10 Filter mode 10 1 FBM11 Filter mode 11 1 FBM12 Filter mode 12 1 FBM13 Filter mode 13 1 FBM14 Filter mode 14 1 FBM15 Filter mode 15 1 FBM16 Filter mode 16 1 FBM17 Filter mode 17 1 FBM18 Filter mode 18 1 FBM19 Filter mode 19 1 FBM20 Filter mode 20 1 FBM21 Filter mode 21 1 FBM22 Filter mode 22 1 FBM23 Filter mode 23 1 FBM24 Filter mode 24 1 FBM25 Filter mode 25 1 FBM26 Filter mode 26 1 FBM27 Filter mode 27 1 FS1R FS1R filter scale register 0x20C 0x20 read-write 0x00000000 FSC0 Filter scale configuration 0 1 FSC1 Filter scale configuration 1 1 FSC2 Filter scale configuration 2 1 FSC3 Filter scale configuration 3 1 FSC4 Filter scale configuration 4 1 FSC5 Filter scale configuration 5 1 FSC6 Filter scale configuration 6 1 FSC7 Filter scale configuration 7 1 FSC8 Filter scale configuration 8 1 FSC9 Filter scale configuration 9 1 FSC10 Filter scale configuration 10 1 FSC11 Filter scale configuration 11 1 FSC12 Filter scale configuration 12 1 FSC13 Filter scale configuration 13 1 FSC14 Filter scale configuration 14 1 FSC15 Filter scale configuration 15 1 FSC16 Filter scale configuration 16 1 FSC17 Filter scale configuration 17 1 FSC18 Filter scale configuration 18 1 FSC19 Filter scale configuration 19 1 FSC20 Filter scale configuration 20 1 FSC21 Filter scale configuration 21 1 FSC22 Filter scale configuration 22 1 FSC23 Filter scale configuration 23 1 FSC24 Filter scale configuration 24 1 FSC25 Filter scale configuration 25 1 FSC26 Filter scale configuration 26 1 FSC27 Filter scale configuration 27 1 FFA1R FFA1R filter FIFO assignment register 0x214 0x20 read-write 0x00000000 FFA0 Filter FIFO assignment for filter 0 0 1 FFA1 Filter FIFO assignment for filter 1 1 1 FFA2 Filter FIFO assignment for filter 2 2 1 FFA3 Filter FIFO assignment for filter 3 3 1 FFA4 Filter FIFO assignment for filter 4 4 1 FFA5 Filter FIFO assignment for filter 5 5 1 FFA6 Filter FIFO assignment for filter 6 6 1 FFA7 Filter FIFO assignment for filter 7 7 1 FFA8 Filter FIFO assignment for filter 8 8 1 FFA9 Filter FIFO assignment for filter 9 9 1 FFA10 Filter FIFO assignment for filter 10 10 1 FFA11 Filter FIFO assignment for filter 11 11 1 FFA12 Filter FIFO assignment for filter 12 12 1 FFA13 Filter FIFO assignment for filter 13 13 1 FFA14 Filter FIFO assignment for filter 14 14 1 FFA15 Filter FIFO assignment for filter 15 15 1 FFA16 Filter FIFO assignment for filter 16 16 1 FFA17 Filter FIFO assignment for filter 17 17 1 FFA18 Filter FIFO assignment for filter 18 18 1 FFA19 Filter FIFO assignment for filter 19 19 1 FFA20 Filter FIFO assignment for filter 20 20 1 FFA21 Filter FIFO assignment for filter 21 21 1 FFA22 Filter FIFO assignment for filter 22 22 1 FFA23 Filter FIFO assignment for filter 23 23 1 FFA24 Filter FIFO assignment for filter 24 24 1 FFA25 Filter FIFO assignment for filter 25 25 1 FFA26 Filter FIFO assignment for filter 26 26 1 FFA27 Filter FIFO assignment for filter 27 27 1 FA1R FA1R filter activation register 0x21C 0x20 read-write 0x00000000 FACT0 Filter active 0 1 FACT1 Filter active 1 1 FACT2 Filter active 2 1 FACT3 Filter active 3 1 FACT4 Filter active 4 1 FACT5 Filter active 5 1 FACT6 Filter active 6 1 FACT7 Filter active 7 1 FACT8 Filter active 8 1 FACT9 Filter active 9 1 FACT10 Filter active 10 1 FACT11 Filter active 11 1 FACT12 Filter active 12 1 FACT13 Filter active 13 1 FACT14 Filter active 14 1 FACT15 Filter active 15 1 FACT16 Filter active 16 1 FACT17 Filter active 17 1 FACT18 Filter active 18 1 FACT19 Filter active 19 1 FACT20 Filter active 20 1 FACT21 Filter active 21 1 FACT22 Filter active 22 1 FACT23 Filter active 23 1 FACT24 Filter active 24 1 FACT25 Filter active 25 1 FACT26 Filter active 26 1 FACT27 Filter active 27 1 CAN2 0x40006800 CAN2_TX CAN2 TX interrupts 63 CAN2_TX CAN2 TX interrupts 63 CAN2_RX0 CAN2 RX0 interrupts 64 CAN2_RX0 CAN2 RX0 interrupts 64 CAN2_RX1 CAN2 RX1 interrupts 65 CAN2_RX1 CAN2 RX1 interrupts 65 CAN2_SCE CAN2 SCE interrupt 66 CAN2_SCE CAN2 SCE interrupt 66 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0x355 registers ISER0 ISER0 Interrupt Set-Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x4 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER2 ISER2 Interrupt Set-Enable Register 0x8 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x84 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER2 ICER2 Interrupt Clear-Enable Register 0x88 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x104 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR2 ISPR2 Interrupt Set-Pending Register 0x108 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x184 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR2 ICPR2 Interrupt Clear-Pending Register 0x188 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x200 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x204 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR2 IABR2 Interrupt Active Bit Register 0x208 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x300 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x304 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x308 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x30C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x310 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x314 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x318 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x31C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x320 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x324 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x328 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x32C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x330 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x334 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x338 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR15 IPR15 Interrupt Priority Register 0x33C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR16 IPR16 Interrupt Priority Register 0x340 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR17 IPR17 Interrupt Priority Register 0x344 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR18 IPR18 Interrupt Priority Register 0x348 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR19 IPR19 Interrupt Priority Register 0x34C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR20 IPR20 Interrupt Priority Register 0x350 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 FLASH FLASH FLASH 0x40023C00 0x0 0x400 registers FLASH Flash global interrupt 4 FLASH Flash global interrupt 4 ACR ACR Flash access control register 0x0 0x20 0x00000000 LATENCY Latency 0 4 read-write LATENCYread-writeWS00 wait states0WS11 wait states1WS22 wait states2WS33 wait states3WS44 wait states4WS55 wait states5WS66 wait states6WS77 wait states7WS88 wait states8WS99 wait states9WS1010 wait states10WS1111 wait states11WS1212 wait states12WS1313 wait states13WS1414 wait states14WS1515 wait states15 PRFTEN Prefetch enable 8 1 read-write PRFTENread-writeDisabledPrefetch is disabled0EnabledPrefetch is enabled1 ICEN Instruction cache enable 9 1 read-write ICENread-writeDisabledInstruction cache is disabled0EnabledInstruction cache is enabled1 DCEN Data cache enable 10 1 read-write DCENread-writeDisabledData cache is disabled0EnabledData cache is enabled1 ICRST Instruction cache reset 11 1 write-only ICRSTread-writeNotResetInstruction cache is not reset0ResetInstruction cache is reset1 DCRST Data cache reset 12 1 read-write DCRSTread-writeNotResetData cache is not reset0ResetData cache is reset1 KEYR KEYR Flash key register 0x4 0x20 write-only 0x00000000 KEY FPEC key 0 32 04294967295 OPTKEYR OPTKEYR Flash option key register 0x8 0x20 write-only 0x00000000 OPTKEY Option byte key 0 32 04294967295 SR SR Status register 0xC 0x20 0x00000000 EOP End of operation 0 1 read-write OPERR Operation error 1 1 read-write WRPERR Write protection error 4 1 read-write PGAERR Programming alignment error 5 1 read-write PGPERR Programming parallelism error 6 1 read-write PGSERR Programming sequence error 7 1 read-write BSY Busy 16 1 read-only CR CR Control register 0x10 0x20 read-write 0x80000000 PG Programming 0 1 PGread-writeProgramFlash programming activated1 SER Sector Erase 1 1 SERread-writeSectorEraseErase activated for selected sector1 MER Mass Erase of sectors 0 to 11 2 1 MERread-writeMassEraseErase activated for all user sectors1 SNB Sector number 3 5 011 PSIZE Program size 8 2 PSIZEread-writePSIZE8Program x80PSIZE16Program x161PSIZE32Program x322PSIZE64Program x643 MER1 Mass Erase of sectors 12 to 23 15 1 STRT Start 16 1 STRTread-writeStartTrigger an erase operation1 EOPIE End of operation interrupt enable 24 1 EOPIEread-writeDisabledEnd of operation interrupt disabled0EnabledEnd of operation interrupt enabled1 ERRIE Error interrupt enable 25 1 ERRIEread-writeDisabledError interrupt generation disabled0EnabledError interrupt generation enabled1 LOCK Lock 31 1 LOCKread-writeUnlockedFLASH_CR register is unlocked0LockedFLASH_CR register is locked1 OPTCR OPTCR Flash option control register 0x14 0x20 read-write 0x0FFFAAED OPTLOCK Option lock 0 1 OPTSTRT Option start 1 1 BOR_LEV BOR reset Level 2 2 WDG_SW WDG_SW User option bytes 5 1 nRST_STOP nRST_STOP User option bytes 6 1 nRST_STDBY nRST_STDBY User option bytes 7 1 RDP Read protect 8 8 nWRP Not write protect 16 12 OPTCR1 OPTCR1 Flash option control register 1 0x18 0x20 read-write 0x0FFF0000 nWRP Not write protect 16 12 EXTI External interrupt/event controller EXTI 0x40013C00 0x0 0x400 registers TAMP_STAMP Tamper and TimeStamp interrupts through the EXTI line 2 TAMP_STAMP Tamper and TimeStamp interrupts through the EXTI line 2 EXTI0 EXTI Line0 interrupt 6 EXTI0 EXTI Line0 interrupt 6 EXTI1 EXTI Line1 interrupt 7 EXTI1 EXTI Line1 interrupt 7 EXTI2 EXTI Line2 interrupt 8 EXTI2 EXTI Line2 interrupt 8 EXTI3 EXTI Line3 interrupt 9 EXTI3 EXTI Line3 interrupt 9 EXTI4 EXTI Line4 interrupt 10 EXTI4 EXTI Line4 interrupt 10 EXTI9_5 EXTI Line[9:5] interrupts 23 EXTI9_5 EXTI Line[9:5] interrupts 23 EXTI15_10 EXTI Line[15:10] interrupts 40 EXTI15_10 EXTI Line[15:10] interrupts 40 IMR IMR Interrupt mask register (EXTI_IMR) 0x0 0x20 read-write 0x00000000 MR0 Interrupt Mask on line 0 0 1 MR0read-writeMaskedInterrupt request line is masked0UnmaskedInterrupt request line is unmasked1 MR1 Interrupt Mask on line 1 1 1 MR2 Interrupt Mask on line 2 2 1 MR3 Interrupt Mask on line 3 3 1 MR4 Interrupt Mask on line 4 4 1 MR5 Interrupt Mask on line 5 5 1 MR6 Interrupt Mask on line 6 6 1 MR7 Interrupt Mask on line 7 7 1 MR8 Interrupt Mask on line 8 8 1 MR9 Interrupt Mask on line 9 9 1 MR10 Interrupt Mask on line 10 10 1 MR11 Interrupt Mask on line 11 11 1 MR12 Interrupt Mask on line 12 12 1 MR13 Interrupt Mask on line 13 13 1 MR14 Interrupt Mask on line 14 14 1 MR15 Interrupt Mask on line 15 15 1 MR16 Interrupt Mask on line 16 16 1 MR17 Interrupt Mask on line 17 17 1 MR18 Interrupt Mask on line 18 18 1 MR19 Interrupt Mask on line 19 19 1 MR20 Interrupt Mask on line 20 20 1 MR21 Interrupt Mask on line 21 21 1 MR22 Interrupt Mask on line 22 22 1 EMR EMR Event mask register (EXTI_EMR) 0x4 0x20 read-write 0x00000000 MR0 Event Mask on line 0 0 1 MR0read-writeMaskedInterrupt request line is masked0UnmaskedInterrupt request line is unmasked1 MR1 Event Mask on line 1 1 1 MR2 Event Mask on line 2 2 1 MR3 Event Mask on line 3 3 1 MR4 Event Mask on line 4 4 1 MR5 Event Mask on line 5 5 1 MR6 Event Mask on line 6 6 1 MR7 Event Mask on line 7 7 1 MR8 Event Mask on line 8 8 1 MR9 Event Mask on line 9 9 1 MR10 Event Mask on line 10 10 1 MR11 Event Mask on line 11 11 1 MR12 Event Mask on line 12 12 1 MR13 Event Mask on line 13 13 1 MR14 Event Mask on line 14 14 1 MR15 Event Mask on line 15 15 1 MR16 Event Mask on line 16 16 1 MR17 Event Mask on line 17 17 1 MR18 Event Mask on line 18 18 1 MR19 Event Mask on line 19 19 1 MR20 Event Mask on line 20 20 1 MR21 Event Mask on line 21 21 1 MR22 Event Mask on line 22 22 1 RTSR RTSR Rising Trigger selection register (EXTI_RTSR) 0x8 0x20 read-write 0x00000000 TR0 Rising trigger event configuration of line 0 0 1 TR0read-writeDisabledRising edge trigger is disabled0EnabledRising edge trigger is enabled1 TR1 Rising trigger event configuration of line 1 1 1 TR2 Rising trigger event configuration of line 2 2 1 TR3 Rising trigger event configuration of line 3 3 1 TR4 Rising trigger event configuration of line 4 4 1 TR5 Rising trigger event configuration of line 5 5 1 TR6 Rising trigger event configuration of line 6 6 1 TR7 Rising trigger event configuration of line 7 7 1 TR8 Rising trigger event configuration of line 8 8 1 TR9 Rising trigger event configuration of line 9 9 1 TR10 Rising trigger event configuration of line 10 10 1 TR11 Rising trigger event configuration of line 11 11 1 TR12 Rising trigger event configuration of line 12 12 1 TR13 Rising trigger event configuration of line 13 13 1 TR14 Rising trigger event configuration of line 14 14 1 TR15 Rising trigger event configuration of line 15 15 1 TR16 Rising trigger event configuration of line 16 16 1 TR17 Rising trigger event configuration of line 17 17 1 TR18 Rising trigger event configuration of line 18 18 1 TR19 Rising trigger event configuration of line 19 19 1 TR20 Rising trigger event configuration of line 20 20 1 TR21 Rising trigger event configuration of line 21 21 1 TR22 Rising trigger event configuration of line 22 22 1 FTSR FTSR Falling Trigger selection register (EXTI_FTSR) 0xC 0x20 read-write 0x00000000 TR0 Falling trigger event configuration of line 0 0 1 TR0read-writeDisabledFalling edge trigger is disabled0EnabledFalling edge trigger is enabled1 TR1 Falling trigger event configuration of line 1 1 1 TR2 Falling trigger event configuration of line 2 2 1 TR3 Falling trigger event configuration of line 3 3 1 TR4 Falling trigger event configuration of line 4 4 1 TR5 Falling trigger event configuration of line 5 5 1 TR6 Falling trigger event configuration of line 6 6 1 TR7 Falling trigger event configuration of line 7 7 1 TR8 Falling trigger event configuration of line 8 8 1 TR9 Falling trigger event configuration of line 9 9 1 TR10 Falling trigger event configuration of line 10 10 1 TR11 Falling trigger event configuration of line 11 11 1 TR12 Falling trigger event configuration of line 12 12 1 TR13 Falling trigger event configuration of line 13 13 1 TR14 Falling trigger event configuration of line 14 14 1 TR15 Falling trigger event configuration of line 15 15 1 TR16 Falling trigger event configuration of line 16 16 1 TR17 Falling trigger event configuration of line 17 17 1 TR18 Falling trigger event configuration of line 18 18 1 TR19 Falling trigger event configuration of line 19 19 1 TR20 Falling trigger event configuration of line 20 20 1 TR21 Falling trigger event configuration of line 21 21 1 TR22 Falling trigger event configuration of line 22 22 1 SWIER SWIER Software interrupt event register (EXTI_SWIER) 0x10 0x20 read-write 0x00000000 SWIER0 Software Interrupt on line 0 0 1 SWIER0WwritePendGenerates an interrupt request1 SWIER1 Software Interrupt on line 1 1 1 SWIER2 Software Interrupt on line 2 2 1 SWIER3 Software Interrupt on line 3 3 1 SWIER4 Software Interrupt on line 4 4 1 SWIER5 Software Interrupt on line 5 5 1 SWIER6 Software Interrupt on line 6 6 1 SWIER7 Software Interrupt on line 7 7 1 SWIER8 Software Interrupt on line 8 8 1 SWIER9 Software Interrupt on line 9 9 1 SWIER10 Software Interrupt on line 10 10 1 SWIER11 Software Interrupt on line 11 11 1 SWIER12 Software Interrupt on line 12 12 1 SWIER13 Software Interrupt on line 13 13 1 SWIER14 Software Interrupt on line 14 14 1 SWIER15 Software Interrupt on line 15 15 1 SWIER16 Software Interrupt on line 16 16 1 SWIER17 Software Interrupt on line 17 17 1 SWIER18 Software Interrupt on line 18 18 1 SWIER19 Software Interrupt on line 19 19 1 SWIER20 Software Interrupt on line 20 20 1 SWIER21 Software Interrupt on line 21 21 1 SWIER22 Software Interrupt on line 22 22 1 PR PR Pending register (EXTI_PR) 0x14 0x20 read-write 0x00000000 PR0 Pending bit 0 0 1 PR0RreadNotPendingNo trigger request occurred0PendingSelected trigger request occurred1 PR0WwriteClearClears pending bit1 PR1 Pending bit 1 1 1 PR2 Pending bit 2 2 1 PR3 Pending bit 3 3 1 PR4 Pending bit 4 4 1 PR5 Pending bit 5 5 1 PR6 Pending bit 6 6 1 PR7 Pending bit 7 7 1 PR8 Pending bit 8 8 1 PR9 Pending bit 9 9 1 PR10 Pending bit 10 10 1 PR11 Pending bit 11 11 1 PR12 Pending bit 12 12 1 PR13 Pending bit 13 13 1 PR14 Pending bit 14 14 1 PR15 Pending bit 15 15 1 PR16 Pending bit 16 16 1 PR17 Pending bit 17 17 1 PR18 Pending bit 18 18 1 PR19 Pending bit 19 19 1 PR20 Pending bit 20 20 1 PR21 Pending bit 21 21 1 PR22 Pending bit 22 22 1 OTG_HS_GLOBAL USB on the go high speed USB_OTG_HS 0x40040000 0x0 0x400 registers OTG_HS_EP1_OUT USB On The Go HS End Point 1 Out global interrupt 74 OTG_HS_EP1_OUT USB On The Go HS End Point 1 Out global interrupt 74 OTG_HS_EP1_IN USB On The Go HS End Point 1 In global interrupt 75 OTG_HS_EP1_IN USB On The Go HS End Point 1 In global interrupt 75 OTG_HS_WKUP USB On The Go HS Wakeup through EXTI interrupt 76 OTG_HS_WKUP USB On The Go HS Wakeup through EXTI interrupt 76 OTG_HS USB On The Go HS global interrupt 77 OTG_HS USB On The Go HS global interrupt 77 GOTGCTL GOTGCTL OTG_HS control and status register 0x0 32 0x00000800 SRQSCS Session request success 0 1 read-only SRQ Session request 1 1 read-write HNGSCS Host negotiation success 8 1 read-only HNPRQ HNP request 9 1 read-write HSHNPEN Host set HNP enable 10 1 read-write DHNPEN Device HNP enabled 11 1 read-write CIDSTS Connector ID status 16 1 read-only DBCT Long/short debounce time 17 1 read-only ASVLD A-session valid 18 1 read-only BSVLD B-session valid 19 1 read-only GOTGINT GOTGINT OTG_HS interrupt register 0x4 32 read-write 0x0 SEDET Session end detected 2 1 SRSSCHG Session request success status change 8 1 HNSSCHG Host negotiation success status change 9 1 HNGDET Host negotiation detected 17 1 ADTOCHG A-device timeout change 18 1 DBCDNE Debounce done 19 1 GAHBCFG GAHBCFG OTG_HS AHB configuration register 0x8 32 read-write 0x0 GINT Global interrupt mask 0 1 HBSTLEN Burst length/type 1 4 DMAEN DMA enable 5 1 TXFELVL TxFIFO empty level 7 1 PTXFELVL Periodic TxFIFO empty level 8 1 GUSBCFG GUSBCFG OTG_HS USB configuration register 0xC 32 0x00000A00 TOCAL FS timeout calibration 0 3 read-write PHYSEL USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select 6 1 write-only SRPCAP SRP-capable 8 1 read-write HNPCAP HNP-capable 9 1 read-write TRDT USB turnaround time 10 4 read-write PHYLPCS PHY Low-power clock select 15 1 read-write ULPIFSLS ULPI FS/LS select 17 1 read-write ULPIAR ULPI Auto-resume 18 1 read-write ULPICSM ULPI Clock SuspendM 19 1 read-write ULPIEVBUSD ULPI External VBUS Drive 20 1 read-write ULPIEVBUSI ULPI external VBUS indicator 21 1 read-write TSDPS TermSel DLine pulsing selection 22 1 read-write PCCI Indicator complement 23 1 read-write PTCI Indicator pass through 24 1 read-write ULPIIPD ULPI interface protect disable 25 1 read-write FHMOD Forced host mode 29 1 read-write FDMOD Forced peripheral mode 30 1 read-write CTXPKT Corrupt Tx packet 31 1 read-write GRSTCTL GRSTCTL OTG_HS reset register 0x10 32 0x20000000 CSRST Core soft reset 0 1 read-write HSRST HCLK soft reset 1 1 read-write FCRST Host frame counter reset 2 1 read-write RXFFLSH RxFIFO flush 4 1 read-write TXFFLSH TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write DMAREQ DMA request signal 30 1 read-only AHBIDL AHB master idle 31 1 read-only GINTSTS GINTSTS OTG_HS core interrupt register 0x14 32 0x04000020 CMOD Current mode of operation 0 1 read-only MMIS Mode mismatch interrupt 1 1 read-write OTGINT OTG interrupt 2 1 read-only SOF Start of frame 3 1 read-write RXFLVL RxFIFO nonempty 4 1 read-only NPTXFE Nonperiodic TxFIFO empty 5 1 read-only GINAKEFF Global IN nonperiodic NAK effective 6 1 read-only BOUTNAKEFF Global OUT NAK effective 7 1 read-only ESUSP Early suspend 10 1 read-write USBSUSP USB suspend 11 1 read-write USBRST USB reset 12 1 read-write ENUMDNE Enumeration done 13 1 read-write ISOODRP Isochronous OUT packet dropped interrupt 14 1 read-write EOPF End of periodic frame interrupt 15 1 read-write IEPINT IN endpoint interrupt 18 1 read-only OEPINT OUT endpoint interrupt 19 1 read-only IISOIXFR Incomplete isochronous IN transfer 20 1 read-write PXFR_INCOMPISOOUT Incomplete periodic transfer 21 1 read-write DATAFSUSP Data fetch suspended 22 1 read-write HPRTINT Host port interrupt 24 1 read-only HCINT Host channels interrupt 25 1 read-only PTXFE Periodic TxFIFO empty 26 1 read-only CIDSCHG Connector ID status change 28 1 read-write DISCINT Disconnect detected interrupt 29 1 read-write SRQINT Session request/new session detected interrupt 30 1 read-write WKUPINT Resume/remote wakeup detected interrupt 31 1 read-write GINTMSK GINTMSK OTG_HS interrupt mask register 0x18 32 0x0 MMISM Mode mismatch interrupt mask 1 1 read-write OTGINT OTG interrupt mask 2 1 read-write SOFM Start of frame mask 3 1 read-write RXFLVLM Receive FIFO nonempty mask 4 1 read-write NPTXFEM Nonperiodic TxFIFO empty mask 5 1 read-write GINAKEFFM Global nonperiodic IN NAK effective mask 6 1 read-write GONAKEFFM Global OUT NAK effective mask 7 1 read-write ESUSPM Early suspend mask 10 1 read-write USBSUSPM USB suspend mask 11 1 read-write USBRST USB reset mask 12 1 read-write ENUMDNEM Enumeration done mask 13 1 read-write ISOODRPM Isochronous OUT packet dropped interrupt mask 14 1 read-write EOPFM End of periodic frame interrupt mask 15 1 read-write EPMISM Endpoint mismatch interrupt mask 17 1 read-write IEPINT IN endpoints interrupt mask 18 1 read-write OEPINT OUT endpoints interrupt mask 19 1 read-write IISOIXFRM Incomplete isochronous IN transfer mask 20 1 read-write PXFRM_IISOOXFRM Incomplete periodic transfer mask 21 1 read-write FSUSPM Data fetch suspended mask 22 1 read-write PRTIM Host port interrupt mask 24 1 read-only HCIM Host channels interrupt mask 25 1 read-write PTXFEM Periodic TxFIFO empty mask 26 1 read-write CIDSCHGM Connector ID status change mask 28 1 read-write DISCINT Disconnect detected interrupt mask 29 1 read-write SRQIM Session request/new session detected interrupt mask 30 1 read-write WUIM Resume/remote wakeup detected interrupt mask 31 1 read-write GRXSTSR_Host GRXSTSR_Host OTG_HS Receive status debug read register (host mode) 0x1C 32 read-only 0x0 CHNUM Channel number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 GRXSTSP_Host GRXSTSP_Host OTG_HS status read and pop register (host mode) 0x20 32 read-only 0x0 CHNUM Channel number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 GRXFSIZ GRXFSIZ OTG_HS Receive FIFO size register 0x24 32 read-write 0x00000200 RXFD RxFIFO depth 0 16 GNPTXFSIZ GNPTXFSIZ OTG_HS nonperiodic transmit FIFO size register (host mode) 0x28 32 read-write 0x00000200 NPTXFSA Nonperiodic transmit RAM start address 0 16 NPTXFD Nonperiodic TxFIFO depth 16 16 TX0FSIZ TX0FSIZ Endpoint 0 transmit FIFO size (peripheral mode) GNPTXFSIZ 0x28 32 read-write 0x00000200 TX0FSA Endpoint 0 transmit RAM start address 0 16 TX0FD Endpoint 0 TxFIFO depth 16 16 GNPTXSTS GNPTXSTS OTG_HS nonperiodic transmit FIFO/queue status register 0x2C 32 read-only 0x00080200 NPTXFSAV Nonperiodic TxFIFO space available 0 16 NPTQXSAV Nonperiodic transmit request queue space available 16 8 NPTXQTOP Top of the nonperiodic transmit request queue 24 7 GCCFG GCCFG OTG_HS general core configuration register 0x38 32 read-write 0x0 PWRDWN Power down 16 1 I2CPADEN Enable I2C bus connection for the external I2C PHY interface 17 1 VBUSASEN Enable the VBUS sensing device 18 1 VBUSBSEN Enable the VBUS sensing device 19 1 SOFOUTEN SOF output enable 20 1 NOVBUSSENS VBUS sensing disable option 21 1 CID CID OTG_HS core ID register 0x3C 32 read-write 0x00001200 PRODUCT_ID Product ID field 0 32 HPTXFSIZ HPTXFSIZ OTG_HS Host periodic transmit FIFO size register 0x100 32 read-write 0x02000600 PTXSA Host periodic TxFIFO start address 0 16 PTXFD Host periodic TxFIFO depth 16 16 50x41,2,3,4,5DIEPTXF%s DIEPTXF1 OTG_HS device IN endpoint transmit FIFO size register 0x104 32 read-write 0x02000400 INEPTXSA IN endpoint FIFOx transmit RAM start address 0 16 INEPTXFD IN endpoint TxFIFO depth 16 16 GRXSTSR_Peripheral GRXSTSR_Peripheral OTG_HS Receive status debug read register (peripheral mode mode) OTG_HS_GRXSTSR_Host 0x1C 32 read-only 0x0 EPNUM Endpoint number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 FRMNUM Frame number 21 4 GRXSTSP_Peripheral GRXSTSP_Peripheral OTG_HS status read and pop register (peripheral mode) OTG_HS_GRXSTSP_Host 0x20 32 read-only 0x0 EPNUM Endpoint number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 FRMNUM Frame number 21 4 OTG_HS_HOST USB on the go high speed USB_OTG_HS 0x40040400 0x0 0x400 registers HCFG HCFG OTG_HS host configuration register 0x0 32 0x0 FSLSPCS FS/LS PHY clock select 0 2 read-write FSLSS FS- and LS-only support 2 1 read-only HFIR HFIR OTG_HS Host frame interval register 0x4 32 read-write 0x0000EA60 FRIVL Frame interval 0 16 HFNUM HFNUM OTG_HS host frame number/frame time remaining register 0x8 32 read-only 0x00003FFF FRNUM Frame number 0 16 FTREM Frame time remaining 16 16 HPTXSTS HPTXSTS OTG_HS_Host periodic transmit FIFO/queue status register 0x10 32 0x00080100 PTXFSAVL Periodic transmit data FIFO space available 0 16 read-write PTXQSAV Periodic transmit request queue space available 16 8 read-only PTXQTOP Top of the periodic transmit request queue 24 8 read-only HAINT HAINT OTG_HS Host all channels interrupt register 0x14 32 read-only 0x0 HAINT Channel interrupts 0 16 HAINTMSK HAINTMSK OTG_HS host all channels interrupt mask register 0x18 32 read-write 0x0 HAINTM Channel interrupt mask 0 16 HPRT HPRT OTG_HS host port control and status register 0x40 32 0x0 PCSTS Port connect status 0 1 read-only PCDET Port connect detected 1 1 read-write PENA Port enable 2 1 read-write PENCHNG Port enable/disable change 3 1 read-write POCA Port overcurrent active 4 1 read-only POCCHNG Port overcurrent change 5 1 read-write PRES Port resume 6 1 read-write PSUSP Port suspend 7 1 read-write PRST Port reset 8 1 read-write PLSTS Port line status 10 2 read-only PPWR Port power 12 1 read-write PTCTL Port test control 13 4 read-write PSPD Port speed 17 2 read-only HCCHAR0 HCCHAR0 OTG_HS host channel-0 characteristics register 0x100 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR1 HCCHAR1 OTG_HS host channel-1 characteristics register 0x120 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR2 HCCHAR2 OTG_HS host channel-2 characteristics register 0x140 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR3 HCCHAR3 OTG_HS host channel-3 characteristics register 0x160 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR4 HCCHAR4 OTG_HS host channel-4 characteristics register 0x180 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR5 HCCHAR5 OTG_HS host channel-5 characteristics register 0x1A0 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR6 HCCHAR6 OTG_HS host channel-6 characteristics register 0x1C0 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR7 HCCHAR7 OTG_HS host channel-7 characteristics register 0x1E0 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR8 HCCHAR8 OTG_HS host channel-8 characteristics register 0x200 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR9 HCCHAR9 OTG_HS host channel-9 characteristics register 0x220 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR10 HCCHAR10 OTG_HS host channel-10 characteristics register 0x240 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCCHAR11 HCCHAR11 OTG_HS host channel-11 characteristics register 0x260 32 read-write 0x0 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MC Multi Count (MC) / Error Count (EC) 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 HCSPLT0 HCSPLT0 OTG_HS host channel-0 split control register 0x104 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCSPLT1 HCSPLT1 OTG_HS host channel-1 split control register 0x124 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCSPLT2 HCSPLT2 OTG_HS host channel-2 split control register 0x144 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCSPLT3 HCSPLT3 OTG_HS host channel-3 split control register 0x164 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCSPLT4 HCSPLT4 OTG_HS host channel-4 split control register 0x184 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCSPLT5 HCSPLT5 OTG_HS host channel-5 split control register 0x1A4 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCSPLT6 HCSPLT6 OTG_HS host channel-6 split control register 0x1C4 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCSPLT7 HCSPLT7 OTG_HS host channel-7 split control register 0x1E4 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCSPLT8 HCSPLT8 OTG_HS host channel-8 split control register 0x204 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCSPLT9 HCSPLT9 OTG_HS host channel-9 split control register 0x224 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCSPLT10 HCSPLT10 OTG_HS host channel-10 split control register 0x244 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCSPLT11 HCSPLT11 OTG_HS host channel-11 split control register 0x264 32 read-write 0x0 PRTADDR Port address 0 7 HUBADDR Hub address 7 7 XACTPOS XACTPOS 14 2 COMPLSPLT Do complete split 16 1 SPLITEN Split enable 31 1 HCINT0 HCINT0 OTG_HS host channel-11 interrupt register 0x108 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT1 HCINT1 OTG_HS host channel-1 interrupt register 0x128 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT2 HCINT2 OTG_HS host channel-2 interrupt register 0x148 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT3 HCINT3 OTG_HS host channel-3 interrupt register 0x168 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT4 HCINT4 OTG_HS host channel-4 interrupt register 0x188 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT5 HCINT5 OTG_HS host channel-5 interrupt register 0x1A8 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT6 HCINT6 OTG_HS host channel-6 interrupt register 0x1C8 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT7 HCINT7 OTG_HS host channel-7 interrupt register 0x1E8 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT8 HCINT8 OTG_HS host channel-8 interrupt register 0x208 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT9 HCINT9 OTG_HS host channel-9 interrupt register 0x228 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT10 HCINT10 OTG_HS host channel-10 interrupt register 0x248 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINT11 HCINT11 OTG_HS host channel-11 interrupt register 0x268 32 read-write 0x0 XFRC Transfer completed 0 1 CHH Channel halted 1 1 AHBERR AHB error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET Response received interrupt 6 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 HCINTMSK0 HCINTMSK0 OTG_HS host channel-11 interrupt mask register 0x10C 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK1 HCINTMSK1 OTG_HS host channel-1 interrupt mask register 0x12C 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK2 HCINTMSK2 OTG_HS host channel-2 interrupt mask register 0x14C 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK3 HCINTMSK3 OTG_HS host channel-3 interrupt mask register 0x16C 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK4 HCINTMSK4 OTG_HS host channel-4 interrupt mask register 0x18C 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK5 HCINTMSK5 OTG_HS host channel-5 interrupt mask register 0x1AC 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK6 HCINTMSK6 OTG_HS host channel-6 interrupt mask register 0x1CC 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK7 HCINTMSK7 OTG_HS host channel-7 interrupt mask register 0x1EC 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK8 HCINTMSK8 OTG_HS host channel-8 interrupt mask register 0x20C 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK9 HCINTMSK9 OTG_HS host channel-9 interrupt mask register 0x22C 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK10 HCINTMSK10 OTG_HS host channel-10 interrupt mask register 0x24C 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCINTMSK11 HCINTMSK11 OTG_HS host channel-11 interrupt mask register 0x26C 32 read-write 0x0 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 AHBERR AHB error 2 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 HCTSIZ0 HCTSIZ0 OTG_HS host channel-11 transfer size register 0x110 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ1 HCTSIZ1 OTG_HS host channel-1 transfer size register 0x130 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ2 HCTSIZ2 OTG_HS host channel-2 transfer size register 0x150 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ3 HCTSIZ3 OTG_HS host channel-3 transfer size register 0x170 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ4 HCTSIZ4 OTG_HS host channel-4 transfer size register 0x190 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ5 HCTSIZ5 OTG_HS host channel-5 transfer size register 0x1B0 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ6 HCTSIZ6 OTG_HS host channel-6 transfer size register 0x1D0 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ7 HCTSIZ7 OTG_HS host channel-7 transfer size register 0x1F0 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ8 HCTSIZ8 OTG_HS host channel-8 transfer size register 0x210 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ9 HCTSIZ9 OTG_HS host channel-9 transfer size register 0x230 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ10 HCTSIZ10 OTG_HS host channel-10 transfer size register 0x250 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCTSIZ11 HCTSIZ11 OTG_HS host channel-11 transfer size register 0x270 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 HCDMA0 HCDMA0 OTG_HS host channel-0 DMA address register 0x114 32 read-write 0x0 DMAADDR DMA address 0 32 HCDMA1 HCDMA1 OTG_HS host channel-1 DMA address register 0x134 32 read-write 0x0 DMAADDR DMA address 0 32 HCDMA2 HCDMA2 OTG_HS host channel-2 DMA address register 0x154 32 read-write 0x0 DMAADDR DMA address 0 32 HCDMA3 HCDMA3 OTG_HS host channel-3 DMA address register 0x174 32 read-write 0x0 DMAADDR DMA address 0 32 HCDMA4 HCDMA4 OTG_HS host channel-4 DMA address register 0x194 32 read-write 0x0 DMAADDR DMA address 0 32 HCDMA5 HCDMA5 OTG_HS host channel-5 DMA address register 0x1B4 32 read-write 0x0 DMAADDR DMA address 0 32 HCDMA6 HCDMA6 OTG_HS host channel-6 DMA address register 0x1D4 32 read-write 0x0 DMAADDR DMA address 0 32 HCDMA7 HCDMA7 OTG_HS host channel-7 DMA address register 0x1F4 32 read-write 0x0 DMAADDR DMA address 0 32 HCDMA8 HCDMA8 OTG_HS host channel-8 DMA address register 0x214 32 read-write 0x0 DMAADDR DMA address 0 32 HCDMA9 HCDMA9 OTG_HS host channel-9 DMA address register 0x234 32 read-write 0x0 DMAADDR DMA address 0 32 HCDMA10 HCDMA10 OTG_HS host channel-10 DMA address register 0x254 32 read-write 0x0 DMAADDR DMA address 0 32 HCDMA11 HCDMA11 OTG_HS host channel-11 DMA address register 0x274 32 read-write 0x0 DMAADDR DMA address 0 32 OTG_HS_DEVICE USB on the go high speed USB_OTG_HS 0x40040800 0x0 0x400 registers DCFG DCFG OTG_HS device configuration register 0x0 32 read-write 0x02200000 DSPD Device speed 0 2 NZLSOHSK Nonzero-length status OUT handshake 2 1 DAD Device address 4 7 PFIVL Periodic (micro)frame interval 11 2 PERSCHIVL Periodic scheduling interval 24 2 DCTL DCTL OTG_HS device control register 0x4 32 0x0 RWUSIG Remote wakeup signaling 0 1 read-write SDIS Soft disconnect 1 1 read-write GINSTS Global IN NAK status 2 1 read-only GONSTS Global OUT NAK status 3 1 read-only TCTL Test control 4 3 read-write SGINAK Set global IN NAK 7 1 write-only CGINAK Clear global IN NAK 8 1 write-only SGONAK Set global OUT NAK 9 1 write-only CGONAK Clear global OUT NAK 10 1 write-only POPRGDNE Power-on programming done 11 1 read-write DSTS DSTS OTG_HS device status register 0x8 32 read-only 0x00000010 SUSPSTS Suspend status 0 1 ENUMSPD Enumerated speed 1 2 EERR Erratic error 3 1 FNSOF Frame number of the received SOF 8 14 DIEPMSK DIEPMSK OTG_HS device IN endpoint common interrupt mask register 0x10 32 read-write 0x0 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 TOM Timeout condition mask (nonisochronous endpoints) 3 1 ITTXFEMSK IN token received when TxFIFO empty mask 4 1 INEPNMM IN token received with EP mismatch mask 5 1 INEPNEM IN endpoint NAK effective mask 6 1 TXFURM FIFO underrun mask 8 1 BIM BNA interrupt mask 9 1 DOEPMSK DOEPMSK OTG_HS device OUT endpoint common interrupt mask register 0x14 32 read-write 0x0 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 STUPM SETUP phase done mask 3 1 OTEPDM OUT token received when endpoint disabled mask 4 1 B2BSTUP Back-to-back SETUP packets received mask 6 1 OPEM OUT packet error mask 8 1 BOIM BNA interrupt mask 9 1 DAINT DAINT OTG_HS device all endpoints interrupt register 0x18 32 read-only 0x0 IEPINT IN endpoint interrupt bits 0 16 OEPINT OUT endpoint interrupt bits 16 16 DAINTMSK DAINTMSK OTG_HS all endpoints interrupt mask register 0x1C 32 read-write 0x0 IEPM IN EP interrupt mask bits 0 16 OEPM OUT EP interrupt mask bits 16 16 DVBUSDIS DVBUSDIS OTG_HS device VBUS discharge time register 0x28 32 read-write 0x000017D7 VBUSDT Device VBUS discharge time 0 16 DVBUSPULSE DVBUSPULSE OTG_HS device VBUS pulsing time register 0x2C 32 read-write 0x000005B8 DVBUSP Device VBUS pulsing time 0 12 DTHRCTL DTHRCTL OTG_HS Device threshold control register 0x30 32 read-write 0x0 NONISOTHREN Nonisochronous IN endpoints threshold enable 0 1 ISOTHREN ISO IN endpoint threshold enable 1 1 TXTHRLEN Transmit threshold length 2 9 RXTHREN Receive threshold enable 16 1 RXTHRLEN Receive threshold length 17 9 ARPEN Arbiter parking enable 27 1 DIEPEMPMSK DIEPEMPMSK OTG_HS device IN endpoint FIFO empty interrupt mask register 0x34 32 read-write 0x0 INEPTXFEM IN EP Tx FIFO empty interrupt mask bits 0 16 DEACHINT DEACHINT OTG_HS device each endpoint interrupt register 0x38 32 read-write 0x0 IEP1INT IN endpoint 1interrupt bit 1 1 OEP1INT OUT endpoint 1 interrupt bit 17 1 DEACHINTMSK DEACHINTMSK OTG_HS device each endpoint interrupt register mask 0x3C 32 read-write 0x0 IEP1INTM IN Endpoint 1 interrupt mask bit 1 1 OEP1INTM OUT Endpoint 1 interrupt mask bit 17 1 DIEPEACHMSK1 DIEPEACHMSK1 OTG_HS device each in endpoint-1 interrupt register 0x40 32 read-write 0x0 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 TOM Timeout condition mask (nonisochronous endpoints) 3 1 ITTXFEMSK IN token received when TxFIFO empty mask 4 1 INEPNMM IN token received with EP mismatch mask 5 1 INEPNEM IN endpoint NAK effective mask 6 1 TXFURM FIFO underrun mask 8 1 BIM BNA interrupt mask 9 1 NAKM NAK interrupt mask 13 1 DOEPEACHMSK1 DOEPEACHMSK1 OTG_HS device each OUT endpoint-1 interrupt register 0x80 32 read-write 0x0 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 TOM Timeout condition mask 3 1 ITTXFEMSK IN token received when TxFIFO empty mask 4 1 INEPNMM IN token received with EP mismatch mask 5 1 INEPNEM IN endpoint NAK effective mask 6 1 TXFURM OUT packet error mask 8 1 BIM BNA interrupt mask 9 1 BERRM Bubble error interrupt mask 12 1 NAKM NAK interrupt mask 13 1 NYETM NYET interrupt mask 14 1 DIEPCTL0 DIEPCTL0 OTG device endpoint-0 control register 0x100 32 0x0 MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM_DPID Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID_SEVNFRM Set DATA0 PID 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write 50x201,2,3,4,5DIEPCTL%s DIEPCTL1 OTG device endpoint-1 control register 0x120 32 0x0 MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM_DPID Even/odd frame 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID_SEVNFRM Set DATA0 PID 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write 60x200,1,2,3,4,5DIEPINT%s DIEPINT0 OTG device endpoint-%s interrupt register 0x108 32 0x00000080 XFRC Transfer completed interrupt 0 1 read-write EPDISD Endpoint disabled interrupt 1 1 read-write TOC Timeout condition 3 1 read-write ITTXFE IN token received when TxFIFO is empty 4 1 read-write INEPNE IN endpoint NAK effective 6 1 read-write TXFE Transmit FIFO empty 7 1 read-only TXFIFOUDRN Transmit Fifo Underrun 8 1 read-write BNA Buffer not available interrupt 9 1 read-write PKTDRPSTS Packet dropped status 11 1 read-write BERR Babble error interrupt 12 1 read-write NAK NAK interrupt 13 1 read-write DIEPTSIZ0 DIEPTSIZ0 OTG_HS device IN endpoint 0 transfer size register 0x110 32 read-write 0x0 XFRSIZ Transfer size 0 7 PKTCNT Packet count 19 2 DIEPDMA1 DIEPDMA1 OTG_HS device endpoint-1 DMA address register 0x114 32 read-write 0x0 DMAADDR DMA address 0 32 DIEPDMA2 DIEPDMA2 OTG_HS device endpoint-2 DMA address register 0x134 32 read-write 0x0 DMAADDR DMA address 0 32 DIEPDMA3 DIEPDMA3 OTG_HS device endpoint-3 DMA address register 0x154 32 read-write 0x0 DMAADDR DMA address 0 32 DIEPDMA4 DIEPDMA4 OTG_HS device endpoint-4 DMA address register 0x174 32 read-write 0x0 DMAADDR DMA address 0 32 DIEPDMA5 DIEPDMA5 OTG_HS device endpoint-5 DMA address register 0x194 32 read-write 0x0 DMAADDR DMA address 0 32 60x200,1,2,3,4,5DTXFSTS%s DTXFSTS0 OTG_HS device IN endpoint transmit FIFO status register 0x118 32 read-only 0x0 INEPTFSAV IN endpoint TxFIFO space avail 0 16 50x201,2,3,4,5DIEPTSIZ%s DIEPTSIZ1 OTG_HS device endpoint transfer size register 0x130 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 MCNT Multi count 29 2 DOEPCTL0 DOEPCTL0 OTG_HS device control OUT endpoint 0 control register 0x300 32 0x00008000 MPSIZ Maximum packet size 0 2 read-only USBAEP USB active endpoint 15 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-only SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPDIS Endpoint disable 30 1 read-only EPENA Endpoint enable 31 1 write-only 50x201,2,3,4,5DOEPCTL%s DOEPCTL1 OTG device endpoint-1 control register 0x320 32 0x0 MPSIZ Maximum packet size 0 11 read-write USBAEP USB active endpoint 15 1 read-write EONUM_DPID Even odd frame/Endpoint data PID 16 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-write SNPM Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only SD0PID_SEVNFRM Set DATA0 PID/Set even frame 28 1 write-only SODDFRM Set odd frame 29 1 write-only EPDIS Endpoint disable 30 1 read-write EPENA Endpoint enable 31 1 read-write 60x200,1,2,3,4,5DOEPINT%s DOEPINT0 OTG_HS device endpoint-%s interrupt register 0x308 32 read-write 0x00000080 XFRC Transfer completed interrupt 0 1 EPDISD Endpoint disabled interrupt 1 1 STUP SETUP phase done 3 1 OTEPDIS OUT token received when endpoint disabled 4 1 B2BSTUP Back-to-back SETUP packets received 6 1 NYET NYET interrupt 14 1 DOEPTSIZ0 DOEPTSIZ0 OTG_HS device endpoint-1 transfer size register 0x310 32 read-write 0x0 XFRSIZ Transfer size 0 7 PKTCNT Packet count 19 1 STUPCNT SETUP packet count 29 2 50x201,2,3,4,5DOEPTSIZ%s DOEPTSIZ1 OTG_HS device endpoint-2 transfer size register 0x330 32 read-write 0x0 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 OTG_HS_PWRCLK USB on the go high speed USB_OTG_HS 0x40040E00 0x0 0x3F200 registers PCGCCTL PCGCCTL Power and clock gating control register 0x0 32 read-write 0x0 STPPCLK Stop PHY clock 0 1 GATEHCLK Gate HCLK 1 1 PHYSUSP PHY suspended 4 1 LTDC LCD-TFT Controller LTDC 0x40016800 0x0 0x400 registers LCD_TFT LTDC global interrupt 88 LCD_TFT LTDC global interrupt 88 LCD_TFT_1 LTDC global error interrupt 89 LCD_TFT_1 LTDC global error interrupt 89 20x801,2LAYER%sCluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR0x84 CR L1CR Layerx Control Register 0x0 0x20 read-write 0x00000000 CLUTEN Color Look-Up Table Enable 4 1 CLUTENread-writeDisabledColor look-up table disabled0EnabledColor look-up table enabled1 COLKEN Color Keying Enable 1 1 COLKENread-writeDisabledColor keying disabled0EnabledColor keying enabled1 LEN Layer Enable 0 1 LENread-writeDisabledLayer disabled0EnabledLayer enabled1 WHPCR L1WHPCR Layerx Window Horizontal Position Configuration Register 0x4 0x20 read-write 0x00000000 WHSPPOS Window Horizontal Stop Position 16 12 04095 WHSTPOS Window Horizontal Start Position 0 12 04095 WVPCR L1WVPCR Layerx Window Vertical Position Configuration Register 0x8 0x20 read-write 0x00000000 WVSPPOS Window Vertical Stop Position 16 11 02047 WVSTPOS Window Vertical Start Position 0 11 02047 CKCR L1CKCR Layerx Color Keying Configuration Register 0xc 0x20 read-write 0x00000000 CKRED Color Key Red value 16 8 0255 CKGREEN Color Key Green value 8 8 0255 CKBLUE Color Key Blue value 0 8 0255 PFCR L1PFCR Layerx Pixel Format Configuration Register 0x10 0x20 read-write 0x00000000 PF Pixel Format 0 3 PFread-writeARGB8888ARGB88880RGB888RGB8881RGB565RGB5652ARGB1555ARGB15553ARGB4444ARGB44444L8L8 (8-bit luminance)5AL44AL44 (4-bit alpha, 4-bit luminance)6AL88AL88 (8-bit alpha, 8-bit luminance)7 CACR L1CACR Layerx Constant Alpha Configuration Register 0x14 0x20 read-write 0x00000000 CONSTA Constant Alpha 0 8 0255 DCCR L1DCCR Layerx Default Color Configuration Register 0x18 0x20 read-write 0x00000000 DCALPHA Default Color Alpha 24 8 0255 DCRED Default Color Red 16 8 0255 DCGREEN Default Color Green 8 8 0255 DCBLUE Default Color Blue 0 8 0255 BFCR L1BFCR Layerx Blending Factors Configuration Register 0x1c 0x20 read-write 0x00000607 BF1 Blending Factor 1 8 3 BF1read-writeConstantBF1 = constant alpha4PixelBF1 = pixel alpha * constant alpha6 BF2 Blending Factor 2 0 3 BF2read-writeConstantBF2 = 1 - constant alpha5PixelBF2 = 1 - pixel alpha * constant alpha7 CFBAR L1CFBAR Layerx Color Frame Buffer Address Register 0x28 0x20 read-write 0x00000000 CFBADD Color Frame Buffer Start Address 0 32 04294967295 CFBLR L1CFBLR Layerx Color Frame Buffer Length Register 0x2c 0x20 read-write 0x00000000 CFBP Color Frame Buffer Pitch in bytes 16 13 08191 CFBLL Color Frame Buffer Line Length 0 13 08191 CFBLNR L1CFBLNR Layerx ColorFrame Buffer Line Number Register 0x30 0x20 read-write 0x00000000 CFBLNBR Frame Buffer Line Number 0 11 02047 CLUTWR L1CLUTWR Layerx CLUT Write Register 0x40 0x20 write-only 0x00000000 CLUTADD CLUT Address 24 8 0255 RED Red value 16 8 0255 GREEN Green value 8 8 0255 BLUE Blue value 0 8 0255 SSCR SSCR Synchronization Size Configuration Register 0x8 0x20 read-write 0x00000000 HSW Horizontal Synchronization Width (in units of pixel clock period) 16 12 04095 VSH Vertical Synchronization Height (in units of horizontal scan line) 0 11 02047 BPCR BPCR Back Porch Configuration Register 0xC 0x20 read-write 0x00000000 AHBP Accumulated Horizontal back porch (in units of pixel clock period) 16 12 04095 AVBP Accumulated Vertical back porch (in units of horizontal scan line) 0 11 02047 AWCR AWCR Active Width Configuration Register 0x10 0x20 read-write 0x00000000 AAW Accumulated Active Width (in units of pixel clock period) 16 12 04095 AAH Accumulated Active Height (in units of horizontal scan line) 0 11 02047 TWCR TWCR Total Width Configuration Register 0x14 0x20 read-write 0x00000000 TOTALW Total Width (in units of pixel clock period) 16 12 04095 TOTALH Total Height (in units of horizontal scan line) 0 11 02047 GCR GCR Global Control Register 0x18 0x20 0x00002220 HSPOL Horizontal Synchronization Polarity 31 1 read-write HSPOLread-writeActiveLowHorizontal synchronization polarity is active low0ActiveHighHorizontal synchronization polarity is active high1 VSPOL Vertical Synchronization Polarity 30 1 read-write VSPOLread-writeActiveLowVertical synchronization polarity is active low0ActiveHighVertical synchronization polarity is active high1 DEPOL Data Enable Polarity 29 1 read-write DEPOLread-writeActiveLowData enable polarity is active low0ActiveHighData enable polarity is active high1 PCPOL Pixel Clock Polarity 28 1 read-write PCPOLread-writeRisingEdgePixel clock on rising edge0FallingEdgePixel clock on falling edge1 DEN Dither Enable 16 1 read-write DENread-writeDisabledDither disabled0EnabledDither enabled1 DRW Dither Red Width 12 3 read-only DGW Dither Green Width 8 3 read-only DBW Dither Blue Width 4 3 read-only LTDCEN LCD-TFT controller enable bit 0 1 read-write LTDCENread-writeDisabledLCD-TFT controller disabled0EnabledLCD-TFT controller enabled1 SRCR SRCR Shadow Reload Configuration Register 0x24 0x20 read-write 0x00000000 VBR Vertical Blanking Reload 1 1 VBRread-writeReloadThe shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area).1NoEffectThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)0 IMR Immediate Reload 0 1 IMRread-writeReloadThe shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload1NoEffectThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)0 BCCR BCCR Background Color Configuration Register 0x2C 0x20 read-write 0x00000000 BCBLUEBackground color blue value080255 BCGREENBackground color green value880255 BCREDBackground color red value1680255 IER IER Interrupt Enable Register 0x34 0x20 read-write 0x00000000 RRIE Register Reload interrupt enable 3 1 RRIEread-writeDisabledRegister reload interrupt disabled0EnabledRegister reload interrupt enabled1 TERRIE Transfer Error Interrupt Enable 2 1 TERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 FUIE FIFO Underrun Interrupt Enable 1 1 FUIEread-writeDisabledFIFO underrun interrupt disabled0EnabledFIFO underrun interrupt enabled1 LIE Line Interrupt Enable 0 1 LIEread-writeDisabledLine interrupt disabled0EnabledLine interrupt enabled1 ISR ISR Interrupt Status Register 0x38 0x20 read-only 0x00000000 RRIF Register Reload Interrupt Flag 3 1 RRIFread-writeNoReloadNo register reload0ReloadRegister reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)1 TERRIF Transfer Error interrupt flag 2 1 TERRIFread-writeNoErrorNo transfer error0ErrorTransfer error interrupt generated when a bus error occurs1 FUIF FIFO Underrun Interrupt flag 1 1 FUIFread-writeNoUnderrunNo FIFO underrun0UnderrunFIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO1 LIF Line Interrupt flag 0 1 LIFread-writeNotReachedProgrammed line not reached0ReachedLine interrupt generated when a programmed line is reached1 ICR ICR Interrupt Clear Register 0x3C 0x20 write-only 0x00000000 CRRIF Clears Register Reload Interrupt Flag 3 1 CRRIFread-writeClearClears the RRIF flag in the ISR register1 CTERRIF Clears the Transfer Error Interrupt Flag 2 1 CTERRIFread-writeClearClears the TERRIF flag in the ISR register1 CFUIF Clears the FIFO Underrun Interrupt flag 1 1 CFUIFread-writeClearClears the FUIF flag in the ISR register1 CLIF Clears the Line Interrupt Flag 0 1 CLIFread-writeClearClears the LIF flag in the ISR register1 LIPCR LIPCR Line Interrupt Position Configuration Register 0x40 0x20 read-write 0x00000000 LIPOS Line Interrupt Position 0 11 02047 CPSR CPSR Current Position Status Register 0x44 0x20 read-only 0x00000000 CXPOS Current X Position 16 16 CYPOS Current Y Position 0 16 CDSR CDSR Current Display Status Register 0x48 0x20 read-only 0x0000000F HSYNCS Horizontal Synchronization display Status 3 1 HSYNCSread-writeNotActiveCurrently not in HSYNC phase0ActiveCurrently in HSYNC phase1 VSYNCS Vertical Synchronization display Status 2 1 VSYNCSread-writeNotActiveCurrently not in VSYNC phase0ActiveCurrently in VSYNC phase1 HDES Horizontal Data Enable display Status 1 1 HDESread-writeNotActiveCurrently not in horizontal Data Enable phase0ActiveCurrently in horizontal Data Enable phase1 VDES Vertical Data Enable display Status 0 1 VDESread-writeNotActiveCurrently not in vertical Data Enable phase0ActiveCurrently in vertical Data Enable phase1 SAI Serial audio interface SAI 0x40015800 0x0 0x400 registers SAI1 SAI1 global interrupt 87 SAI1 SAI1 global interrupt 87 20x20A,BCH%sCluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR0x4 CR1 ACR1 AConfiguration register 1 0x0 0x20 read-write 0x00000040 MCKDIV Master clock divider 20 4 NODIV No divider 19 1 NODIVread-writeMasterClockMCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value0NoDivMCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.1 DMAEN DMA enable 17 1 DMAENread-writeDisabledDMA disabled0EnabledDMA enabled1 SAIEN Audio block A enable 16 1 SAIENread-writeDisabledSAI audio block disabled0EnabledSAI audio block enabled1 OUTDRIV Output drive 13 1 OUTDRIVread-writeOnStartAudio block output driven when SAIEN is set0ImmediatelyAudio block output driven immediately after the setting of this bit1 MONO Mono mode 12 1 MONOread-writeStereoStereo mode0MonoMono mode1 SYNCEN Synchronization enable 10 2 SYNCENread-writeAsynchronousaudio sub-block in asynchronous mode0Internalaudio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode1Externalaudio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode2 CKSTR Clock strobing edge 9 1 CKSTRread-writeFallingEdgeData strobing edge is falling edge of SCK0RisingEdgeData strobing edge is rising edge of SCK1 LSBFIRST Least significant bit first 8 1 LSBFIRSTread-writeMsbFirstData are transferred with MSB first0LsbFirstData are transferred with LSB first1 DS Data size 5 3 DSread-writeBit88 bits2Bit1010 bits3Bit1616 bits4Bit2020 bits5Bit2424 bits6Bit3232 bits7 PRTCFG Protocol configuration 2 2 PRTCFGread-writeFreeFree protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol0SpdifSPDIF protocol1Ac97AC’97 protocol2 MODE Audio block mode 0 2 MODEread-writeMasterTxMaster transmitter0MasterRxMaster receiver1SlaveTxSlave transmitter2SlaveRxSlave receiver3 CR2 ACR2 AConfiguration register 2 0x4 0x20 read-write 0x00000000 COMP Companding mode 14 2 COMPread-writeNoCompandingNo companding algorithm0MuLawμ-Law algorithm2ALawA-Law algorithm3 CPL Complement bit 13 1 CPLread-writeOnesComplement1’s complement representation0TwosComplement2’s complement representation1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 MUTEVALread-writeSendZeroBit value 0 is sent during the mute mode0SendLastLast values are sent during the mute mode1 MUTE Mute 5 1 MUTEread-writeDisabledNo mute mode0EnabledMute mode enabled1 TRIS Tristate management on data line 4 1 FFLUSH FIFO flush 3 1 FFLUSHread-writeNoFlushNo FIFO flush0FlushFIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared1 FTH FIFO threshold 0 3 FTHread-writeEmptyFIFO empty0Quarter11⁄4 FIFO1Quarter21⁄2 FIFO2Quarter33⁄4 FIFO3FullFIFO full4 FRCR AFRCR AFRCR 0x8 0x20 read-write 0x00000007 FSOFF Frame synchronization offset 18 1 FSOFFread-writeOnFirstFS is asserted on the first bit of the slot 00BeforeFirstFS is asserted one bit before the first bit of the slot 01 FSPOL Frame synchronization polarity 17 1 FSPOLread-writeFallingEdgeFS is active low (falling edge)0RisingEdgeFS is active high (rising edge)1 FSDEF Frame synchronization definition 16 1 FSALL Frame synchronization active level length 8 7 FRL Frame length 0 8 SLOTR ASLOTR ASlot register 0xc 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 SLOTENread-writeInactiveInactive slot0ActiveActive slot1 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 SLOTSZread-writeDataSizeThe slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)0Bit1616-bit1Bit3232-bit2 FBOFF First bit offset 0 5 IM AIM AInterrupt mask register2 0x10 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 LFSDETIEread-writeDisabledInterrupt is disabled0EnabledInterrupt is enabled1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 AFSDETIEread-writeDisabledInterrupt is disabled0EnabledInterrupt is enabled1 CNRDYIE Codec not ready interrupt enable 4 1 CNRDYIEread-writeDisabledInterrupt is disabled0EnabledInterrupt is enabled1 FREQIE FIFO request interrupt enable 3 1 FREQIEread-writeDisabledInterrupt is disabled0EnabledInterrupt is enabled1 WCKCFGIE Wrong clock configuration interrupt enable 2 1 WCKCFGIEread-writeDisabledInterrupt is disabled0EnabledInterrupt is enabled1 MUTEDETIE Mute detection interrupt enable 1 1 MUTEDETIEread-writeDisabledInterrupt is disabled0EnabledInterrupt is enabled1 OVRUDRIE Overrun/underrun interrupt enable 0 1 OVRUDRIEread-writeDisabledInterrupt is disabled0EnabledInterrupt is enabled1 SR ASR AStatus register 0x14 0x20 read-write 0x00000000 FLVL FIFO level threshold 16 3 FLVLRreadEmptyFIFO empty0Quarter1FIFO <= 1⁄4 but not empty1Quarter21⁄4 < FIFO <= 1⁄22Quarter31⁄2 < FIFO <= 3⁄43Quarter43⁄4 < FIFO but not full4FullFIFO full5 LFSDET Late frame synchronization detection 6 1 LFSDETRreadNoErrorNo error0NoSyncFrame synchronization signal is not present at the right time1 AFSDET Anticipated frame synchronization detection 5 1 AFSDETRreadNoErrorNo error0EarlySyncFrame synchronization signal is detected earlier than expected1 CNRDY Codec not ready 4 1 CNRDYRreadReadyExternal AC’97 Codec is ready0NotReadyExternal AC’97 Codec is not ready1 FREQ FIFO request 3 1 FREQRreadNoRequestNo FIFO request0RequestFIFO request to read or to write the SAI_xDR1 WCKCFG Wrong clock configuration flag. This bit is read only. 2 1 WCKCFGRreadCorrectClock configuration is correct0WrongClock configuration does not respect the rule concerning the frame length specification1 MUTEDET Mute detection 1 1 MUTEDETRreadNoMuteNo MUTE detection on the SD input line0MuteMUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame1 OVRUDR Overrun / underrun 0 1 OVRUDRRreadNoErrorNo overrun/underrun error0OverrunOverrun/underrun error detection1 CLRFR ACLRFR AClear flag register 0x18 0x20 read-write 0x00000000 CLFSDET Clear late frame synchronization detection flag 6 1 CLFSDETWwriteClearClears the LFSDET flag1 CAFSDET Clear anticipated frame synchronization detection flag. 5 1 CAFSDETWwriteClearClears the AFSDET flag1 CCNRDY Clear codec not ready flag 4 1 CCNRDYWwriteClearClears the CNRDY flag1 CWCKCFG Clear wrong clock configuration flag 2 1 CWCKCFGWwriteClearClears the WCKCFG flag1 CMUTEDET Mute detection flag 1 1 CMUTEDETWwriteClearClears the MUTEDET flag1 COVRUDR Clear overrun / underrun 0 1 COVRUDRWwriteClearClears the OVRUDR flag1 DR ADR AData register 0x1c 0x20 read-write 0x00000000 DATA Data 0 32 DMA2D DMA2D controller DMA2D 0x4002B000 0x0 0xC00 registers DMA2D DMA2D global interrupt 90 DMA2D DMA2D global interrupt 90 CR CR control register 0x0 0x20 read-write 0x00000000 MODE DMA2D mode 16 2 CEIE Configuration Error Interrupt Enable 13 1 CTCIE CLUT transfer complete interrupt enable 12 1 CAEIE CLUT access error interrupt enable 11 1 TWIE Transfer watermark interrupt enable 10 1 TCIE Transfer complete interrupt enable 9 1 TEIE Transfer error interrupt enable 8 1 ABORT Abort 2 1 SUSP Suspend 1 1 START Start 0 1 ISR ISR Interrupt Status Register 0x4 0x20 read-only 0x00000000 CEIF Configuration error interrupt flag 5 1 CTCIF CLUT transfer complete interrupt flag 4 1 CAEIF CLUT access error interrupt flag 3 1 TWIF Transfer watermark interrupt flag 2 1 TCIF Transfer complete interrupt flag 1 1 TEIF Transfer error interrupt flag 0 1 IFCR IFCR interrupt flag clear register 0x8 0x20 read-write 0x00000000 CCEIF Clear configuration error interrupt flag 5 1 CCTCIF Clear CLUT transfer complete interrupt flag 4 1 CAECIF Clear CLUT access error interrupt flag 3 1 CTWIF Clear transfer watermark interrupt flag 2 1 CTCIF Clear transfer complete interrupt flag 1 1 CTEIF Clear Transfer error interrupt flag 0 1 FGMAR FGMAR foreground memory address register 0xC 0x20 read-write 0x00000000 MA Memory address 0 32 FGOR FGOR foreground offset register 0x10 0x20 read-write 0x00000000 LO Line offset 0 14 BGMAR BGMAR background memory address register 0x14 0x20 read-write 0x00000000 MA Memory address 0 32 BGOR BGOR background offset register 0x18 0x20 read-write 0x00000000 LO Line offset 0 14 FGPFCCR FGPFCCR foreground PFC control register 0x1C 0x20 read-write 0x00000000 ALPHA Alpha value 24 8 AM Alpha mode 16 2 CS CLUT size 8 8 START Start 5 1 CCM CLUT color mode 4 1 CM Color mode 0 4 FGCOLR FGCOLR foreground color register 0x20 0x20 read-write 0x00000000 RED Red Value 16 8 GREEN Green Value 8 8 BLUE Blue Value 0 8 BGPFCCR BGPFCCR background PFC control register 0x24 0x20 read-write 0x00000000 ALPHA Alpha value 24 8 AM Alpha mode 16 2 CS CLUT size 8 8 START Start 5 1 CCM CLUT Color mode 4 1 CM Color mode 0 4 BGCOLR BGCOLR background color register 0x28 0x20 read-write 0x00000000 RED Red Value 16 8 GREEN Green Value 8 8 BLUE Blue Value 0 8 FGCMAR FGCMAR foreground CLUT memory address register 0x2C 0x20 read-write 0x00000000 MA Memory Address 0 32 BGCMAR BGCMAR background CLUT memory address register 0x30 0x20 read-write 0x00000000 MA Memory address 0 32 OPFCCR OPFCCR output PFC control register 0x34 0x20 read-write 0x00000000 CM Color mode 0 3 OCOLR OCOLR output color register 0x38 0x20 read-write 0x00000000 APLHA Alpha Channel Value 24 8 RED Red Value 16 8 GREEN Green Value 8 8 BLUE Blue Value 0 8 OMAR OMAR output memory address register 0x3C 0x20 read-write 0x00000000 MA Memory Address 0 32 OOR OOR output offset register 0x40 0x20 read-write 0x00000000 LO Line Offset 0 14 NLR NLR number of line register 0x44 0x20 read-write 0x00000000 PL Pixel per lines 16 14 NL Number of lines 0 16 LWR LWR line watermark register 0x48 0x20 read-write 0x00000000 LW Line watermark 0 16 AMTCR AMTCR AHB master timer configuration register 0x4C 0x20 read-write 0x00000000 DT Dead Time 8 8 EN Enable 0 1 FGCLUT FGCLUT FGCLUT 0x400 0x20 read-write 0x00000000 APLHA APLHA 24 8 RED RED 16 8 GREEN GREEN 8 8 BLUE BLUE 0 8 BGCLUT BGCLUT BGCLUT 0x800 0x20 read-write 0x00000000 APLHA APLHA 24 8 RED RED 16 8 GREEN GREEN 8 8 BLUE BLUE 0 8 I2C3 0x40005C00 I2C3_EV I2C3 event interrupt 72 I2C3_EV I2C3 event interrupt 72 I2C3_ER I2C3 error interrupt 73 I2C3_ER I2C3 error interrupt 73 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 33 I2C2_EV I2C2 event interrupt 33 I2C2_ER I2C2 error interrupt 34 I2C2_ER I2C2 error interrupt 34 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 31 I2C1_EV I2C1 event interrupt 31 I2C1_ER I2C1 error interrupt 32 I2C1_ER I2C1 error interrupt 32 CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 SWRST Software reset 15 1 SWRSTread-writeNotResetI2C peripheral not under reset0ResetI2C peripheral under reset1 ALERT SMBus alert 13 1 ALERTread-writeReleaseSMBA pin released high0DriveSMBA pin driven low1 PEC Packet error checking 12 1 PECread-writeDisabledNo PEC transfer0EnabledPEC transfer1 POS Acknowledge/PEC Position (for data reception) 11 1 POSread-writeCurrentACK bit controls the (N)ACK of the current byte being received0NextACK bit controls the (N)ACK of the next byte to be received1 ACK Acknowledge enable 10 1 ACKread-writeNAKNo acknowledge returned0ACKAcknowledge returned after a byte is received1 STOP Stop generation 9 1 STOPread-writeNoStopNo Stop generation0StopIn master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte1 START Start generation 8 1 STARTread-writeNoStartNo Start generation0StartIn master mode: repeated start generation, in slave mode: start generation when bus is free1 NOSTRETCH Clock stretching disable (Slave mode) 7 1 NOSTRETCHread-writeEnabledClock stretching enabled0DisabledClock stretching disabled1 ENGC General call enable 6 1 ENGCread-writeDisabledGeneral call disabled0EnabledGeneral call enabled1 ENPEC PEC enable 5 1 ENPECread-writeDisabledPEC calculation disabled0EnabledPEC calculation enabled1 ENARP ARP enable 4 1 ENARPread-writeDisabledARP disabled0EnabledARP enabled1 SMBTYPE SMBus type 3 1 SMBTYPEread-writeDeviceSMBus Device0HostSMBus Host1 SMBUS SMBus mode 1 1 SMBUSread-writeI2CI2C Mode0SMBusSMBus1 PE Peripheral enable 0 1 PEread-writeDisabledPeripheral disabled0EnabledPeripheral enabled1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 LAST DMA last transfer 12 1 LASTread-writeNotLastNext DMA EOT is not the last transfer0LastNext DMA EOT is the last transfer1 DMAEN DMA requests enable 11 1 DMAENread-writeDisabledDMA requests disabled0EnabledDMA request enabled when TxE=1 or RxNE=11 ITBUFEN Buffer interrupt enable 10 1 ITBUFENread-writeDisabledTxE=1 or RxNE=1 does not generate any interrupt0EnabledTxE=1 or RxNE=1 generates Event interrupt1 ITEVTEN Event interrupt enable 9 1 ITEVTENread-writeDisabledEvent interrupt disabled0EnabledEvent interrupt enabled1 ITERREN Error interrupt enable 8 1 ITERRENread-writeDisabledError interrupt disabled0EnabledError interrupt enabled1 FREQ Peripheral clock frequency 0 6 250 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x0000 ADDMODE Addressing mode (slave mode) 15 1 ADDMODEread-writeADD77-bit slave address0ADD1010-bit slave address1 ADDInterface address01001023 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x0000 ADD2 Interface address 1 7 0127 ENDUAL Dual addressing mode enable 0 1 ENDUALread-writeSingleSingle addressing mode0DualDual addressing mode1 DR DR Data register 0x10 0x20 read-write 0x0000 DR 8-bit data register 0 8 0255 SR1 SR1 Status register 1 0x14 0x20 0x0000 SMBALERT SMBus alert 15 1 read-write SMBALERTread-writeNoAlertNo SMBALERT occured0AlertSMBALERT occurred1 TIMEOUT Timeout or Tlow error 14 1 read-write TIMEOUTread-writeNoTimeoutNo Timeout error0TimeoutSCL remained LOW for 25 ms1 PECERR PEC Error in reception 12 1 read-write PECERRread-writeNoErrorno PEC error: receiver returns ACK after PEC reception (if ACK=1)0ErrorPEC error: receiver returns NACK after PEC reception (whatever ACK)1 OVR Overrun/Underrun 11 1 read-write OVRread-writeNoOverrunNo overrun/underrun occured0OverrunOverrun/underrun occured1 AF Acknowledge failure 10 1 read-write AFread-writeNoFailureNo acknowledge failure0FailureAcknowledge failure1 ARLO Arbitration lost (master mode) 9 1 read-write ARLOread-writeNoLostNo Arbitration Lost detected0LostArbitration Lost detected1 BERR Bus error 8 1 read-write BERRread-writeNoErrorNo misplaced Start or Stop condition0ErrorMisplaced Start or Stop condition1 TxE Data register empty (transmitters) 7 1 read-only TxEread-writeNotEmptyData register not empty0EmptyData register empty1 RxNE Data register not empty (receivers) 6 1 read-only RxNEread-writeEmptyData register empty0NotEmptyData register not empty1 STOPF Stop detection (slave mode) 4 1 read-only STOPFread-writeNoStopNo Stop condition detected0StopStop condition detected1 ADD10 10-bit header sent (Master mode) 3 1 read-only BTF Byte transfer finished 2 1 read-only BTFread-writeNotFinishedData byte transfer not done0FinishedData byte transfer successful1 ADDR Address sent (master mode)/matched (slave mode) 1 1 read-only ADDRread-writeNotMatchAdress mismatched or not received0MatchReceived slave address matched with one of the enabled slave addresses1 SB Start bit (Master mode) 0 1 read-only SBread-writeNoStartNo Start condition0StartStart condition generated1 SR2 SR2 Status register 2 0x18 0x20 read-only 0x0000 PEC acket error checking register 8 8 DUALF Dual flag (Slave mode) 7 1 SMBHOST SMBus host header (Slave mode) 6 1 SMBDEFAULT SMBus device default address (Slave mode) 5 1 GENCALL General call address (Slave mode) 4 1 TRA Transmitter/receiver 2 1 BUSY Bus busy 1 1 MSL Master/slave 0 1 CCR CCR Clock control register 0x1C 0x20 read-write 0x0000 F_S I2C master mode selection 15 1 F_Sread-writeStandardStandard mode I2C0FastFast mode I2C1 DUTY Fast mode duty cycle 14 1 DUTYread-writeDuty2_1Duty cycle t_low/t_high = 2/10Duty16_9Duty cycle t_low/t_high = 16/91 CCR Clock control register in Fast/Standard mode (Master mode) 0 12 14095 TRISE TRISE TRISE register 0x20 0x20 read-write 0x0002 TRISE Maximum rise time in Fast/Standard mode (Master mode) 0 6 063 FLTR FLTR I2C FLTR register 0x24 0x20 read-write 0x0000 DNF Digital noise filter 0 4 DNFread-writeNoFilterDigital filter disabled0Filter1Digital filter enabled and filtering capability up to 1 tI2CCLK1Filter2Digital filter enabled and filtering capability up to 2 tI2CCLK2Filter3Digital filter enabled and filtering capability up to 3 tI2CCLK3Filter4Digital filter enabled and filtering capability up to 4 tI2CCLK4Filter5Digital filter enabled and filtering capability up to 5 tI2CCLK5Filter6Digital filter enabled and filtering capability up to 6 tI2CCLK6Filter7Digital filter enabled and filtering capability up to 7 tI2CCLK7Filter8Digital filter enabled and filtering capability up to 8 tI2CCLK8Filter9Digital filter enabled and filtering capability up to 9 tI2CCLK9Filter10Digital filter enabled and filtering capability up to 10 tI2CCLK10Filter11Digital filter enabled and filtering capability up to 11 tI2CCLK11Filter12Digital filter enabled and filtering capability up to 12 tI2CCLK12Filter13Digital filter enabled and filtering capability up to 13 tI2CCLK13Filter14Digital filter enabled and filtering capability up to 14 tI2CCLK14Filter15Digital filter enabled and filtering capability up to 15 tI2CCLK15 ANOFF Analog noise filter OFF 4 1 ANOFFread-writeEnabledAnalog noise filter enabled0DisabledAnalog noise filter disabled1 FPU Floting point unit FPU 0xE000EF34 0x0 0xD registers FPUFloating point unit81 FPCCR FPCCR Floating-point context control register 0x0 0x20 read-write 0x00000000 LSPACT LSPACT 0 1 USER USER 1 1 THREAD THREAD 3 1 HFRDY HFRDY 4 1 MMRDY MMRDY 5 1 BFRDY BFRDY 6 1 MONRDY MONRDY 8 1 LSPEN LSPEN 30 1 ASPEN ASPEN 31 1 FPCAR FPCAR Floating-point context address register 0x4 0x20 read-write 0x00000000 ADDRESS Location of unpopulated floating-point 3 29 FPSCR FPSCR Floating-point status control register 0x8 0x20 read-write 0x00000000 IOC Invalid operation cumulative exception bit 0 1 DZC Division by zero cumulative exception bit. 1 1 OFC Overflow cumulative exception bit 2 1 UFC Underflow cumulative exception bit 3 1 IXC Inexact cumulative exception bit 4 1 IDC Input denormal cumulative exception bit. 7 1 RMode Rounding Mode control field 22 2 FZ Flush-to-zero mode control bit: 24 1 DN Default NaN mode control bit 25 1 AHP Alternative half-precision control bit 26 1 V Overflow condition code flag 28 1 C Carry condition code flag 29 1 Z Zero condition code flag 30 1 N Negative condition code flag 31 1 MPU Memory protection unit MPU 0xE000ED90 0x0 0x15 registers TYPER TYPER MPU type register 0x0 0x20 read-only 0X00000800 SEPARATE Separate flag 0 1 DREGION Number of MPU data regions 8 8 IREGION Number of MPU instruction regions 16 8 CTRL CTRL MPU control register 0x4 0x20 read-only 0X00000000 ENABLE Enables the MPU 0 1 HFNMIENA Enables the operation of MPU during hard fault 1 1 PRIVDEFENA Enable priviliged software access to default memory map 2 1 RNR RNR MPU region number register 0x8 0x20 read-write 0X00000000 REGION MPU region 0 8 RBAR RBAR MPU region base address register 0xC 0x20 read-write 0X00000000 REGION MPU region field 0 4 VALID MPU region number valid 4 1 ADDR Region base address field 5 27 RASR RASR MPU region attribute and size register 0x10 0x20 read-write 0X00000000 ENABLE Region enable bit. 0 1 SIZE Size of the MPU protection region 1 5 SRD Subregion disable bits 8 8 B memory attribute 16 1 C memory attribute 17 1 S Shareable memory attribute 18 1 TEX memory attribute 19 3 AP Access permission 24 3 XN Instruction access disable bit 28 1 STK SysTick timer STK 0xE000E010 0x0 0x11 registers CTRL CTRL SysTick control and status register 0x0 0x20 read-write 0X00000000 ENABLE Counter enable 0 1 TICKINT SysTick exception request enable 1 1 CLKSOURCE Clock source selection 2 1 COUNTFLAG COUNTFLAG 16 1 LOAD LOAD SysTick reload value register 0x4 0x20 read-write 0X00000000 RELOAD RELOAD value 0 24 VAL VAL SysTick current value register 0x8 0x20 read-write 0X00000000 CURRENT Current counter value 0 24 CALIB CALIB SysTick calibration value register 0xC 0x20 read-write 0X00000000 TENMS Calibration value 0 24 SKEW SKEW flag: Indicates whether the TENMS value is exact 30 1 NOREF NOREF flag. Reads as zero 31 1 SCB System control block SCB 0xE000ED00 0x0 0x41 registers CPUID CPUID CPUID base register 0x0 0x20 read-only 0x410FC241 Revision Revision number 0 4 PartNo Part number of the processor 4 12 Constant Reads as 0xF 16 4 Variant Variant number 20 4 Implementer Implementer code 24 8 ICSR ICSR Interrupt control and state register 0x4 0x20 read-write 0x00000000 VECTACTIVE Active vector 0 9 RETTOBASE Return to base level 11 1 VECTPENDING Pending vector 12 7 ISRPENDING Interrupt pending flag 22 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVSET PendSV set-pending bit 28 1 NMIPENDSET NMI set-pending bit. 31 1 VTOR VTOR Vector table offset register 0x8 0x20 read-write 0x00000000 TBLOFF Vector table base offset field 9 21 AIRCR AIRCR Application interrupt and reset control register 0xC 0x20 read-write 0x00000000 VECTRESET VECTRESET 0 1 VECTCLRACTIVE VECTCLRACTIVE 1 1 SYSRESETREQ SYSRESETREQ 2 1 PRIGROUP PRIGROUP 8 3 ENDIANESS ENDIANESS 15 1 VECTKEYSTAT Register key 16 16 SCR SCR System control register 0x10 0x20 read-write 0x00000000 SLEEPONEXIT SLEEPONEXIT 1 1 SLEEPDEEP SLEEPDEEP 2 1 SEVEONPEND Send Event on Pending bit 4 1 CCR CCR Configuration and control register 0x14 0x20 read-write 0x00000000 NONBASETHRDENA Configures how the processor enters Thread mode 0 1 USERSETMPEND USERSETMPEND 1 1 UNALIGN__TRP UNALIGN_ TRP 3 1 DIV_0_TRP DIV_0_TRP 4 1 BFHFNMIGN BFHFNMIGN 8 1 STKALIGN STKALIGN 9 1 SHPR1 SHPR1 System handler priority registers 0x18 0x20 read-write 0x00000000 PRI_4 Priority of system handler 4 0 8 PRI_5 Priority of system handler 5 8 8 PRI_6 Priority of system handler 6 16 8 SHPR2 SHPR2 System handler priority registers 0x1C 0x20 read-write 0x00000000 PRI_11 Priority of system handler 11 24 8 SHPR3 SHPR3 System handler priority registers 0x20 0x20 read-write 0x00000000 PRI_14 Priority of system handler 14 16 8 PRI_15 Priority of system handler 15 24 8 SHCRS SHCRS System handler control and state register 0x24 0x20 read-write 0x00000000 MEMFAULTACT Memory management fault exception active bit 0 1 BUSFAULTACT Bus fault exception active bit 1 1 USGFAULTACT Usage fault exception active bit 3 1 SVCALLACT SVC call active bit 7 1 MONITORACT Debug monitor active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTPENDED Usage fault exception pending bit 12 1 MEMFAULTPENDED Memory management fault exception pending bit 13 1 BUSFAULTPENDED Bus fault exception pending bit 14 1 SVCALLPENDED SVC call pending bit 15 1 MEMFAULTENA Memory management fault enable bit 16 1 BUSFAULTENA Bus fault enable bit 17 1 USGFAULTENA Usage fault enable bit 18 1 CFSR_UFSR_BFSR_MMFSR CFSR_UFSR_BFSR_MMFSR Configurable fault status register 0x28 0x20 read-write 0x00000000 IACCVIOL Instruction access violation flag 1 1 MUNSTKERR Memory manager fault on unstacking for a return from exception 3 1 MSTKERR Memory manager fault on stacking for exception entry. 4 1 MLSPERR MLSPERR 5 1 MMARVALID Memory Management Fault Address Register (MMAR) valid flag 7 1 IBUSERR Instruction bus error 8 1 PRECISERR Precise data bus error 9 1 IMPRECISERR Imprecise data bus error 10 1 UNSTKERR Bus fault on unstacking for a return from exception 11 1 STKERR Bus fault on stacking for exception entry 12 1 LSPERR Bus fault on floating-point lazy state preservation 13 1 BFARVALID Bus Fault Address Register (BFAR) valid flag 15 1 UNDEFINSTR Undefined instruction usage fault 16 1 INVSTATE Invalid state usage fault 17 1 INVPC Invalid PC load usage fault 18 1 NOCP No coprocessor usage fault. 19 1 UNALIGNED Unaligned access usage fault 24 1 DIVBYZERO Divide by zero usage fault 25 1 HFSR HFSR Hard fault status register 0x2C 0x20 read-write 0x00000000 VECTTBL Vector table hard fault 1 1 FORCED Forced hard fault 30 1 DEBUG_VT Reserved for Debug use 31 1 MMFAR MMFAR Memory management fault address register 0x34 0x20 read-write 0x00000000 MMFAR Memory management fault address 0 32 BFAR BFAR Bus fault address register 0x38 0x20 read-write 0x00000000 BFAR Bus fault address 0 32 AFSR AFSR Auxiliary fault status register 0x3C 0x20 read-write 0x00000000 IMPDEF Implementation defined 0 32 NVIC_STIR Nested vectored interrupt controller NVIC 0xE000EF00 0x0 0x5 registers STIR STIR Software trigger interrupt register 0x0 0x20 read-write 0x00000000 INTID Software generated interrupt ID 0 9 FPU_CPACR Floating point unit CPACR FPU 0xE000ED88 0x0 0x5 registers CPACR CPACR Coprocessor access control register 0x0 0x20 read-write 0x0000000 CP CP 20 4 SCB_ACTRL System control block ACTLR SCB 0xE000E008 0x0 0x5 registers ACTRL ACTRL Auxiliary control register 0x0 0x20 read-write 0x00000000 DISMCYCINT DISMCYCINT 0 1 DISDEFWBUF DISDEFWBUF 1 1 DISFOLD DISFOLD 2 1 DISFPCA DISFPCA 8 1 DISOOFP DISOOFP 9 1