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Added example MS/TP port to ATxmega XPLAINED A3BU evaluation board.

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skarg
2015-04-16 13:23:29 +00:00
parent 086840a763
commit fe8e60dd3d
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bacnet-stack/ports/xplained/ASF/xmega/drivers/twi/twi_common.h
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/**
* \file
*
* \brief AVR XMEGA TWI driver common definitions
*
* Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef TWI_COMMON_H
#define TWI_COMMON_H
/* Fix header error in iox32e5.h */
#ifndef TWI_BRIDGEEN_bm
#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */
#endif
#ifndef TWI_BRIDGEEN_bp
#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */
#endif
#ifndef TWI_SFMPEN_bm
#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */
#endif
#ifndef TWI_SFMPEN_bp
#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */
#endif
/* End of: Fix header error in iox32e5.h */
/**
* \defgroup group_xmega_drivers_twi TWI - Two-Wire Interface
*
* See \ref xmega_twi_quickstart
*
* Driver for the Two-Wire Interface (TWI).
* Provides functions for configuring and using the TWI in both master and
* slave mode.
*
* \section xmega_twi_quickstart_guide Quick start guide
* See \ref xmega_twi_quickstart
*
* \{
*/
/*!
* \brief Input parameters when initializing the twi module mode
*/
typedef struct
{
//! The baudrate of the TWI bus.
unsigned long speed;
//! The baudrate register value of the TWI bus.
unsigned long speed_reg;
//! The desired address.
char chip;
}
twi_options_t;
/*!
* \brief Information concerning the data transmission
*/
typedef struct
{
//! TWI chip address to communicate with.
char chip;
//! TWI address/commands to issue to the other chip (node).
uint8_t addr[3];
//! Length of the TWI data address segment (1-3 bytes).
int addr_length;
//! Where to find the data to be written.
void *buffer;
//! How many bytes do we want to write.
unsigned int length;
//! Whether to wait if bus is busy (false) or return immediately (true)
bool no_wait;
}
twi_package_t;
/**
* \}
*/
/**
* \page xmega_twi_quickstart Quick start guide for XMEGA TWI driver
*
* This is the quick start guide for the
*\ref group_xmega_drivers_twi "TWI Driver", with step-by-step instructions on
* how to configure and use the driver for specific use cases.
*
* The section described below can be compiled into e.g. the main application
* loop or any other function that might use the TWI functionality.
*
* \section xmega_twi_quickstart_basic Basic use case of the TWI driver
* In our basic use case, the TWI driver is used to set up internal
* communication between two TWI modules on the XMEGA A1 Xplained board, since
* this is the most simple way to show functionality without external
* dependencies. TWIC is set up in master mode, and TWIF is set up in slave
* mode, and these are connected together on the board by placing a connection
* between SDA/SCL on J1 to SDA/SCL on J4.
*
* \section xmega_twi_qs_use_cases Specific use case for XMEGA E devices
* - \subpage xmega_twi_xmegae
*
* \section xmega_twi_quickstart_prereq Prerequisites
* The \ref sysclk_group module is required to enable the clock to the TWI
* modules. The \ref group_xmega_drivers_twi_twim "TWI Master" driver and
* \ref group_xmega_drivers_twi_twis "TWI Slave" driver must also be included.
*
* \section xmega_twi_quickstart_setup Setup
* When the \ref sysclk_group module has been included, it must be initialized:
* \code
* sysclk_init();
* \endcode
*
* \section xmega_twi_quickstart_use_case Use case
*
* \subsection xmega_twi_quickstart_use_case_example_code Example code
*
* \code
* #define TWI_MASTER TWIC
* #define TWI_MASTER_PORT PORTC
* #define TWI_SLAVE TWIF
* #define TWI_SPEED 50000
* #define TWI_MASTER_ADDR 0x50
* #define TWI_SLAVE_ADDR 0x60
*
* #define DATA_LENGTH 8
*
* TWI_Slave_t slave;
*
* uint8_t data[DATA_LENGTH] = {
* 0x0f, 0x1f, 0x2f, 0x3f, 0x4f, 0x5f, 0x6f, 0x7f
* };
*
* uint8_t recv_data[DATA_LENGTH] = {
* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
* };
*
* twi_options_t m_options = {
* .speed = TWI_SPEED,
* .chip = TWI_MASTER_ADDR,
* .speed_reg = TWI_BAUD(sysclk_get_cpu_hz(), TWI_SPEED)
* };
*
* static void slave_process(void) {
* int i;
*
* for(i = 0; i < DATA_LENGTH; i++) {
* recv_data[i] = slave.receivedData[i];
* }
* }
*
* ISR(TWIF_TWIS_vect) {
* TWI_SlaveInterruptHandler(&slave);
* }
*
* void send_and_recv_twi()
* {
* twi_package_t packet = {
* .addr_length = 0,
* .chip = TWI_SLAVE_ADDR,
* .buffer = (void *)data,
* .length = DATA_LENGTH,
* .no_wait = false
* };
*
* uint8_t i;
*
* TWI_MASTER_PORT.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
* TWI_MASTER_PORT.PIN1CTRL = PORT_OPC_WIREDANDPULL_gc;
*
* irq_initialize_vectors();
*
* sysclk_enable_peripheral_clock(&TWI_MASTER);
* twi_master_init(&TWI_MASTER, &m_options);
* twi_master_enable(&TWI_MASTER);
*
* sysclk_enable_peripheral_clock(&TWI_SLAVE);
* TWI_SlaveInitializeDriver(&slave, &TWI_SLAVE, *slave_process);
* TWI_SlaveInitializeModule(&slave, TWI_SLAVE_ADDR,
* TWI_SLAVE_INTLVL_MED_gc);
*
* for (i = 0; i < TWIS_SEND_BUFFER_SIZE; i++) {
* slave.receivedData[i] = 0;
* }
*
* cpu_irq_enable();
*
* twi_master_write(&TWI_MASTER, &packet);
*
* do {
* // Nothing
* } while(slave.result != TWIS_RESULT_OK);
* }
* \endcode
*
* \subsection xmega_twi_quickstart_use_case_workflow Workflow
* We first create some definitions. TWI master and slave, speed, and
* addresses:
* \code
* #define TWI_MASTER TWIC
* #define TWI_MASTER_PORT PORTC
* #define TWI_SLAVE TWIF
* #define TWI_SPEED 50000
* #define TWI_MASTER_ADDR 0x50
* #define TWI_SLAVE_ADDR 0x60
*
* #define DATA_LENGTH 8
* \endcode
*
* We create a handle to contain information about the slave module:
* \code
* TWI_Slave_t slave;
* \endcode
*
* We create two variables, one which contains data that will be transmitted,
* and one which will contain the received data:
* \code
* uint8_t data[DATA_LENGTH] = {
* 0x0f, 0x1f, 0x2f, 0x3f, 0x4f, 0x5f, 0x6f, 0x7f
* };
*
* uint8_t recv_data[DATA_LENGTH] = {
* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
* };
* \endcode
*
* Options for the TWI module initialization procedure are given below:
* \code
* twi_options_t m_options = {
* .speed = TWI_SPEED,
* .chip = TWI_MASTER_ADDR,
* .speed_reg = TWI_BAUD(sysclk_get_cpu_hz(), TWI_SPEED)
* };
* \endcode
*
* The TWI slave will fire an interrupt when it has received data, and the
* function below will be called, which will copy the data from the driver
* to our recv_data buffer:
* \code
* static void slave_process(void) {
* int i;
*
* for(i = 0; i < DATA_LENGTH; i++) {
* recv_data[i] = slave.receivedData[i];
* }
* }
* \endcode
*
* Set up the interrupt handler:
* \code
* ISR(TWIF_TWIS_vect) {
* TWI_SlaveInterruptHandler(&slave);
* }
* \endcode
*
* We create a packet for the data that we will send to the slave TWI:
* \code
* twi_package_t packet = {
* .addr_length = 0,
* .chip = TWI_SLAVE_ADDR,
* .buffer = (void *)data,
* .length = DATA_LENGTH,
* .no_wait = false
* };
* \endcode
*
* We need to set SDA/SCL pins for the master TWI to be wired and
* enable pull-up:
* \code
* TWI_MASTER_PORT.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
* TWI_MASTER_PORT.PIN1CTRL = PORT_OPC_WIREDANDPULL_gc;
* \endcode
*
* We enable all interrupt levels:
* \code
* irq_initialize_vectors();
* \endcode
*
* We enable the clock to the master module, and initialize it with the
* options we described before:
* \code
* sysclk_enable_peripheral_clock(&TWI_MASTER);
* twi_master_init(&TWI_MASTER, &m_options);
* twi_master_enable(&TWI_MASTER);
* \endcode
*
* We do the same for the slave, using the slave portion of the driver,
* passing through the slave_process function, its address, and set medium
* interrupt level:
* \code
* sysclk_enable_peripheral_clock(&TWI_SLAVE);
* TWI_SlaveInitializeDriver(&slave, &TWI_SLAVE, *slave_process);
* TWI_SlaveInitializeModule(&slave, TWI_SLAVE_ADDR,
* TWI_SLAVE_INTLVL_MED_gc);
* \endcode
*
* We zero out the receive buffer in the slave handle:
* \code
* for (i = 0; i < TWIS_SEND_BUFFER_SIZE; i++) {
* slave.receivedData[i] = 0;
* }
* \endcode
*
* And enable interrupts:
* \code
* cpu_irq_enable();
* \endcode
*
* Finally, we write our packet through the master TWI module:
* \code
* twi_master_write(&TWI_MASTER, &packet);
* \endcode
*
* We wait for the slave to finish receiving:
* \code
* do {
* // Waiting
* } while(slave.result != TWIS_RESULT_OK);
* \endcode
* \note When the slave has finished receiving, the slave_process()
* function will copy the received data into our recv_data buffer,
* which now contains what was sent through the master.
*
*/
/**
* \page xmega_twi_xmegae XMEGA E TWI additions with Bridge and Fast Mode Plus
*
* XMEGA E TWI module provides two additionnnal features compare to regular
* XMEGA TWI module:
* - Fast Mode Plus communication speed
* - Bridge Mode
*
* The following use case will set up the TWI module to be used in in Fast Mode
* Plus together with bridge mode.
* This use case is similar to the regular XMEGA TWI initialization, it only
* differs by the activation of both Bridge and Fast Mode Plus mode.
*
* \subsection xmegae_twi_quickstart_use_case_example_code Example code
*
* \code
* #define TWI_MASTER TWIC
* #define TWI_MASTER_PORT PORTC
* #define TWI_SLAVE TWIC
* #define TWI_SPEED 1000000
* #define TWI_MASTER_ADDR 0x50
* #define TWI_SLAVE_ADDR 0x50
*
* #define DATA_LENGTH 8
*
* TWI_Slave_t slave;
*
* uint8_t data[DATA_LENGTH] = {
* 0x0f, 0x1f, 0x2f, 0x3f, 0x4f, 0x5f, 0x6f, 0x7f
* };
*
* uint8_t recv_data[DATA_LENGTH] = {
* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
* };
*
* twi_options_t m_options = {
* .speed = TWI_SPEED,
* .chip = TWI_MASTER_ADDR,
* .speed_reg = TWI_BAUD(sysclk_get_cpu_hz(), TWI_SPEED)
* };
*
* static void slave_process(void) {
* int i;
*
* for(i = 0; i < DATA_LENGTH; i++) {
* recv_data[i] = slave.receivedData[i];
* }
* }
*
* ISR(TWIC_TWIS_vect) {
* TWI_SlaveInterruptHandler(&slave);
* }
*
* void send_and_recv_twi()
* {
* twi_package_t packet = {
* .addr_length = 0,
* .chip = TWI_SLAVE_ADDR,
* .buffer = (void *)data,
* .length = DATA_LENGTH,
* .no_wait = false
* };
*
* uint8_t i;
*
* TWI_MASTER_PORT.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
* TWI_MASTER_PORT.PIN1CTRL = PORT_OPC_WIREDANDPULL_gc;
*
* irq_initialize_vectors();
*
* sysclk_enable_peripheral_clock(&TWI_MASTER);
*
* twi_bridge_enable(&TWI_MASTER);
* twi_fast_mode_enable(&TWI_MASTER);
* twi_slave_fast_mode_enable(&TWI_SLAVE);
*
* twi_master_init(&TWI_MASTER, &m_options);
* twi_master_enable(&TWI_MASTER);
*
* sysclk_enable_peripheral_clock(&TWI_SLAVE);
* TWI_SlaveInitializeDriver(&slave, &TWI_SLAVE, *slave_process);
* TWI_SlaveInitializeModule(&slave, TWI_SLAVE_ADDR,
* TWI_SLAVE_INTLVL_MED_gc);
*
* for (i = 0; i < TWIS_SEND_BUFFER_SIZE; i++) {
* slave.receivedData[i] = 0;
* }
*
* cpu_irq_enable();
*
* twi_master_write(&TWI_MASTER, &packet);
*
* do {
* // Nothing
* } while(slave.result != TWIS_RESULT_OK);
* }
* \endcode
*
* \subsection xmegae_twi_quickstart_use_case_workflow Workflow
* We first create some definitions. TWI master and slave, speed, and
* addresses:
* \code
* #define TWI_MASTER TWIC
* #define TWI_MASTER_PORT PORTC
* #define TWI_SLAVE TWIC
* #define TWI_SPEED 1000000
* #define TWI_MASTER_ADDR 0x50
* #define TWI_SLAVE_ADDR 0x50
*
* #define DATA_LENGTH 8
* \endcode
*
* We create a handle to contain information about the slave module:
* \code
* TWI_Slave_t slave;
* \endcode
*
* We create two variables, one which contains data that will be transmitted,
* and one which will contain the received data:
* \code
* uint8_t data[DATA_LENGTH] = {
* 0x0f, 0x1f, 0x2f, 0x3f, 0x4f, 0x5f, 0x6f, 0x7f
* };
*
* uint8_t recv_data[DATA_LENGTH] = {
* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
* };
* \endcode
*
* Options for the TWI module initialization procedure are given below:
* \code
* twi_options_t m_options = {
* .speed = TWI_SPEED,
* .chip = TWI_MASTER_ADDR,
* .speed_reg = TWI_BAUD(sysclk_get_cpu_hz(), TWI_SPEED)
* };
* \endcode
*
* The TWI slave will fire an interrupt when it has received data, and the
* function below will be called, which will copy the data from the driver
* to our recv_data buffer:
* \code
* static void slave_process(void) {
* int i;
*
* for(i = 0; i < DATA_LENGTH; i++) {
* recv_data[i] = slave.receivedData[i];
* }
* }
* \endcode
*
* Set up the interrupt handler:
* \code
* ISR(TWIC_TWIS_vect) {
* TWI_SlaveInterruptHandler(&slave);
* }
* \endcode
*
* We create a packet for the data that we will send to the slave TWI:
* \code
* twi_package_t packet = {
* .addr_length = 0,
* .chip = TWI_SLAVE_ADDR,
* .buffer = (void *)data,
* .length = DATA_LENGTH,
* .no_wait = false
* };
* \endcode
*
* We need to set SDA/SCL pins for the master TWI to be wired and
* enable pull-up:
* \code
* TWI_MASTER_PORT.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
* TWI_MASTER_PORT.PIN1CTRL = PORT_OPC_WIREDANDPULL_gc;
* \endcode
*
* We enable all interrupt levels:
* \code
* irq_initialize_vectors();
* \endcode
*
* We enable the clock to the master module:
* \code
* sysclk_enable_peripheral_clock(&TWI_MASTER);
* \endcode
*
* We enable the global TWI bridge mode as well as the Fast Mode Plus
* communication speed for both master and slave:
* \code
* twi_bridge_enable(&TWI_MASTER);
* twi_fast_mode_enable(&TWI_MASTER);
* twi_slave_fast_mode_enable(&TWI_SLAVE);
* \endcode
*
* Initialize the master module with the options we described before:
* \code
* twi_master_init(&TWI_MASTER, &m_options);
* twi_master_enable(&TWI_MASTER);
* \endcode
*
* We do the same for the slave, using the slave portion of the driver,
* passing through the slave_process function, its address, and set medium
* interrupt level:
* \code
* sysclk_enable_peripheral_clock(&TWI_SLAVE);
* TWI_SlaveInitializeDriver(&slave, &TWI_SLAVE, *slave_process);
* TWI_SlaveInitializeModule(&slave, TWI_SLAVE_ADDR,
* TWI_SLAVE_INTLVL_MED_gc);
* \endcode
*
* We zero out the receive buffer in the slave handle:
* \code
* for (i = 0; i < TWIS_SEND_BUFFER_SIZE; i++) {
* slave.receivedData[i] = 0;
* }
* \endcode
*
* And enable interrupts:
* \code
* cpu_irq_enable();
* \endcode
*
* Finally, we write our packet through the master TWI module:
* \code
* twi_master_write(&TWI_MASTER, &packet);
* \endcode
*
* We wait for the slave to finish receiving:
* \code
* do {
* // Waiting
* } while(slave.result != TWIS_RESULT_OK);
* \endcode
* \note When the slave has finished receiving, the slave_process()
* function will copy the received data into our recv_data buffer,
* which now contains what was sent through the master.
*
*/
#if XMEGA_E
/*! \brief Enable bridge mode on TWIC.
* SDA and SCL are on PORTC for Master and on PORTD for slave
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_bridge_enable (TWI_t * twi)
{
twi->CTRL |= TWI_BRIDGEEN_bm;
}
/*! \brief Disable bridge mode on TWIC.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_bridge_disable (TWI_t * twi)
{
twi->CTRL &= (~TWI_BRIDGEEN_bm);
}
/*! \brief Enable Fast mode plus on TWIC (1MHz).
* FMPEN bit enables 1MHz on master and slave.
* In bridge mode, it enables only 1MHz on master.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_fast_mode_enable (TWI_t * twi)
{
twi->CTRL |= TWI_FMPEN_bm;
}
/*! \brief Disable Fast mode plus on TWIC (1MHz).
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_fast_mode_disable (TWI_t * twi)
{
twi->CTRL &= (~TWI_FMPEN_bm);
}
/*! \brief Enable Fast mode plus for slave.
* If set in bridge mode, it enables 1MHz on slave.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_slave_fast_mode_enable (TWI_t * twi)
{
twi->CTRL |= TWI_SFMPEN_bm;
}
/*! \brief Disable Fast mode plus for slave.
* If reset in bridge mode, it disables 1MHz on slave.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_slave_fast_mode_disable (TWI_t * twi)
{
twi->CTRL &= (~TWI_SFMPEN_bm);
}
#endif
#endif // TWI_COMMON_H
bacnet-stack/ports/xplained/ASF/xmega/drivers/twi/twim.c
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/**
* \file
*
* \brief XMEGA TWI master source file.
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "twim.h"
/* Master Transfer Descriptor */
static struct {
TWI_t *bus; // Bus register interface
twi_package_t *pkg; // Bus message descriptor
int addr_count; // Bus transfer address data counter
unsigned int data_count; // Bus transfer payload data counter
bool read; // Bus transfer direction
bool locked; // Bus busy or unavailable
volatile status_code_t status; // Transfer status
} transfer;
/**
* \internal
*
* \brief TWI Master Interrupt Vectors
*
* The TWI master interrupt request entry points are conditionally compiled
* for the TWI interfaces supported by the XMEGA MCU variant. All of these
* entry points call a common service function, twim_interrupt_handler(),
* to handle bus events. This handler uses the bus interface and message
* parameters specified in the global \c transfer structure.
*/
static void twim_interrupt_handler(void);
#ifdef TWIC
ISR(TWIC_TWIM_vect)
{
twim_interrupt_handler();
}
#endif
#ifdef TWID
ISR(TWID_TWIM_vect)
{
twim_interrupt_handler();
}
#endif
#ifdef TWIE
ISR(TWIE_TWIM_vect)
{
twim_interrupt_handler();
}
#endif
#ifdef TWIF
ISR(TWIF_TWIM_vect)
{
twim_interrupt_handler();
}
#endif
/**
* \internal
*
* \brief Test for an idle bus state.
*
* Software can determine the TWI master bus state (unknown, idle, owner, or
* busy) by reading the bus master status register:
*
* TWI_MASTER_BUSSTATE_UNKNOWN_gc Bus state is unknown.
* TWI_MASTER_BUSSTATE_IDLE_gc Bus state is idle.
* TWI_MASTER_BUSSTATE_OWNER_gc Bus state is owned by the master.
* TWI_MASTER_BUSSTATE_BUSY_gc Bus state is busy.
*
* \param twi Base address of the TWI (i.e. &TWI_t).
*
* \retval true The bus is currently idle.
* \retval false The bus is currently busy.
*/
static inline bool twim_idle(const TWI_t * twi)
{
return ((twi->MASTER.STATUS & TWI_MASTER_BUSSTATE_gm)
== TWI_MASTER_BUSSTATE_IDLE_gc);
}
/**
* \internal
*
* \brief Get exclusive access to global TWI resources.
*
* Wait to acquire bus hardware interface and ISR variables.
*
* \param no_wait Set \c true to return instead of doing busy-wait (spin-lock).
*
* \return STATUS_OK if the bus is acquired, else ERR_BUSY.
*/
static inline status_code_t twim_acquire(bool no_wait)
{
while (transfer.locked) {
if (no_wait) {
return ERR_BUSY;
}
}
irqflags_t const flags = cpu_irq_save();
transfer.locked = true;
transfer.status = OPERATION_IN_PROGRESS;
cpu_irq_restore(flags);
return STATUS_OK;
}
/**
* \internal
*
* \brief Release exclusive access to global TWI resources.
*
* Release bus hardware interface and ISR variables previously locked by
* a call to \ref twim_acquire(). This function will busy-wait for
* pending driver operations to complete.
*
* \return status_code_t
* - STATUS_OK if the transfer completes
* - ERR_BUSY to indicate an unavailable bus
* - ERR_IO_ERROR to indicate a bus transaction error
* - ERR_NO_MEMORY to indicate buffer errors
* - ERR_PROTOCOL to indicate an unexpected bus state
*/
static inline status_code_t twim_release(void)
{
/* First wait for the driver event handler to indicate something
* other than a transfer in-progress, then test the bus interface
* for an Idle bus state.
*/
while (OPERATION_IN_PROGRESS == transfer.status);
while (!twim_idle(transfer.bus)) {
barrier();
}
status_code_t const status = transfer.status;
transfer.locked = false;
return status;
}
/**
* \internal
*
* \brief TWI master write interrupt handler.
*
* Handles TWI transactions (master write) and responses to (N)ACK.
*/
static inline void twim_write_handler(void)
{
TWI_t *const bus = transfer.bus;
twi_package_t *const pkg = transfer.pkg;
if (transfer.addr_count < pkg->addr_length) {
const uint8_t *const data = pkg->addr;
bus->MASTER.DATA = data[transfer.addr_count++];
} else if (transfer.data_count < pkg->length) {
if (transfer.read) {
/* Send repeated START condition (Address|R/W=1). */
bus->MASTER.ADDR |= 0x01;
} else {
const uint8_t *const data = pkg->buffer;
bus->MASTER.DATA = data[transfer.data_count++];
}
} else {
/* Send STOP condition to complete the transaction. */
bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
transfer.status = STATUS_OK;
}
}
/**
* \internal
*
* \brief TWI master read interrupt handler.
*
* This is the master read interrupt handler that takes care of
* reading bytes from the TWI slave.
*/
static inline void twim_read_handler(void)
{
TWI_t *const bus = transfer.bus;
twi_package_t *const pkg = transfer.pkg;
if (transfer.data_count < pkg->length) {
uint8_t *const data = pkg->buffer;
data[transfer.data_count++] = bus->MASTER.DATA;
/* If there is more to read, issue ACK and start a byte read.
* Otherwise, issue NACK and STOP to complete the transaction.
*/
if (transfer.data_count < pkg->length) {
bus->MASTER.CTRLC = TWI_MASTER_CMD_RECVTRANS_gc;
} else {
bus->MASTER.CTRLC = TWI_MASTER_ACKACT_bm | TWI_MASTER_CMD_STOP_gc;
transfer.status = STATUS_OK;
}
} else {
/* Issue STOP and buffer overflow condition. */
bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
transfer.status = ERR_NO_MEMORY;
}
}
/**
* \internal
*
* \brief Common TWI master interrupt service routine.
*
* Check current status and calls the appropriate handler.
*/
static void twim_interrupt_handler(void)
{
uint8_t const master_status = transfer.bus->MASTER.STATUS;
if (master_status & TWI_MASTER_ARBLOST_bm) {
transfer.bus->MASTER.STATUS = master_status | TWI_MASTER_ARBLOST_bm;
transfer.bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
transfer.status = ERR_BUSY;
} else if ((master_status & TWI_MASTER_BUSERR_bm) ||
(master_status & TWI_MASTER_RXACK_bm)) {
transfer.bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
transfer.status = ERR_IO_ERROR;
} else if (master_status & TWI_MASTER_WIF_bm) {
twim_write_handler();
} else if (master_status & TWI_MASTER_RIF_bm) {
twim_read_handler();
} else {
transfer.status = ERR_PROTOCOL;
}
}
/**
* \brief Initialize the twi master module
*
* \param twi Base address of the TWI (i.e. &TWIC).
* \param *opt Options for initializing the twi module
* (see \ref twi_options_t)
* \retval STATUS_OK Transaction is successful
* \retval ERR_INVALID_ARG Invalid arguments in \c opt.
*/
status_code_t twi_master_init(TWI_t * twi,
const twi_options_t * opt)
{
uint8_t const ctrla =
CONF_TWIM_INTLVL | TWI_MASTER_RIEN_bm | TWI_MASTER_WIEN_bm |
TWI_MASTER_ENABLE_bm;
twi->MASTER.BAUD = opt->speed_reg;
twi->MASTER.CTRLA = ctrla;
twi->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc;
transfer.locked = false;
transfer.status = STATUS_OK;
/* Enable configured PMIC interrupt level. */
PMIC.CTRL |= CONF_PMIC_INTLVL;
cpu_irq_enable();
return STATUS_OK;
}
/**
* \brief Perform a TWI master write or read transfer.
*
* This function is a TWI Master write or read transaction.
*
* \param twi Base address of the TWI (i.e. &TWI_t).
* \param package Package information and data
* (see \ref twi_package_t)
* \param read Selects the transfer direction
*
* \return status_code_t
* - STATUS_OK if the transfer completes
* - ERR_BUSY to indicate an unavailable bus
* - ERR_IO_ERROR to indicate a bus transaction error
* - ERR_NO_MEMORY to indicate buffer errors
* - ERR_PROTOCOL to indicate an unexpected bus state
* - ERR_INVALID_ARG to indicate invalid arguments.
*/
status_code_t twi_master_transfer(TWI_t * twi,
const twi_package_t * package,
bool read)
{
/* Do a sanity check on the arguments. */
if ((twi == NULL) || (package == NULL)) {
return ERR_INVALID_ARG;
}
/* Initiate a transaction when the bus is ready. */
status_code_t status = twim_acquire(package->no_wait);
if (STATUS_OK == status) {
transfer.bus = (TWI_t *) twi;
transfer.pkg = (twi_package_t *) package;
transfer.addr_count = 0;
transfer.data_count = 0;
transfer.read = read;
uint8_t const chip = (package->chip) << 1;
if (package->addr_length || (false == read)) {
transfer.bus->MASTER.ADDR = chip;
} else if (read) {
transfer.bus->MASTER.ADDR = chip | 0x01;
}
status = twim_release();
}
return status;
}
bacnet-stack/ports/xplained/ASF/xmega/drivers/twi/twim.h
+168
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@@ -0,0 +1,168 @@
/**
* \file
*
* \brief TWI driver for AVR.
*
* This file defines a useful set of functions for the TWI interface on AVR
* devices.
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _TWIM_H_
#define _TWIM_H_
/**
* \defgroup group_xmega_drivers_twi_twim TWI Master
*
* \ingroup group_xmega_drivers_twi
*
* \{
*/
#ifdef __cplusplus
extern "C"
{
#endif
#include <compiler.h>
#include <status_codes.h>
#include "conf_twim.h"
#include "twi_common.h"
/*! \brief Error Codes for the Module
*
* \deprecated
* This definition is provided for compatibility with existing ASF example
* applications. This module uses the \ref status_code_t values that will
* replace module-specific error codes in ASF drivers.
*/
#define TWI_SUCCESS (STATUS_OK)
/*! Baud register setting calculation. Formula described in datasheet. */
#define TWI_BAUD(F_SYS, F_TWI) ((F_SYS / (2 * F_TWI)) - 5)
/*! \brief Initialize the twi master module
*
* \param twi Base address of the TWI (i.e. &TWIC).
* \param *opt Options for initializing the twi module
* (see \ref twi_options_t)
* \retval STATUS_OK Transaction is successful
* \retval ERR_INVALID_ARG Invalid arguments in \c opt.
*/
status_code_t twi_master_init (TWI_t * twi, const twi_options_t * opt);
/*! \brief Perform a TWI master write or read transfer.
*
* This function is a TWI Master write or read transaction.
*
* \param twi Base address of the TWI (i.e. &TWI_t).
* \param package Package information and data
* (see \ref twi_package_t)
* \param read Selects the transfer direction
*
* \return status_code_t
* - STATUS_OK if the transfer completes
* - ERR_BUSY to indicate an unavailable bus
* - ERR_IO_ERROR to indicate a bus transaction error
* - ERR_NO_MEMORY to indicate buffer errors
* - ERR_PROTOCOL to indicate an unexpected bus state
* - ERR_INVALID_ARG to indicate invalid arguments.
*/
status_code_t twi_master_transfer (TWI_t * twi,
const twi_package_t * package,
bool read);
/*! \brief Read multiple bytes from a TWI compatible slave device
*
* \param twi Base address of the TWI (i.e. &TWI_t).
* \param package Package information and data
* (see \ref twi_package_t)
* \return STATUS_OK If all bytes were read, error code otherwise
*/
static inline status_code_t twi_master_read (TWI_t * twi,
const twi_package_t * package)
{
return twi_master_transfer (twi, package, true);
}
/*! \brief Write multiple bytes to a TWI compatible slave device
*
* \param twi Base address of the TWI (i.e. &TWI_t).
* \param package Package information and data
* (see \ref twi_package_t)
* \return STATUS_OK If all bytes were written, error code otherwise
*/
static inline status_code_t twi_master_write (TWI_t * twi,
const twi_package_t * package)
{
return twi_master_transfer (twi, package, false);
}
/*! \brief Enable Master Mode of the TWI.
*
* \param twi Base address of the TWI instance.
*/
static inline void twi_master_enable (TWI_t * twi)
{
twi->MASTER.CTRLA |= TWI_MASTER_ENABLE_bm;
}
/*! \brief Disable Master Mode of the TWI.
*
* \param twi Base address of the TWI instance.
*/
static inline void twi_master_disable (TWI_t * twi)
{
twi->MASTER.CTRLA &= (~TWI_MASTER_ENABLE_bm);
}
#ifdef __cplusplus
}
#endif
/**
* \}
*/
#endif // _TWIM_H_
bacnet-stack/ports/xplained/ASF/xmega/drivers/twi/twis.c
+330
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/**
* \file *********************************************************************
*
* \brief
* XMEGA TWI slave driver source file.
*
* This file contains the function implementations the XMEGA TWI slave
* driver.
*
* The driver is not intended for size and/or speed critical code, since
* most functions are just a few lines of code, and the function call
* overhead would decrease code performance. The driver is intended for
* rapid prototyping and documentation purposes for getting started with
* the XMEGA TWI slave module.
*
* For size and/or speed critical code, it is recommended to copy the
* function contents directly into your application instead of making
* a function call.
*
* Several functions use the following construct:
* "some_register = ... | (some_parameter ? SOME_BIT_bm : 0) | ..."
* Although the use of the ternary operator ( if ? then : else ) is
* discouraged, in some occasions the operator makes it possible to write
* pretty clean and neat code. In this driver, the construct is used to
* set or not set a configuration bit based on a boolean input parameter,
* such as the "some_parameter" in the example above.
*
* \par Application note:
* AVR1308: Using the XMEGA TWI
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* Atmel Corporation: http://www.atmel.com \n
*
* $Revision: 2660 $
* $Date: 2009-08-11 12:28:58 +0200 (Tue, 11 Aug 2009) $ \n
*
* Copyright (c) 2008 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*****************************************************************************/
#include "twis.h"
/*! \brief Initalizes TWI slave driver structure.
*
* Initialize the instance of the TWI Slave and set the appropriate values.
*
* \param twi The TWI_Slave_t struct instance.
* \param module Pointer to the TWI module.
* \param processDataFunction Pointer to the function that handles incoming data.
*/
void TWI_SlaveInitializeDriver(TWI_Slave_t * twi,
TWI_t * module,
void (*processDataFunction) (void))
{
twi->interface = module;
twi->Process_Data = processDataFunction;
twi->bytesReceived = 0;
twi->bytesSent = 0;
twi->status = TWIS_STATUS_READY;
twi->result = TWIS_RESULT_UNKNOWN;
twi->abort = false;
}
/*! \brief Initialize the TWI module.
*
* Enables interrupts on address recognition and data available.
* Remember to enable interrupts globally from the main application.
*
* \param twi The TWI_Slave_t struct instance.
* \param address Slave address for this module.
* \param intLevel Interrupt level for the TWI slave interrupt handler.
*/
void TWI_SlaveInitializeModule(TWI_Slave_t * twi,
uint8_t address,
TWI_SLAVE_INTLVL_t intLevel)
{
twi->interface->SLAVE.CTRLA =
intLevel | TWI_SLAVE_DIEN_bm | TWI_SLAVE_APIEN_bm |
TWI_SLAVE_ENABLE_bm;
twi->interface->SLAVE.ADDR = (address << 1);
}
/*! \brief Common TWI slave interrupt service routine.
*
* Handles all TWI transactions and responses to address match, data reception,
* data transmission, bus error and data collision.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveInterruptHandler(TWI_Slave_t * twi)
{
uint8_t currentStatus = twi->interface->SLAVE.STATUS;
/* If bus error. */
if (currentStatus & TWI_SLAVE_BUSERR_bm) {
twi->bytesReceived = 0;
twi->bytesSent = 0;
twi->result = TWIS_RESULT_BUS_ERROR;
twi->status = TWIS_STATUS_READY;
}
/* If transmit collision. */
else if (currentStatus & TWI_SLAVE_COLL_bm) {
twi->bytesReceived = 0;
twi->bytesSent = 0;
twi->result = TWIS_RESULT_TRANSMIT_COLLISION;
twi->status = TWIS_STATUS_READY;
}
/* If address match. */
else if ((currentStatus & TWI_SLAVE_APIF_bm) &&
(currentStatus & TWI_SLAVE_AP_bm)) {
TWI_SlaveAddressMatchHandler(twi);
}
/* If stop (only enabled through slave read transaction). */
else if (currentStatus & TWI_SLAVE_APIF_bm) {
TWI_SlaveStopHandler(twi);
}
/* If data interrupt. */
else if (currentStatus & TWI_SLAVE_DIF_bm) {
TWI_SlaveDataHandler(twi);
}
/* If unexpected state. */
else {
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_FAIL);
}
}
/*! \brief TWI address match interrupt handler.
*
* Prepares TWI module for transaction when an address match occurs.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveAddressMatchHandler(TWI_Slave_t * twi)
{
/* If application signalling need to abort (error occured). */
if (twi->abort) {
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_COMPTRANS_gc;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_ABORTED);
twi->abort = false;
} else {
twi->status = TWIS_STATUS_BUSY;
twi->result = TWIS_RESULT_UNKNOWN;
/* Disable stop interrupt. */
uint8_t currentCtrlA = twi->interface->SLAVE.CTRLA;
twi->interface->SLAVE.CTRLA = currentCtrlA & ~TWI_SLAVE_PIEN_bm;
twi->bytesReceived = 0;
twi->bytesSent = 0;
/* Send ACK, wait for data interrupt. */
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_RESPONSE_gc;
}
}
/*! \brief TWI stop condition interrupt handler.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveStopHandler(TWI_Slave_t * twi)
{
/* Disable stop interrupt. */
uint8_t currentCtrlA = twi->interface->SLAVE.CTRLA;
twi->interface->SLAVE.CTRLA = currentCtrlA & ~TWI_SLAVE_PIEN_bm;
/* Clear APIF, according to flowchart don't ACK or NACK */
uint8_t currentStatus = twi->interface->SLAVE.STATUS;
twi->interface->SLAVE.STATUS = currentStatus | TWI_SLAVE_APIF_bm;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_OK);
}
/*! \brief TWI data interrupt handler.
*
* Calls the appropriate slave read or write handler.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveDataHandler(TWI_Slave_t * twi)
{
if (twi->interface->SLAVE.STATUS & TWI_SLAVE_DIR_bm) {
TWI_SlaveWriteHandler(twi);
} else {
TWI_SlaveReadHandler(twi);
}
}
/*! \brief TWI slave read interrupt handler.
*
* Handles TWI slave read transactions and responses.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveReadHandler(TWI_Slave_t * twi)
{
/* Enable stop interrupt. */
uint8_t currentCtrlA = twi->interface->SLAVE.CTRLA;
twi->interface->SLAVE.CTRLA = currentCtrlA | TWI_SLAVE_PIEN_bm;
/* If free space in buffer. */
if (twi->bytesReceived < TWIS_RECEIVE_BUFFER_SIZE) {
/* Fetch data */
uint8_t data = twi->interface->SLAVE.DATA;
twi->receivedData[twi->bytesReceived] = data;
/* Process data. */
twi->Process_Data();
twi->bytesReceived++;
/* If application signalling need to abort (error occured),
* complete transaction and wait for next START. Otherwise
* send ACK and wait for data interrupt.
*/
if (twi->abort) {
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_COMPTRANS_gc;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_ABORTED);
twi->abort = false;
} else {
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_RESPONSE_gc;
}
}
/* If buffer overflow, send NACK and wait for next START. Set
* result buffer overflow.
*/
else {
twi->interface->SLAVE.CTRLB =
TWI_SLAVE_ACKACT_bm | TWI_SLAVE_CMD_COMPTRANS_gc;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_BUFFER_OVERFLOW);
}
}
/*! \brief TWI slave write interrupt handler.
*
* Handles TWI slave write transactions and responses.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveWriteHandler(TWI_Slave_t * twi)
{
/* If NACK, slave write transaction finished. */
if ((twi->bytesSent > 0) &&
(twi->interface->SLAVE.STATUS & TWI_SLAVE_RXACK_bm)) {
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_COMPTRANS_gc;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_OK);
}
/* If ACK, master expects more data. */
else {
if (twi->bytesSent < TWIS_SEND_BUFFER_SIZE) {
uint8_t data = twi->sendData[twi->bytesSent];
twi->interface->SLAVE.DATA = data;
twi->bytesSent++;
/* Send data, wait for data interrupt. */
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_RESPONSE_gc;
}
/* If buffer overflow. */
else {
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_COMPTRANS_gc;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_BUFFER_OVERFLOW);
}
}
}
/*! \brief TWI transaction finished function.
*
* Prepares module for new transaction.
*
* \param twi The TWI_Slave_t struct instance.
* \param result The result of the transaction.
*/
void TWI_SlaveTransactionFinished(TWI_Slave_t * twi,
uint8_t result)
{
twi->result = result;
twi->status = TWIS_STATUS_READY;
}
bacnet-stack/ports/xplained/ASF/xmega/drivers/twi/twis.h
+179
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/**
* \file *********************************************************************
*
* \brief XMEGA TWI slave driver header file.
*
* This file contains the function prototypes and enumerator definitions
* for various configuration parameters for the XMEGA TWI slave driver.
*
* The driver is not intended for size and/or speed critical code, since
* most functions are just a few lines of code, and the function call
* overhead would decrease code performance. The driver is intended for
* rapid prototyping and documentation purposes for getting started with
* the XMEGA TWI slave module.
*
* For size and/or speed critical code, it is recommended to copy the
* function contents directly into your application instead of making
* a function call.
*
* \par Application note:
* AVR1307: Using the XMEGA TWI
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* Atmel Corporation: http://www.atmel.com \n
*
* $Revision: 1569 $
* $Date: 2008-04-22 13:03:43 +0200 (Tue, 22 Apr 2008) $ \n
*
* Copyright (c) 2008 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*****************************************************************************/
#ifndef TWIS_H
#define TWIS_H
/**
* \defgroup group_xmega_drivers_twi_twis TWI Slave
*
* \ingroup group_xmega_drivers_twi
*
* \{
*/
#include "compiler.h"
#include "twi_common.h"
/*! Baud register setting calculation. Formula described in datasheet. */
#define TWI_BAUD(F_SYS, F_TWI) ((F_SYS / (2 * F_TWI)) - 5)
/* Transaction status defines.*/
#define TWIS_STATUS_READY 0
#define TWIS_STATUS_BUSY 1
/* Transaction result enumeration */
typedef enum TWIS_RESULT_enum
{
TWIS_RESULT_UNKNOWN = (0x00 << 0),
TWIS_RESULT_OK = (0x01 << 0),
TWIS_RESULT_BUFFER_OVERFLOW = (0x02 << 0),
TWIS_RESULT_TRANSMIT_COLLISION = (0x03 << 0),
TWIS_RESULT_BUS_ERROR = (0x04 << 0),
TWIS_RESULT_FAIL = (0x05 << 0),
TWIS_RESULT_ABORTED = (0x06 << 0),
}
TWIS_RESULT_t;
/* Buffer size defines. */
#define TWIS_RECEIVE_BUFFER_SIZE 8
#define TWIS_SEND_BUFFER_SIZE 8
/*! \brief TWI slave driver struct.
*
* TWI slave struct. Holds pointer to TWI module and data processing routine,
* buffers and necessary variables.
*/
typedef struct TWI_Slave
{
TWI_t *interface; /*!< Pointer to what interface to use */
void (*Process_Data) (void); /*!< Pointer to process data function */
register8_t receivedData[TWIS_RECEIVE_BUFFER_SIZE]; /*!< Read data */
register8_t sendData[TWIS_SEND_BUFFER_SIZE]; /*!< Data to write */
register8_t bytesReceived; /*!< Number of bytes received */
register8_t bytesSent; /*!< Number of bytes sent */
register8_t status; /*!< Status of transaction */
register8_t result; /*!< Result of transaction */
bool abort; /*!< Strobe to abort */
}
TWI_Slave_t;
void TWI_SlaveInitializeDriver (TWI_Slave_t * twi,
TWI_t * module,
void (*processDataFunction) (void));
void TWI_SlaveInitializeModule (TWI_Slave_t * twi,
uint8_t address, TWI_SLAVE_INTLVL_t intLevel);
void TWI_SlaveInterruptHandler (TWI_Slave_t * twi);
void TWI_SlaveAddressMatchHandler (TWI_Slave_t * twi);
void TWI_SlaveStopHandler (TWI_Slave_t * twi);
void TWI_SlaveDataHandler (TWI_Slave_t * twi);
void TWI_SlaveReadHandler (TWI_Slave_t * twi);
void TWI_SlaveWriteHandler (TWI_Slave_t * twi);
void TWI_SlaveTransactionFinished (TWI_Slave_t * twi, uint8_t result);
/*! TWI slave interrupt service routine.
*
* Interrupt service routine for the TWI slave. Copy the interrupt vector
* into your code if needed.
*
ISR(TWIC_TWIS_vect)
{
TWI_SlaveInterruptHandler(&twiSlaveC);
}
*
*/
/*! \brief Enable Slave Mode of the TWI.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_slave_enable (TWI_t * twi)
{
twi->SLAVE.CTRLA |= TWI_SLAVE_ENABLE_bm;
}
/*! \brief Disable Slave Mode of the TWI.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_slave_disable (TWI_t * twi)
{
twi->SLAVE.CTRLA &= (~TWI_SLAVE_ENABLE_bm);
}
/**
* \}
*/
#endif /* TWIS_H */