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Added example MS/TP port to ATxmega XPLAINED A3BU evaluation board.

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skarg
2015-04-16 13:23:29 +00:00
parent 086840a763
commit fe8e60dd3d
107 changed files with 33116 additions and 0 deletions
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bacnet-stack/ports/xplained/ASF/common/services/clock/genclk.h
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/**
* \file
*
* \brief Generic clock management
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef CLK_GENCLK_H_INCLUDED
#define CLK_GENCLK_H_INCLUDED
#include "parts.h"
#if SAM3S
# include "sam3s/genclk.h"
#elif SAM3U
# include "sam3u/genclk.h"
#elif SAM3N
# include "sam3n/genclk.h"
#elif SAM3XA
# include "sam3x/genclk.h"
#elif SAM4S
# include "sam4s/genclk.h"
#elif SAM4L
# include "sam4l/genclk.h"
#elif SAM4E
# include "sam4e/genclk.h"
#elif (UC3A0 || UC3A1)
# include "uc3a0_a1/genclk.h"
#elif UC3A3
# include "uc3a3_a4/genclk.h"
#elif UC3B
# include "uc3b0_b1/genclk.h"
#elif UC3C
# include "uc3c/genclk.h"
#elif UC3D
# include "uc3d/genclk.h"
#elif UC3L
# include "uc3l/genclk.h"
#else
# error Unsupported chip type
#endif
/**
* \ingroup clk_group
* \defgroup genclk_group Generic Clock Management
*
* Generic clocks are configurable clocks which run outside the system
* clock domain. They are often connected to peripherals which have an
* asynchronous component running independently of the bus clock, e.g.
* USB controllers, low-power timers and RTCs, etc.
*
* Note that not all platforms have support for generic clocks; on such
* platforms, this API will not be available.
*
* @{
*/
/**
* \def GENCLK_DIV_MAX
* \brief Maximum divider supported by the generic clock implementation
*/
/**
* \enum genclk_source
* \brief Generic clock source ID
*
* Each generic clock may be generated from a different clock source.
* These are the available alternatives provided by the chip.
*/
//! \name Generic clock configuration
//@{
/**
* \struct genclk_config
* \brief Hardware representation of a set of generic clock parameters
*/
/**
* \fn void genclk_config_defaults(struct genclk_config *cfg,
* unsigned int id)
* \brief Initialize \a cfg to the default configuration for the clock
* identified by \a id.
*/
/**
* \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id)
* \brief Read the currently active configuration of the clock
* identified by \a id into \a cfg.
*/
/**
* \fn void genclk_config_write(const struct genclk_config *cfg,
* unsigned int id)
* \brief Activate the configuration \a cfg on the clock identified by
* \a id.
*/
/**
* \fn void genclk_config_set_source(struct genclk_config *cfg,
* enum genclk_source src)
* \brief Select a new source clock \a src in configuration \a cfg.
*/
/**
* \fn void genclk_config_set_divider(struct genclk_config *cfg,
* unsigned int divider)
* \brief Set a new \a divider in configuration \a cfg.
*/
/**
* \fn void genclk_enable_source(enum genclk_source src)
* \brief Enable the source clock \a src used by a generic clock.
*/
//@}
//! \name Enabling and disabling Generic Clocks
//@{
/**
* \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id)
* \brief Activate the configuration \a cfg on the clock identified by
* \a id and enable it.
*/
/**
* \fn void genclk_disable(unsigned int id)
* \brief Disable the generic clock identified by \a id.
*/
//@}
/**
* \brief Enable the configuration defined by \a src and \a divider
* for the generic clock identified by \a id.
*
* \param id The ID of the generic clock.
* \param src The source clock of the generic clock.
* \param divider The divider used to generate the generic clock.
*/
static inline void
genclk_enable_config (unsigned int id, enum genclk_source src,
unsigned int divider)
{
struct genclk_config gcfg;
genclk_config_defaults (&gcfg, id);
genclk_enable_source (src);
genclk_config_set_source (&gcfg, src);
genclk_config_set_divider (&gcfg, divider);
genclk_enable (&gcfg, id);
}
//! @}
#endif /* CLK_GENCLK_H_INCLUDED */
bacnet-stack/ports/xplained/ASF/common/services/clock/osc.h
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/**
* \file
*
* \brief Oscillator management
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef OSC_H_INCLUDED
#define OSC_H_INCLUDED
#include "parts.h"
#include "conf_clock.h"
#if SAM3S
# include "sam3s/osc.h"
#elif SAM3XA
# include "sam3x/osc.h"
#elif SAM3U
# include "sam3u/osc.h"
#elif SAM3N
# include "sam3n/osc.h"
#elif SAM4S
# include "sam4s/osc.h"
#elif SAM4E
# include "sam4e/osc.h"
#elif SAM4L
# include "sam4l/osc.h"
#elif (UC3A0 || UC3A1)
# include "uc3a0_a1/osc.h"
#elif UC3A3
# include "uc3a3_a4/osc.h"
#elif UC3B
# include "uc3b0_b1/osc.h"
#elif UC3C
# include "uc3c/osc.h"
#elif UC3D
# include "uc3d/osc.h"
#elif UC3L
# include "uc3l/osc.h"
#elif XMEGA
# include "xmega/osc.h"
#else
# error Unsupported chip type
#endif
/**
* \ingroup clk_group
* \defgroup osc_group Oscillator Management
*
* This group contains functions and definitions related to configuring
* and enabling/disabling on-chip oscillators. Internal RC-oscillators,
* external crystal oscillators and external clock generators are
* supported by this module. What all of these have in common is that
* they swing at a fixed, nominal frequency which is normally not
* adjustable.
*
* \par Example: Enabling an oscillator
*
* The following example demonstrates how to enable the external
* oscillator on XMEGA A and wait for it to be ready to use. The
* oscillator identifiers are platform-specific, so while the same
* procedure is used on all platforms, the parameter to osc_enable()
* will be different from device to device.
* \code
osc_enable(OSC_ID_XOSC);
osc_wait_ready(OSC_ID_XOSC); \endcode
*
* \section osc_group_board Board-specific Definitions
* If external oscillators are used, the board code must provide the
* following definitions for each of those:
* - \b BOARD_<osc name>_HZ: The nominal frequency of the oscillator.
* - \b BOARD_<osc name>_STARTUP_US: The startup time of the
* oscillator in microseconds.
* - \b BOARD_<osc name>_TYPE: The type of oscillator connected, i.e.
* whether it's a crystal or external clock, and sometimes what kind
* of crystal it is. The meaning of this value is platform-specific.
*
* @{
*/
//! \name Oscillator Management
//@{
/**
* \fn void osc_enable(uint8_t id)
* \brief Enable oscillator \a id
*
* The startup time and mode value is automatically determined based on
* definitions in the board code.
*/
/**
* \fn void osc_disable(uint8_t id)
* \brief Disable oscillator \a id
*/
/**
* \fn osc_is_ready(uint8_t id)
* \brief Determine whether oscillator \a id is ready.
* \retval true Oscillator \a id is running and ready to use as a clock
* source.
* \retval false Oscillator \a id is not running.
*/
/**
* \fn uint32_t osc_get_rate(uint8_t id)
* \brief Return the frequency of oscillator \a id in Hz
*/
#ifndef __ASSEMBLY__
/**
* \brief Wait until the oscillator identified by \a id is ready
*
* This function will busy-wait for the oscillator identified by \a id
* to become stable and ready to use as a clock source.
*
* \param id A number identifying the oscillator to wait for.
*/
static inline void
osc_wait_ready (uint8_t id)
{
while (!osc_is_ready (id))
{
/* Do nothing */
}
}
#endif /* __ASSEMBLY__ */
//@}
//! @}
#endif /* OSC_H_INCLUDED */
bacnet-stack/ports/xplained/ASF/common/services/clock/pll.h
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/**
* \file
*
* \brief PLL management
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef CLK_PLL_H_INCLUDED
#define CLK_PLL_H_INCLUDED
#include "parts.h"
#include "conf_clock.h"
#if SAM3S
# include "sam3s/pll.h"
#elif SAM3XA
# include "sam3x/pll.h"
#elif SAM3U
# include "sam3u/pll.h"
#elif SAM3N
# include "sam3n/pll.h"
#elif SAM4S
# include "sam4s/pll.h"
#elif SAM4E
# include "sam4e/pll.h"
#elif SAM4L
# include "sam4l/pll.h"
#elif (UC3A0 || UC3A1)
# include "uc3a0_a1/pll.h"
#elif UC3A3
# include "uc3a3_a4/pll.h"
#elif UC3B
# include "uc3b0_b1/pll.h"
#elif UC3C
# include "uc3c/pll.h"
#elif UC3D
# include "uc3d/pll.h"
#elif (UC3L0128 || UC3L0256 || UC3L3_L4)
# include "uc3l/pll.h"
#elif XMEGA
# include "xmega/pll.h"
#else
# error Unsupported chip type
#endif
/**
* \ingroup clk_group
* \defgroup pll_group PLL Management
*
* This group contains functions and definitions related to configuring
* and enabling/disabling on-chip PLLs. A PLL will take an input signal
* (the \em source), optionally divide the frequency by a configurable
* \em divider, and then multiply the frequency by a configurable \em
* multiplier.
*
* Some devices don't support input dividers; specifying any other
* divisor than 1 on these devices will result in an assertion failure.
* Other devices may have various restrictions to the frequency range of
* the input and output signals.
*
* \par Example: Setting up PLL0 with default parameters
*
* The following example shows how to configure and enable PLL0 using
* the default parameters specified using the configuration symbols
* listed above.
* \code
pll_enable_config_defaults(0); \endcode
*
* To configure, enable PLL0 using the default parameters and to disable
* a specific feature like Wide Bandwidth Mode (a UC3A3-specific
* PLL option.), you can use this initialization process.
* \code
struct pll_config pllcfg;
if (pll_is_locked(pll_id)) {
return; // Pll already running
}
pll_enable_source(CONFIG_PLL0_SOURCE);
pll_config_defaults(&pllcfg, 0);
pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
pll_enable(&pllcfg, 0);
pll_wait_for_lock(0); \endcode
*
* When the last function call returns, PLL0 is ready to be used as the
* main system clock source.
*
* \section pll_group_config Configuration Symbols
*
* Each PLL has a set of default parameters determined by the following
* configuration symbols in the application's configuration file:
* - \b CONFIG_PLLn_SOURCE: The default clock source connected to the
* input of PLL \a n. Must be one of the values defined by the
* #pll_source enum.
* - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL
* \a n.
* - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n.
*
* These configuration symbols determine the result of calling
* pll_config_defaults() and pll_get_default_rate().
*
* @{
*/
//! \name Chip-specific PLL characteristics
//@{
/**
* \def PLL_MAX_STARTUP_CYCLES
* \brief Maximum PLL startup time in number of slow clock cycles
*/
/**
* \def NR_PLLS
* \brief Number of on-chip PLLs
*/
/**
* \def PLL_MIN_HZ
* \brief Minimum frequency that the PLL can generate
*/
/**
* \def PLL_MAX_HZ
* \brief Maximum frequency that the PLL can generate
*/
/**
* \def PLL_NR_OPTIONS
* \brief Number of PLL option bits
*/
//@}
/**
* \enum pll_source
* \brief PLL clock source
*/
//! \name PLL configuration
//@{
/**
* \struct pll_config
* \brief Hardware-specific representation of PLL configuration.
*
* This structure contains one or more device-specific values
* representing the current PLL configuration. The contents of this
* structure is typically different from platform to platform, and the
* user should not access any fields except through the PLL
* configuration API.
*/
/**
* \fn void pll_config_init(struct pll_config *cfg,
* enum pll_source src, unsigned int div, unsigned int mul)
* \brief Initialize PLL configuration from standard parameters.
*
* \note This function may be defined inline because it is assumed to be
* called very few times, and usually with constant parameters. Inlining
* it will in such cases reduce the code size significantly.
*
* \param cfg The PLL configuration to be initialized.
* \param src The oscillator to be used as input to the PLL.
* \param div PLL input divider.
* \param mul PLL loop divider (i.e. multiplier).
*
* \return A configuration which will make the PLL run at
* (\a mul / \a div) times the frequency of \a src
*/
/**
* \def pll_config_defaults(cfg, pll_id)
* \brief Initialize PLL configuration using default parameters.
*
* After this function returns, \a cfg will contain a configuration
* which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV)
* times the frequency of CONFIG_PLLx_SOURCE.
*
* \param cfg The PLL configuration to be initialized.
* \param pll_id Use defaults for this PLL.
*/
/**
* \def pll_get_default_rate(pll_id)
* \brief Get the default rate in Hz of \a pll_id
*/
/**
* \fn void pll_config_set_option(struct pll_config *cfg,
* unsigned int option)
* \brief Set the PLL option bit \a option in the configuration \a cfg.
*
* \param cfg The PLL configuration to be changed.
* \param option The PLL option bit to be set.
*/
/**
* \fn void pll_config_clear_option(struct pll_config *cfg,
* unsigned int option)
* \brief Clear the PLL option bit \a option in the configuration \a cfg.
*
* \param cfg The PLL configuration to be changed.
* \param option The PLL option bit to be cleared.
*/
/**
* \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id)
* \brief Read the currently active configuration of \a pll_id.
*
* \param cfg The configuration object into which to store the currently
* active configuration.
* \param pll_id The ID of the PLL to be accessed.
*/
/**
* \fn void pll_config_write(const struct pll_config *cfg,
* unsigned int pll_id)
* \brief Activate the configuration \a cfg on \a pll_id
*
* \param cfg The configuration object representing the PLL
* configuration to be activated.
* \param pll_id The ID of the PLL to be updated.
*/
//@}
//! \name Interaction with the PLL hardware
//@{
/**
* \fn void pll_enable(const struct pll_config *cfg,
* unsigned int pll_id)
* \brief Activate the configuration \a cfg and enable PLL \a pll_id.
*
* \param cfg The PLL configuration to be activated.
* \param pll_id The ID of the PLL to be enabled.
*/
/**
* \fn void pll_disable(unsigned int pll_id)
* \brief Disable the PLL identified by \a pll_id.
*
* After this function is called, the PLL identified by \a pll_id will
* be disabled. The PLL configuration stored in hardware may be affected
* by this, so if the caller needs to restore the same configuration
* later, it should either do a pll_config_read() before disabling the
* PLL, or remember the last configuration written to the PLL.
*
* \param pll_id The ID of the PLL to be disabled.
*/
/**
* \fn bool pll_is_locked(unsigned int pll_id)
* \brief Determine whether the PLL is locked or not.
*
* \param pll_id The ID of the PLL to check.
*
* \retval true The PLL is locked and ready to use as a clock source
* \retval false The PLL is not yet locked, or has not been enabled.
*/
/**
* \fn void pll_enable_source(enum pll_source src)
* \brief Enable the source of the pll.
* The source is enabled, if the source is not already running.
*
* \param src The ID of the PLL source to enable.
*/
/**
* \fn void pll_enable_config_defaults(unsigned int pll_id)
* \brief Enable the pll with the default configuration.
* PLL is enabled, if the PLL is not already locked.
*
* \param pll_id The ID of the PLL to enable.
*/
/**
* \brief Wait for PLL \a pll_id to become locked
*
* \todo Use a timeout to avoid waiting forever and hanging the system
*
* \param pll_id The ID of the PLL to wait for.
*
* \retval STATUS_OK The PLL is now locked.
* \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.
*/
static inline int
pll_wait_for_lock (unsigned int pll_id)
{
Assert (pll_id < NR_PLLS);
while (!pll_is_locked (pll_id))
{
/* Do nothing */
}
return 0;
}
//@}
//! @}
#endif /* CLK_PLL_H_INCLUDED */
bacnet-stack/ports/xplained/ASF/common/services/clock/sysclk.h
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/**
* \file
*
* \brief System clock management
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SYSCLK_H_INCLUDED
#define SYSCLK_H_INCLUDED
#include "parts.h"
#include "conf_clock.h"
#if SAM3S
# include "sam3s/sysclk.h"
#elif SAM3U
# include "sam3u/sysclk.h"
#elif SAM3N
# include "sam3n/sysclk.h"
#elif SAM3XA
# include "sam3x/sysclk.h"
#elif SAM4S
# include "sam4s/sysclk.h"
#elif SAM4E
# include "sam4e/sysclk.h"
#elif SAM4L
# include "sam4l/sysclk.h"
#elif (UC3A0 || UC3A1)
# include "uc3a0_a1/sysclk.h"
#elif UC3A3
# include "uc3a3_a4/sysclk.h"
#elif UC3B
# include "uc3b0_b1/sysclk.h"
#elif UC3C
# include "uc3c/sysclk.h"
#elif UC3D
# include "uc3d/sysclk.h"
#elif UC3L
# include "uc3l/sysclk.h"
#elif XMEGA
# include "xmega/sysclk.h"
#elif MEGA
# include "mega/sysclk.h"
#else
# error Unsupported chip type
#endif
/**
* \defgroup clk_group Clock Management
*/
/**
* \ingroup clk_group
* \defgroup sysclk_group System Clock Management
*
* See \ref sysclk_quickstart.
*
* The <em>sysclk</em> API covers the <em>system clock</em> and all
* clocks derived from it. The system clock is a chip-internal clock on
* which all <em>synchronous clocks</em>, i.e. CPU and bus/peripheral
* clocks, are based. The system clock is typically generated from one
* of a variety of sources, which may include crystal and RC oscillators
* as well as PLLs. The clocks derived from the system clock are
* sometimes also known as <em>synchronous clocks</em>, since they
* always run synchronously with respect to each other, as opposed to
* <em>generic clocks</em> which may run from different oscillators or
* PLLs.
*
* Most applications should simply call sysclk_init() to initialize
* everything related to the system clock and its source (oscillator,
* PLL or DFLL), and leave it at that. More advanced applications, and
* platform-specific drivers, may require additional services from the
* clock system, some of which may be platform-specific.
*
* \section sysclk_group_platform Platform Dependencies
*
* The sysclk API is partially chip- or platform-specific. While all
* platforms provide mostly the same functionality, there are some
* variations around how different bus types and clock tree structures
* are handled.
*
* The following functions are available on all platforms with the same
* parameters and functionality. These functions may be called freely by
* portable applications, drivers and services:
* - sysclk_init()
* - sysclk_set_source()
* - sysclk_get_main_hz()
* - sysclk_get_cpu_hz()
* - sysclk_get_peripheral_bus_hz()
*
* The following functions are available on all platforms, but there may
* be variations in the function signature (i.e. parameters) and
* behavior. These functions are typically called by platform-specific
* parts of drivers, and applications that aren't intended to be
* portable:
* - sysclk_enable_peripheral_clock()
* - sysclk_disable_peripheral_clock()
* - sysclk_enable_module()
* - sysclk_disable_module()
* - sysclk_module_is_enabled()
* - sysclk_set_prescalers()
*
* All other functions should be considered platform-specific.
* Enabling/disabling clocks to specific peripherals as well as
* determining the speed of these clocks should be done by calling
* functions provided by the driver for that peripheral.
*
* @{
*/
//! \name System Clock Initialization
//@{
/**
* \fn void sysclk_init(void)
* \brief Initialize the synchronous clock system.
*
* This function will initialize the system clock and its source. This
* includes:
* - Mask all synchronous clocks except for any clocks which are
* essential for normal operation (for example internal memory
* clocks).
* - Set up the system clock prescalers as specified by the
* application's configuration file.
* - Enable the clock source specified by the application's
* configuration file (oscillator or PLL) and wait for it to become
* stable.
* - Set the main system clock source to the clock specified by the
* application's configuration file.
*
* Since all non-essential peripheral clocks are initially disabled, it
* is the responsibility of the peripheral driver to re-enable any
* clocks that are needed for normal operation.
*/
//@}
//! @}
#endif /* SYSCLK_H_INCLUDED */
bacnet-stack/ports/xplained/ASF/common/services/clock/xmega/osc.h
+513
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/**
* \file
*
* \brief Chip-specific oscillator management functions
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef XMEGA_OSC_H_INCLUDED
#define XMEGA_OSC_H_INCLUDED
#include <compiler.h>
#include <board.h>
/**
* \weakgroup osc_group
*
* \section osc_group_errata Errata
* - Auto-calibration does not work on XMEGA A1 revision H and
* earlier.
* @{
*/
//! \name Oscillator identifiers
//@{
//! 2 MHz Internal RC Oscillator
#define OSC_ID_RC2MHZ OSC_RC2MEN_bm
//! 32 MHz Internal RC Oscillator
#define OSC_ID_RC32MHZ OSC_RC32MEN_bm
//! 32 KHz Internal RC Oscillator
#define OSC_ID_RC32KHZ OSC_RC32KEN_bm
//! External Oscillator
#define OSC_ID_XOSC OSC_XOSCEN_bm
#if XMEGA_E
//! 8 MHz Internal RC Oscillator
# define OSC_ID_RC8MHZ OSC_RC8MEN_bm
#endif
/**
* \brief Reference from USB Start Of Frame
* \note This cannot be enabled or disabled, but can be used as a reference for
* the autocalibration (DFLL).
*/
#define OSC_ID_USBSOF 0xff
//@}
//! \name External oscillator types
//@{
#define XOSC_TYPE_EXTERNAL 0 //!< External clock signal
#define XOSC_TYPE_32KHZ 2 //!< 32.768 kHz resonator on TOSC
#define XOSC_TYPE_XTAL 3 //!< 0.4 to 16 MHz resonator on XTAL
//@}
/**
* \def CONFIG_XOSC_32KHZ_LPM
* \brief Define for enabling Low Power Mode for 32 kHz external oscillator.
*/
#ifdef __DOXYGEN__
# define CONFIG_XOSC_32KHZ_LPM
#endif /* __DOXYGEN__ */
/**
* \def CONFIG_XOSC_STARTUP
* \brief Board-dependent value that determines the number of start-up cycles
* for external resonators, based on BOARD_XOSC_STARTUP_US. This is written to
* the two MSB of the XOSCSEL field of OSC.XOSCCTRL.
*
* \note This is automatically computed from BOARD_XOSC_HZ and
* BOARD_XOSC_STARTUP_US if it is not manually set.
*/
//! \name XTAL resonator start-up cycles
//@{
#define XOSC_STARTUP_256 0 //!< 256 cycle start-up time
#define XOSC_STARTUP_1024 1 //!< 1 k cycle start-up time
#define XOSC_STARTUP_16384 2 //!< 16 k cycle start-up time
//@}
/**
* \def CONFIG_XOSC_RANGE
* \brief Board-dependent value that sets the frequency range of the external
* oscillator. This is written to the FRQRANGE field of OSC.XOSCCTRL.
*
* \note This is automatically computed from BOARD_XOSC_HZ if it is not manually
* set.
*/
//! \name XTAL resonator frequency range
//@{
//! 0.4 to 2 MHz frequency range
#define XOSC_RANGE_04TO2 OSC_FRQRANGE_04TO2_gc
//! 2 to 9 MHz frequency range
#define XOSC_RANGE_2TO9 OSC_FRQRANGE_2TO9_gc
//! 9 to 12 MHz frequency range
#define XOSC_RANGE_9TO12 OSC_FRQRANGE_9TO12_gc
//! 12 to 16 MHz frequency range
#define XOSC_RANGE_12TO16 OSC_FRQRANGE_12TO16_gc
//@}
/**
* \def XOSC_STARTUP_TIMEOUT
* \brief Number of us to wait for XOSC to start
*
* This is the number of slow clock cycles corresponding to
* OSC0_STARTUP_VALUE with an additional 25% safety margin. If the
* oscillator isn't running when this timeout has expired, it is assumed
* to have failed to start.
*/
// If application intends to use XOSC.
#ifdef BOARD_XOSC_HZ
// Get start-up config for XOSC, if not manually set.
# ifndef CONFIG_XOSC_STARTUP
# ifndef BOARD_XOSC_STARTUP_US
# error BOARD_XOSC_STARTUP_US must be configured.
# else
//! \internal Number of start-up cycles for the board's XOSC.
# define BOARD_XOSC_STARTUP_CYCLES \
(BOARD_XOSC_HZ / 1000000 * BOARD_XOSC_STARTUP_US)
# if (BOARD_XOSC_TYPE == XOSC_TYPE_XTAL)
# if (BOARD_XOSC_STARTUP_CYCLES > 16384)
# error BOARD_XOSC_STARTUP_US is too high for current BOARD_XOSC_HZ.
# elif (BOARD_XOSC_STARTUP_CYCLES > 1024)
# define CONFIG_XOSC_STARTUP XOSC_STARTUP_16384
# define XOSC_STARTUP_TIMEOUT (16384*(1000000/BOARD_XOSC_HZ))
# elif (BOARD_XOSC_STARTUP_CYCLES > 256)
# define CONFIG_XOSC_STARTUP XOSC_STARTUP_1024
# define XOSC_STARTUP_TIMEOUT (1024*(1000000/BOARD_XOSC_HZ))
# else
# define CONFIG_XOSC_STARTUP XOSC_STARTUP_256
# define XOSC_STARTUP_TIMEOUT (256*(1000000/BOARD_XOSC_HZ))
# endif
# else /* BOARD_XOSC_TYPE == XOSC_TYPE_XTAL */
# define CONFIG_XOSC_STARTUP 0
# endif
# endif /* BOARD_XOSC_STARTUP_US */
# endif /* CONFIG_XOSC_STARTUP */
// Get frequency range setting for XOSC, if not manually set.
# ifndef CONFIG_XOSC_RANGE
# if (BOARD_XOSC_TYPE == XOSC_TYPE_XTAL)
# if (BOARD_XOSC_HZ < 400000)
# error BOARD_XOSC_HZ is below minimum frequency of 400 kHz.
# elif (BOARD_XOSC_HZ < 2000000)
# define CONFIG_XOSC_RANGE XOSC_RANGE_04TO2
# elif (BOARD_XOSC_HZ < 9000000)
# define CONFIG_XOSC_RANGE XOSC_RANGE_2TO9
# elif (BOARD_XOSC_HZ < 12000000)
# define CONFIG_XOSC_RANGE XOSC_RANGE_9TO12
# elif (BOARD_XOSC_HZ <= 16000000)
# define CONFIG_XOSC_RANGE XOSC_RANGE_12TO16
# else
# error BOARD_XOSC_HZ is above maximum frequency of 16 MHz.
# endif
# else /* BOARD_XOSC_TYPE == XOSC_TYPE_XTAL */
# define CONFIG_XOSC_RANGE 0
# endif
# endif /* CONFIG_XOSC_RANGE */
#endif /* BOARD_XOSC_HZ */
#ifndef __ASSEMBLY__
/**
* \internal
* \brief Enable internal oscillator \a id
*
* Do not call this function directly. Use osc_enable() instead.
*/
static inline void
osc_enable_internal (uint8_t id)
{
irqflags_t flags;
Assert (id != OSC_ID_USBSOF);
flags = cpu_irq_save ();
OSC.CTRL |= id;
#if (XMEGA_E && CONFIG_SYSCLK_RC8MHZ_LPM)
if (id == OSC_ID_RC8MHZ)
{
OSC.CTRL |= OSC_RC8MLPM_bm;
}
#endif
cpu_irq_restore (flags);
}
#if defined(BOARD_XOSC_HZ) || defined(__DOXYGEN__)
/**
* \internal
* \brief Enable external oscillator \a id
*
* Do not call this function directly. Use osc_enable() instead. Also
* note that this function is only available if the board actually has
* an external oscillator crystal.
*/
static inline void
osc_enable_external (uint8_t id)
{
irqflags_t flags;
Assert (id == OSC_ID_XOSC);
#ifndef CONFIG_XOSC_32KHZ_LPM
# if (XMEGA_E && (BOARD_XOSC_TYPE == XOSC_TYPE_EXTERNAL) && defined(CONFIG_XOSC_EXTERNAL_PC4))
OSC.XOSCCTRL = OSC_XOSCSEL4_bm;
# else
OSC.XOSCCTRL = BOARD_XOSC_TYPE | (CONFIG_XOSC_STARTUP << 2) |
CONFIG_XOSC_RANGE;
# endif
#else
OSC.XOSCCTRL = BOARD_XOSC_TYPE | (CONFIG_XOSC_STARTUP << 2) |
CONFIG_XOSC_RANGE | OSC_X32KLPM_bm;
#endif /* CONFIG_XOSC_32KHZ_LPM */
flags = cpu_irq_save ();
OSC.CTRL |= id;
cpu_irq_restore (flags);
}
#else
static inline void
osc_enable_external (uint8_t id)
{
Assert (false); // No external oscillator on the selected board
}
#endif
static inline void
osc_disable (uint8_t id)
{
irqflags_t flags;
Assert (id != OSC_ID_USBSOF);
flags = cpu_irq_save ();
OSC.CTRL &= ~id;
cpu_irq_restore (flags);
}
static inline void
osc_enable (uint8_t id)
{
if (id != OSC_ID_XOSC)
{
osc_enable_internal (id);
}
else
{
osc_enable_external (id);
}
}
static inline bool
osc_is_ready (uint8_t id)
{
Assert (id != OSC_ID_USBSOF);
return OSC.STATUS & id;
}
//! \name XMEGA-Specific Oscillator Features
//@{
/**
* \brief Enable DFLL-based automatic calibration of an internal
* oscillator.
*
* The XMEGA features two Digital Frequency Locked Loops (DFLLs) which
* can be used to improve the accuracy of the 2 MHz and 32 MHz internal
* RC oscillators. The DFLL compares the oscillator frequency with a
* more accurate reference clock to do automatic run-time calibration of
* the oscillator.
*
* This function enables auto-calibration for either the 2 MHz or 32 MHz
* internal oscillator using either the 32.768 kHz calibrated internal
* oscillator or an external crystal oscillator as a reference. If the
* latter option is used, the crystal must be connected to the TOSC pins
* and run at 32.768 kHz.
*
* \param id The ID of the oscillator for which to enable
* auto-calibration:
* \arg \c OSC_ID_RC2MHZ or \c OSC_ID_RC32MHZ.
* \param ref_id The ID of the oscillator to use as a reference:
* \arg \c OSC_ID_RC32KHZ or \c OSC_ID_XOSC for internal or external 32 kHz
* reference, respectively.
* \arg \c OSC_ID_USBSOF for 32 MHz only when USB is available and running.
*/
static inline void
osc_enable_autocalibration (uint8_t id, uint8_t ref_id)
{
irqflags_t flags;
flags = cpu_irq_save ();
switch (id)
{
case OSC_ID_RC2MHZ:
#if !XMEGA_E
Assert ((ref_id == OSC_ID_RC32KHZ) || (ref_id == OSC_ID_XOSC));
if (ref_id == OSC_ID_XOSC)
{
osc_enable (OSC_ID_RC32KHZ);
OSC.DFLLCTRL |= OSC_RC2MCREF_bm;
}
else
{
OSC.DFLLCTRL &= ~(OSC_RC2MCREF_bm);
}
DFLLRC2M.CTRL |= DFLL_ENABLE_bm;
#endif
break;
case OSC_ID_RC32MHZ:
#if XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_E
Assert ((ref_id == OSC_ID_RC32KHZ)
|| (ref_id == OSC_ID_XOSC) || (ref_id == OSC_ID_USBSOF));
OSC.DFLLCTRL &= ~(OSC_RC32MCREF_gm);
if (ref_id == OSC_ID_XOSC)
{
osc_enable (OSC_ID_RC32KHZ);
OSC.DFLLCTRL |= OSC_RC32MCREF_XOSC32K_gc;
}
else if (ref_id == OSC_ID_RC32KHZ)
{
OSC.DFLLCTRL |= OSC_RC32MCREF_RC32K_gc;
}
# if !XMEGA_E
else if (ref_id == OSC_ID_USBSOF)
{
/*
* Calibrate 32MRC at 48MHz using USB SOF
* 48MHz / 1kHz = 0xBB80
*/
DFLLRC32M.COMP1 = 0x80;
DFLLRC32M.COMP2 = 0xBB;
OSC.DFLLCTRL |= OSC_RC32MCREF_USBSOF_gc;
}
# endif
#else
Assert ((ref_id == OSC_ID_RC32KHZ) || (ref_id == OSC_ID_XOSC));
if (ref_id == OSC_ID_XOSC)
{
osc_enable (OSC_ID_RC32KHZ);
OSC.DFLLCTRL |= OSC_RC32MCREF_bm;
}
else if (ref_id == OSC_ID_RC32KHZ)
{
OSC.DFLLCTRL &= ~(OSC_RC32MCREF_bm);
}
#endif
DFLLRC32M.CTRL |= DFLL_ENABLE_bm;
break;
default:
Assert (false);
break;
}
cpu_irq_restore (flags);
}
/**
* \brief Disable DFLL-based automatic calibration of an internal
* oscillator.
*
* \see osc_enable_autocalibration
*
* \param id The ID of the oscillator for which to disable
* auto-calibration:
* \arg \c OSC_ID_RC2MHZ or \c OSC_ID_RC32MHZ.
*/
static inline void
osc_disable_autocalibration (uint8_t id)
{
switch (id)
{
case OSC_ID_RC2MHZ:
#if !XMEGA_E
DFLLRC2M.CTRL = 0;
#endif
break;
case OSC_ID_RC32MHZ:
DFLLRC32M.CTRL = 0;
break;
default:
Assert (false);
break;
}
}
/**
* \brief Load a specific calibration value for the specified oscillator.
*
* \param id The ID of the oscillator for which to disable
* auto-calibration:
* \arg \c OSC_ID_RC2MHZ or \c OSC_ID_RC32MHZ.
* \param calib The specific calibration value required:
*
*/
static inline void
osc_user_calibration (uint8_t id, uint16_t calib)
{
switch (id)
{
case OSC_ID_RC2MHZ:
#if !XMEGA_E
DFLLRC2M.CALA = LSB (calib);
DFLLRC2M.CALB = MSB (calib);
#endif
break;
case OSC_ID_RC32MHZ:
DFLLRC32M.CALA = LSB (calib);
DFLLRC32M.CALB = MSB (calib);
break;
#if XMEGA_E
case OSC_ID_RC8MHZ:
OSC.RC8MCAL = LSB (calib);
break;
#endif
default:
Assert (false);
break;
}
}
//@}
static inline uint32_t
osc_get_rate (uint8_t id)
{
Assert (id != OSC_ID_USBSOF);
switch (id)
{
case OSC_ID_RC2MHZ:
return 2000000UL;
case OSC_ID_RC32MHZ:
#ifdef CONFIG_OSC_RC32_CAL
return CONFIG_OSC_RC32_CAL;
#else
return 32000000UL;
#endif
case OSC_ID_RC32KHZ:
return 32768UL;
#ifdef BOARD_XOSC_HZ
case OSC_ID_XOSC:
return BOARD_XOSC_HZ;
#endif
default:
Assert (false);
return 0;
}
}
#endif /* __ASSEMBLY__ */
//! @}
#endif /* XMEGA_OSC_H_INCLUDED */
bacnet-stack/ports/xplained/ASF/common/services/clock/xmega/pll.h
+287
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/**
* \file
*
* \brief Chip-specific PLL management functions
*
* Copyright (c) 2010-2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef XMEGA_PLL_H_INCLUDED
#define XMEGA_PLL_H_INCLUDED
#include <compiler.h>
/**
* \weakgroup pll_group
* @{
*/
#define NR_PLLS 1
#define PLL_MIN_HZ 10000000UL
#define PLL_MAX_HZ 200000000UL
#define PLL_NR_OPTIONS 0
enum pll_source
{
//! 2 MHz Internal RC Oscillator
PLL_SRC_RC2MHZ = OSC_PLLSRC_RC2M_gc,
//! 32 MHz Internal RC Oscillator
PLL_SRC_RC32MHZ = OSC_PLLSRC_RC32M_gc,
//! External Clock Source
PLL_SRC_XOSC = OSC_PLLSRC_XOSC_gc,
};
#define pll_get_default_rate(pll_id) \
pll_get_default_rate_priv(CONFIG_PLL##pll_id##_SOURCE, \
CONFIG_PLL##pll_id##_MUL, \
CONFIG_PLL##pll_id##_DIV)
/**
* \internal
* \brief Return clock rate for specified PLL settings.
*
* \note Due to the hardware implementation of the PLL, \a div must be 4 if the
* 32 MHz RC oscillator is used as reference and 1 otherwise. The reference must
* be above 440 kHz, and the output between 10 and 200 MHz.
*
* \param src ID of the PLL's reference source oscillator.
* \param mul Multiplier for the PLL.
* \param div Divisor for the PLL.
*
* \retval Output clock rate from PLL.
*/
static inline uint32_t
pll_get_default_rate_priv (enum pll_source src,
unsigned int mul, unsigned int div)
{
uint32_t rate;
switch (src)
{
case PLL_SRC_RC2MHZ:
rate = 2000000UL;
Assert (div == 1);
break;
case PLL_SRC_RC32MHZ:
#ifdef CONFIG_OSC_RC32_CAL //32MHz oscillator is calibrated to another frequency
rate = CONFIG_OSC_RC32_CAL / 4;
#else
rate = 8000000UL;
#endif
Assert (div == 4);
break;
case PLL_SRC_XOSC:
rate = osc_get_rate (OSC_ID_XOSC);
Assert (div == 1);
break;
default:
break;
}
Assert (rate >= 440000UL);
rate *= mul;
Assert (rate >= PLL_MIN_HZ);
Assert (rate <= PLL_MAX_HZ);
return rate;
}
struct pll_config
{
uint8_t ctrl;
};
/**
* \note The XMEGA PLL hardware uses hard-wired input dividers, so the
* user must ensure that \a div is set as follows:
* - If \a src is PLL_SRC_32MHZ, \a div must be set to 4.
* - Otherwise, \a div must be set to 1.
*/
static inline void
pll_config_init (struct pll_config *cfg, enum pll_source src,
unsigned int div, unsigned int mul)
{
Assert (mul >= 1 && mul <= 31);
if (src == PLL_SRC_RC32MHZ)
{
Assert (div == 4);
}
else
{
Assert (div == 1);
}
/* Initialize the configuration */
cfg->ctrl = src | (mul << OSC_PLLFAC_gp);
}
#define pll_config_defaults(cfg, pll_id) \
pll_config_init(cfg, \
CONFIG_PLL##pll_id##_SOURCE, \
CONFIG_PLL##pll_id##_DIV, \
CONFIG_PLL##pll_id##_MUL)
static inline void
pll_config_read (struct pll_config *cfg, unsigned int pll_id)
{
Assert (pll_id < NR_PLLS);
cfg->ctrl = OSC.PLLCTRL;
}
static inline void
pll_config_write (const struct pll_config *cfg, unsigned int pll_id)
{
Assert (pll_id < NR_PLLS);
OSC.PLLCTRL = cfg->ctrl;
}
/**
* \note If a different PLL reference oscillator than those enabled by
* \ref sysclk_init() is used, the user must ensure that the desired reference
* is enabled prior to calling this function.
*/
static inline void
pll_enable (const struct pll_config *cfg, unsigned int pll_id)
{
irqflags_t flags;
Assert (pll_id < NR_PLLS);
flags = cpu_irq_save ();
pll_config_write (cfg, pll_id);
OSC.CTRL |= OSC_PLLEN_bm;
cpu_irq_restore (flags);
}
/*! \note This will not automatically disable the reference oscillator that is
* configured for the PLL.
*/
static inline void
pll_disable (unsigned int pll_id)
{
irqflags_t flags;
Assert (pll_id < NR_PLLS);
flags = cpu_irq_save ();
OSC.CTRL &= ~OSC_PLLEN_bm;
cpu_irq_restore (flags);
}
static inline bool
pll_is_locked (unsigned int pll_id)
{
Assert (pll_id < NR_PLLS);
return OSC.STATUS & OSC_PLLRDY_bm;
}
static inline void
pll_enable_source (enum pll_source src)
{
switch (src)
{
case PLL_SRC_RC2MHZ:
break;
case PLL_SRC_RC32MHZ:
if (!osc_is_ready (OSC_ID_RC32MHZ))
{
osc_enable (OSC_ID_RC32MHZ);
osc_wait_ready (OSC_ID_RC32MHZ);
#ifdef CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC
if (CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC != OSC_ID_USBSOF)
{
osc_enable (CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
osc_wait_ready (CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
}
osc_enable_autocalibration (OSC_ID_RC32MHZ,
CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
#endif
}
break;
case PLL_SRC_XOSC:
if (!osc_is_ready (OSC_ID_XOSC))
{
osc_enable (OSC_ID_XOSC);
osc_wait_ready (OSC_ID_XOSC);
}
break;
default:
Assert (false);
break;
}
}
static inline void
pll_enable_config_defaults (unsigned int pll_id)
{
struct pll_config pllcfg;
if (pll_is_locked (pll_id))
{
return; // Pll already running
}
switch (pll_id)
{
#ifdef CONFIG_PLL0_SOURCE
case 0:
pll_enable_source (CONFIG_PLL0_SOURCE);
pll_config_init (&pllcfg,
CONFIG_PLL0_SOURCE, CONFIG_PLL0_DIV, CONFIG_PLL0_MUL);
break;
#endif
default:
Assert (false);
break;
}
pll_enable (&pllcfg, pll_id);
while (!pll_is_locked (pll_id));
}
//! @}
#endif /* XMEGA_PLL_H_INCLUDED */
bacnet-stack/ports/xplained/ASF/common/services/clock/xmega/sysclk.c
+255
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/**
* \file
*
* \brief Chip-specific system clock management functions
*
* Copyright (c) 2010-2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <compiler.h>
#include <sysclk.h>
#include <osc.h>
#include <pll.h>
#if XMEGA_AU || XMEGA_B || XMEGA_C
# include <nvm.h>
#endif
void sysclk_init(void)
{
uint8_t *reg = (uint8_t *) & PR.PRGEN;
uint8_t i;
#ifdef CONFIG_OSC_RC32_CAL
uint16_t cal;
/* avoid Cppcheck Warning */
UNUSED(cal);
#endif
bool need_rc2mhz = false;
/* Turn off all peripheral clocks that can be turned off. */
for (i = 0; i <= SYSCLK_PORT_F; i++) {
*(reg++) = 0xff;
}
/* Set up system clock prescalers if different from defaults */
if ((CONFIG_SYSCLK_PSADIV != SYSCLK_PSADIV_1)
|| (CONFIG_SYSCLK_PSBCDIV != SYSCLK_PSBCDIV_1_1)) {
sysclk_set_prescalers(CONFIG_SYSCLK_PSADIV, CONFIG_SYSCLK_PSBCDIV);
}
#if (CONFIG_OSC_RC32_CAL==48000000UL)
MSB(cal) =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(USBRCOSC));
LSB(cal) =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(USBRCOSCA));
/*
* If a device has an uncalibrated value in the
* production signature row (early sample part), load a
* sane default calibration value.
*/
if (cal == 0xFFFF) {
cal = 0x2340;
}
osc_user_calibration(OSC_ID_RC32MHZ, cal);
#endif
/*
* Switch to the selected initial system clock source, unless
* the default internal 2 MHz oscillator is selected.
*/
if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_RC2MHZ) {
need_rc2mhz = true;
} else {
switch (CONFIG_SYSCLK_SOURCE) {
case SYSCLK_SRC_RC32MHZ:
osc_enable(OSC_ID_RC32MHZ);
osc_wait_ready(OSC_ID_RC32MHZ);
#ifdef CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC
if (CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC != OSC_ID_USBSOF) {
osc_enable(CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
osc_wait_ready(CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
}
osc_enable_autocalibration(OSC_ID_RC32MHZ,
CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
#endif
break;
case SYSCLK_SRC_RC32KHZ:
osc_enable(OSC_ID_RC32KHZ);
osc_wait_ready(OSC_ID_RC32KHZ);
break;
case SYSCLK_SRC_XOSC:
osc_enable(OSC_ID_XOSC);
osc_wait_ready(OSC_ID_XOSC);
break;
#ifdef CONFIG_PLL0_SOURCE
case SYSCLK_SRC_PLL:
if (CONFIG_PLL0_SOURCE == PLL_SRC_RC2MHZ) {
need_rc2mhz = true;
}
pll_enable_config_defaults(0);
break;
#endif
#if XMEGA_E
case SYSCLK_SRC_RC8MHZ:
osc_enable(OSC_ID_RC8MHZ);
osc_wait_ready(OSC_ID_RC8MHZ);
break;
#endif
default:
//unhandled_case(CONFIG_SYSCLK_SOURCE);
return;
}
ccp_write_io((uint8_t *) & CLK.CTRL, CONFIG_SYSCLK_SOURCE);
Assert(CLK.CTRL == CONFIG_SYSCLK_SOURCE);
}
if (need_rc2mhz) {
#ifdef CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC
osc_enable(CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC);
osc_wait_ready(CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC);
osc_enable_autocalibration(OSC_ID_RC2MHZ,
CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC);
#endif
} else {
osc_disable(OSC_ID_RC2MHZ);
}
#ifdef CONFIG_RTC_SOURCE
sysclk_rtcsrc_enable(CONFIG_RTC_SOURCE);
#endif
}
void sysclk_enable_module(enum sysclk_port_id port,
uint8_t id)
{
irqflags_t flags = cpu_irq_save();
*((uint8_t *) & PR.PRGEN + port) &= ~id;
cpu_irq_restore(flags);
}
void sysclk_disable_module(enum sysclk_port_id port,
uint8_t id)
{
irqflags_t flags = cpu_irq_save();
*((uint8_t *) & PR.PRGEN + port) |= id;
cpu_irq_restore(flags);
}
#if XMEGA_AU || XMEGA_B || XMEGA_C || defined(__DOXYGEN__)
/**
* \brief Enable clock for the USB module
*
* \pre CONFIG_USBCLK_SOURCE must be defined.
*
* \param frequency The required USB clock frequency in MHz:
* \arg \c 6 for 6 MHz
* \arg \c 48 for 48 MHz
*/
void sysclk_enable_usb(uint8_t frequency)
{
uint8_t prescaler;
Assert((frequency == 6) || (frequency == 48));
/*
* Enable or disable prescaler depending on if the USB frequency is 6
* MHz or 48 MHz. Only 6 MHz USB frequency requires prescaling.
*/
if (frequency == 6) {
prescaler = CLK_USBPSDIV_8_gc;
} else {
prescaler = 0;
}
/*
* Switch to the system clock selected by the user.
*/
switch (CONFIG_USBCLK_SOURCE) {
case USBCLK_SRC_RCOSC:
if (!osc_is_ready(OSC_ID_RC32MHZ)) {
osc_enable(OSC_ID_RC32MHZ);
osc_wait_ready(OSC_ID_RC32MHZ);
#ifdef CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC
if (CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC != OSC_ID_USBSOF) {
osc_enable(CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
osc_wait_ready(CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
}
osc_enable_autocalibration(OSC_ID_RC32MHZ,
CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC);
#endif
}
ccp_write_io((uint8_t *) & CLK.USBCTRL, (prescaler)
| CLK_USBSRC_RC32M_gc | CLK_USBSEN_bm);
break;
#ifdef CONFIG_PLL0_SOURCE
case USBCLK_SRC_PLL:
pll_enable_config_defaults(0);
ccp_write_io((uint8_t *) & CLK.USBCTRL, (prescaler)
| CLK_USBSRC_PLL_gc | CLK_USBSEN_bm);
break;
#endif
default:
Assert(false);
break;
}
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_USB);
}
/**
* \brief Disable clock for the USB module
*/
void sysclk_disable_usb(void)
{
sysclk_disable_module(SYSCLK_PORT_GEN, SYSCLK_USB);
ccp_write_io((uint8_t *) & CLK.USBCTRL, 0);
}
#endif // XMEGA_AU || XMEGA_B || XMEGA_C
bacnet-stack/ports/xplained/ASF/common/services/clock/xmega/sysclk.h
+1681
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bacnet-stack/ports/xplained/ASF/common/services/delay/delay.h
+137
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/**
* \file
*
* \brief Common Delay Service
*
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _DELAY_H_
#define _DELAY_H_
#ifdef __cplusplus
extern "C"
{
#endif
#include <sysclk.h>
#if UC3
# include <cycle_counter.h>
#elif XMEGA
# include "xmega/cycle_counter.h"
#elif MEGA
# include "mega/cycle_counter.h"
#elif SAM
# include "sam/cycle_counter.h"
#endif
/**
* @defgroup group_common_services_delay Busy-Wait Delay Routines
*
* This module provides simple loop-based delay routines for those
* applications requiring a brief wait during execution. Common API
* for UC3, XMEGA, and AVR MEGA.
*
* @{
*/
/**
* @def F_CPU
* @brief MCU Clock Frequency (Hertz)
*
* @deprecated
* The \ref F_CPU configuration constant is used for compatibility with the
* \ref group_common_services_delay routines. The common loop-based delay
* routines are designed to use the \ref clk_group modules while anticipating
* support for legacy applications assuming a statically defined clock
* frequency. Applications using a statically configured MCU clock frequency
* can define \ref F_CPU (Hertz), in which case the common delay routines will
* use this value rather than calling sysclk_get_cpu_hz() to get the current
* MCU clock frequency.
*/
#ifndef F_CPU
# define F_CPU sysclk_get_cpu_hz()
#endif
/**
* @def delay_init
*
* @brief Initialize the delay driver.
* @param fcpu_hz CPU frequency in Hz
*
* @deprecated
* This function is provided for compatibility with ASF applications that
* may not have been updated to configure the system clock via the common
* clock service; e.g. sysclk_init() and a configuration header file are
* used to configure clocks.
*
* The functions in this module call \ref sysclk_get_cpu_hz() function to
* obtain the system clock frequency.
*/
#define delay_init(fcpu_hz)
/**
* @def delay_s
* @brief Delay in seconds.
* @param delay Delay in seconds
*/
#define delay_s(delay) cpu_delay_ms(1000 * delay, F_CPU)
/**
* @def delay_ms
* @brief Delay in milliseconds.
* @param delay Delay in milliseconds
*/
#define delay_ms(delay) cpu_delay_ms(delay, F_CPU)
/**
* @def delay_us
* @brief Delay in microseconds.
* @param delay Delay in microseconds
*/
#define delay_us(delay) cpu_delay_us(delay, F_CPU)
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* _DELAY_H_ */
bacnet-stack/ports/xplained/ASF/common/services/delay/xmega/cycle_counter.h
+118
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/**
* \file
*
* \brief AVR functions for busy-wait delay loops
*
* Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _CYCLE_COUNTER_H_
#define _CYCLE_COUNTER_H_
#ifdef __cplusplus
extern "C"
{
#endif
#include <compiler.h>
/**
* @name Convenience functions for busy-wait delay loops
*
* @def delay_cycles
* @brief Delay program execution for a specified number of CPU cycles.
* @param n number of CPU cycles to wait
*
* @def cpu_delay_ms
* @brief Delay program execution for a specified number of milliseconds.
* @param delay number of milliseconds to wait
* @param f_cpu CPU frequency in Hertz
*
* @def cpu_delay_us
* @brief Delay program execution for a specified number of microseconds.
* @param delay number of microseconds to wait
* @param f_cpu CPU frequency in Hertz
*
* @def cpu_ms_2_cy
* @brief Convert milli-seconds into CPU cycles.
* @param ms number of milliseconds
* @param f_cpu CPU frequency in Hertz
* @return the converted number of CPU cycles
*
* @def cpu_us_2_cy
* @brief Convert micro-seconds into CPU cycles.
* @param ms number of microseconds
* @param f_cpu CPU frequency in Hertz
* @return the converted number of CPU cycles
*
* @{
*/
__always_optimize
static inline void __portable_avr_delay_cycles (unsigned long n)
{
do
{
barrier ();
}
while (--n);
}
#if !defined(__DELAY_CYCLE_INTRINSICS__)
# define delay_cycles __portable_avr_delay_cycles
# define cpu_ms_2_cy(ms, f_cpu) (((uint64_t)(ms) * (f_cpu) + 999) / 6e3)
# define cpu_us_2_cy(us, f_cpu) (((uint64_t)(us) * (f_cpu) + 999999ul) / 6e6)
#else
# if defined(__GNUC__)
# define delay_cycles __builtin_avr_delay_cycles
# elif defined(__ICCAVR__)
# define delay_cycles __delay_cycles
# endif
# define cpu_ms_2_cy(ms, f_cpu) (((uint64_t)(ms) * (f_cpu) + 999) / 1e3)
# define cpu_us_2_cy(us, f_cpu) (((uint64_t)(us) * (f_cpu) + 999999ul) / 1e6)
#endif
#define cpu_delay_ms(delay, f_cpu) delay_cycles((uint64_t)cpu_ms_2_cy(delay, f_cpu))
#define cpu_delay_us(delay, f_cpu) delay_cycles((uint64_t)cpu_us_2_cy(delay, f_cpu))
//! @}
#ifdef __cplusplus
}
#endif
#endif /* _CYCLE_COUNTER_H_ */
bacnet-stack/ports/xplained/ASF/common/services/gpio/gpio.h
+83
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/**
* \file
*
* \brief Common GPIO API.
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _GPIO_H_
#define _GPIO_H_
#include <parts.h>
#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E)
# include "sam_gpio/sam_gpio.h"
#elif XMEGA
# include "xmega_gpio/xmega_gpio.h"
#elif MEGA || MEGA_RF
# include "mega_gpio/mega_gpio.h"
#else
# error Unsupported chip type
#endif
/**
* \defgroup gpio_group General Purpose Input/Output
*
* This is the common API for GPIO. Additional features are available
* in the documentation of the specific modules.
*
* \section io_group_platform Platform Dependencies
*
* The following functions are available on all platforms, but there may
* be variations in the function signature (i.e. parameters) and
* behaviour. These functions are typically called by platform-specific
* parts of drivers, and applications that aren't intended to be
* portable:
* - gpio_pin_is_low()
* - gpio_pin_is_high()
* - gpio_set_pin_high()
* - gpio_set_pin_group_high()
* - gpio_set_pin_low()
* - gpio_set_pin_group_low()
* - gpio_toggle_pin()
* - gpio_toggle_pin_group()
* - gpio_configure_pin()
* - gpio_configure_group()
*/
#endif /* _GPIO_H_ */
bacnet-stack/ports/xplained/ASF/common/services/gpio/xmega_gpio/xmega_gpio.h
+80
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/**
* \file
*
* \brief Common gpio data/structure for all AVR XMEGA implementations.
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _XMEGA_GPIO_H_
#define _XMEGA_GPIO_H_
#include "compiler.h"
#include "ioport.h"
#define gpio_pin_is_low(io_id) \
ioport_pin_is_low(io_id)
#define gpio_pin_is_high(io_id) \
ioport_pin_is_high(io_id)
#define gpio_set_pin_high(io_id) \
ioport_set_value(io_id,1)
#define gpio_set_pin_low(io_id) \
ioport_set_value(io_id,0)
#define gpio_toggle_pin(io_id) \
ioport_toggle_pin(io_id)
#define gpio_configure_pin(io_id,io_flags) \
ioport_configure_pin(io_id,io_flags)
#define gpio_configure_group(port_id,port_mask,io_flags) \
ioport_configure_group(port_id,port_mask,io_flags)
#define gpio_set_pin_group_high(port_id,mask) \
ioport_set_group_high(port_id,mask)
#define gpio_set_pin_group_low(port_id,mask) \
ioport_set_group_low(port_id,mask)
#define gpio_toggle_pin_group(port_id,mask) \
ioport_tgl_group(port_id,mask)
#endif // _XMEGA_GPIO_H_
bacnet-stack/ports/xplained/ASF/common/services/ioport/ioport.h
+547
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/**
* \file
*
* \brief Common IOPORT service main header file for AVR, UC3 and ARM
* architectures.
*
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef IOPORT_H
#define IOPORT_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <parts.h>
#include <compiler.h>
/**
* \defgroup ioport_group Common IOPORT API
*
* See \ref ioport_quickstart.
*
* This is common IOPORT service for GPIO pin configuration and control in a
* standardized manner across the MEGA, MEGA_RF, XMEGA, UC3 and ARM devices.
*
* Port pin control code is optimized for each platform, and should produce
* both compact and fast execution times when used with constant values.
*
* \section dependencies Dependencies
* This driver depends on the following modules:
* - \ref sysclk_group for clock speed and functions.
* @{
*/
/**
* \def IOPORT_CREATE_PIN(port, pin)
* \brief Create IOPORT pin number
*
* Create a IOPORT pin number for use with the IOPORT functions.
*
* \param port IOPORT port (e.g. PORTA, PA or PIOA depending on chosen
* architecture)
* \param pin IOPORT zero-based index of the I/O pin
*/
/** \brief IOPORT pin directions */
enum ioport_direction
{
IOPORT_DIR_INPUT, /*!< IOPORT input direction */
IOPORT_DIR_OUTPUT, /*!< IOPORT output direction */
};
/** \brief IOPORT levels */
enum ioport_value
{
IOPORT_PIN_LEVEL_LOW, /*!< IOPORT pin value low */
IOPORT_PIN_LEVEL_HIGH, /*!< IOPORT pin value high */
};
#if MEGA_RF
/** \brief IOPORT edge sense modes */
enum ioport_sense
{
IOPORT_SENSE_LEVEL, /*!< IOPORT sense low level */
IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */
IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */
};
#elif SAM && !SAM4L
/** \brief IOPORT edge sense modes */
enum ioport_sense
{
IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */
IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */
IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */
IOPORT_SENSE_LEVEL_HIGH, /*!< IOPORT sense High level */
};
#else
enum ioport_sense
{
IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */
IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */
};
#endif
#if XMEGA
# include "xmega/ioport.h"
# if defined(IOPORT_XMEGA_COMPAT)
# include "xmega/ioport_compat.h"
# endif
#elif MEGA
# include "mega/ioport.h"
#elif UC3
# include "uc3/ioport.h"
#elif SAM
# if SAM4L
# include "sam/ioport_gpio.h"
# else
# include "sam/ioport_pio.h"
# endif
#endif
/**
* \brief Initializes the IOPORT service, ready for use.
*
* This function must be called before using any other functions in the IOPORT
* service.
*/
static inline void ioport_init (void)
{
arch_ioport_init ();
}
/**
* \brief Enable an IOPORT pin, based on a pin created with \ref
* IOPORT_CREATE_PIN().
*
* \param pin IOPORT pin to enable
*/
static inline void ioport_enable_pin (ioport_pin_t pin)
{
arch_ioport_enable_pin (pin);
}
/**
* \brief Enable multiple pins in a single IOPORT port.
*
* \param port IOPORT port to enable
* \param mask Mask of pins within the port to enable
*/
static inline void ioport_enable_port (ioport_port_t port,
ioport_port_mask_t mask)
{
arch_ioport_enable_port (port, mask);
}
/**
* \brief Disable IOPORT pin, based on a pin created with \ref
* IOPORT_CREATE_PIN().
*
* \param pin IOPORT pin to disable
*/
static inline void ioport_disable_pin (ioport_pin_t pin)
{
arch_ioport_disable_pin (pin);
}
/**
* \brief Disable multiple pins in a single IOPORT port.
*
* \param port IOPORT port to disable
* \param mask Pin mask of pins to disable
*/
static inline void ioport_disable_port (ioport_port_t port,
ioport_port_mask_t mask)
{
arch_ioport_disable_port (port, mask);
}
/**
* \brief Set multiple pin modes in a single IOPORT port, such as pull-up,
* pull-down, etc. configuration.
*
* \param port IOPORT port to configure
* \param mask Pin mask of pins to configure
* \param mode Mode masks to configure for the specified pins (\ref
* ioport_modes)
*/
static inline void ioport_set_port_mode (ioport_port_t port,
ioport_port_mask_t mask,
ioport_mode_t mode)
{
arch_ioport_set_port_mode (port, mask, mode);
}
/**
* \brief Set pin mode for one single IOPORT pin.
*
* \param pin IOPORT pin to configure
* \param mode Mode masks to configure for the specified pin (\ref ioport_modes)
*/
static inline void ioport_set_pin_mode (ioport_pin_t pin,
ioport_mode_t mode)
{
arch_ioport_set_pin_mode (pin, mode);
}
/**
* \brief Reset multiple pin modes in a specified IOPORT port to defaults.
*
* \param port IOPORT port to configure
* \param mask Mask of pins whose mode configuration is to be reset
*/
static inline void ioport_reset_port_mode (ioport_port_t port,
ioport_port_mask_t mask)
{
arch_ioport_set_port_mode (port, mask, 0);
}
/**
* \brief Reset pin mode configuration for a single IOPORT pin
*
* \param pin IOPORT pin to configure
*/
static inline void ioport_reset_pin_mode (ioport_pin_t pin)
{
arch_ioport_set_pin_mode (pin, 0);
}
/**
* \brief Set I/O direction for a group of pins in a single IOPORT.
*
* \param port IOPORT port to configure
* \param mask Pin mask of pins to configure
* \param dir Direction to set for the specified pins (\ref ioport_direction)
*/
static inline void ioport_set_port_dir (ioport_port_t port,
ioport_port_mask_t mask,
enum ioport_direction dir)
{
arch_ioport_set_port_dir (port, mask, dir);
}
/**
* \brief Set direction for a single IOPORT pin.
*
* \param pin IOPORT pin to configure
* \param dir Direction to set for the specified pin (\ref ioport_direction)
*/
static inline void ioport_set_pin_dir (ioport_pin_t pin,
enum ioport_direction dir)
{
arch_ioport_set_pin_dir (pin, dir);
}
/**
* \brief Set an IOPORT pin to a specified logical value.
*
* \param pin IOPORT pin to configure
* \param level Logical value of the pin
*/
static inline void ioport_set_pin_level (ioport_pin_t pin, bool level)
{
arch_ioport_set_pin_level (pin, level);
}
/**
* \brief Set a group of IOPORT pins in a single port to a specified logical
* value.
*
* \param port IOPORT port to write to
* \param mask Pin mask of pins to modify
* \param level Level of the pins to be modified
*/
static inline void ioport_set_port_level (ioport_port_t port,
ioport_port_mask_t mask,
ioport_port_mask_t level)
{
arch_ioport_set_port_level (port, mask, level);
}
/**
* \brief Get current value of an IOPORT pin, which has been configured as an
* input.
*
* \param pin IOPORT pin to read
* \return Current logical value of the specified pin
*/
static inline bool ioport_get_pin_level (ioport_pin_t pin)
{
return arch_ioport_get_pin_level (pin);
}
/**
* \brief Get current value of several IOPORT pins in a single port, which have
* been configured as an inputs.
*
* \param port IOPORT port to read
* \param mask Pin mask of pins to read
* \return Logical levels of the specified pins from the read port, returned as
* a mask.
*/
static inline ioport_port_mask_t ioport_get_port_level (ioport_pin_t port,
ioport_port_mask_t
mask)
{
return arch_ioport_get_port_level (port, mask);
}
/**
* \brief Toggle the value of an IOPORT pin, which has previously configured as
* an output.
*
* \param pin IOPORT pin to toggle
*/
static inline void ioport_toggle_pin_level (ioport_pin_t pin)
{
arch_ioport_toggle_pin_level (pin);
}
/**
* \brief Toggle the values of several IOPORT pins located in a single port.
*
* \param port IOPORT port to modify
* \param mask Pin mask of pins to toggle
*/
static inline void ioport_toggle_port_level (ioport_port_t port,
ioport_port_mask_t mask)
{
arch_ioport_toggle_port_level (port, mask);
}
/**
* \brief Set the pin sense mode of a single IOPORT pin.
*
* \param pin IOPORT pin to configure
* \param pin_sense Edge to sense for the pin (\ref ioport_sense)
*/
static inline void ioport_set_pin_sense_mode (ioport_pin_t pin,
enum ioport_sense pin_sense)
{
arch_ioport_set_pin_sense_mode (pin, pin_sense);
}
/**
* \brief Set the pin sense mode of a multiple IOPORT pins on a single port.
*
* \param port IOPORT port to configure
* \param mask Bitmask if pins whose edge sense is to be configured
* \param pin_sense Edge to sense for the pins (\ref ioport_sense)
*/
static inline void ioport_set_port_sense_mode (ioport_port_t port,
ioport_port_mask_t mask,
enum ioport_sense pin_sense)
{
arch_ioport_set_port_sense_mode (port, mask, pin_sense);
}
/**
* \brief Convert a pin ID into a its port ID.
*
* \param pin IOPORT pin ID to convert
* \retval Port ID for the given pin ID
*/
static inline ioport_port_t ioport_pin_to_port_id (ioport_pin_t pin)
{
return arch_ioport_pin_to_port_id (pin);
}
/**
* \brief Convert a pin ID into a bitmask mask for the given pin on its port.
*
* \param pin IOPORT pin ID to convert
* \retval Bitmask with a bit set that corresponds to the given pin ID in its port
*/
static inline ioport_port_mask_t ioport_pin_to_mask (ioport_pin_t pin)
{
return arch_ioport_pin_to_mask (pin);
}
/** @} */
/**
* \page ioport_quickstart Quick start guide for the common IOPORT service
*
* This is the quick start guide for the \ref ioport_group, with
* step-by-step instructions on how to configure and use the service in a
* selection of use cases.
*
* The use cases contain several code fragments. The code fragments in the
* steps for setup can be copied into a custom initialization function, while
* the steps for usage can be copied into, e.g., the main application function.
*
* \section ioport_quickstart_basic Basic use case
* In this use case we will configure one IO pin for button input and one for
* LED control. Then it will read the button state and output it on the LED.
*
* \section ioport_quickstart_basic_setup Setup steps
*
* \subsection ioport_quickstart_basic_setup_code Example code
* \code
* #define MY_LED IOPORT_CREATE_PIN(PORTA, 5)
* #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)
*
* ioport_init();
*
* ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT);
* ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT);
* ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP);
* \endcode
*
* \subsection ioport_quickstart_basic_setup_flow Workflow
* -# It's useful to give the GPIOs symbolic names and this can be done with
* the \ref IOPORT_CREATE_PIN macro. We define one for a LED and one for a
* button.
* - \code
* #define MY_LED IOPORT_CREATE_PIN(PORTA, 5)
* #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)
* \endcode
* - \note The usefulness of the \ref IOPORT_CREATE_PIN macro and port names
* differ between architectures:
* - MEGA, MEGA_RF and XMEGA: Use \ref IOPORT_CREATE_PIN macro with port definitions
* PORTA, PORTB ...
* - UC3: Most convenient to pick up the device header file pin definition
* and us it directly. E.g.: AVR32_PIN_PB06
* - SAM: Most convenient to pick up the device header file pin definition
* and us it directly. E.g.: PIO_PA5_IDX<br>
* \ref IOPORT_CREATE_PIN can also be used with port definitions
* PIOA, PIOB ...
* -# Initialize the ioport service. This typically enables the IO module if
* needed.
* - \code ioport_init(); \endcode
* -# Set the LED GPIO as output:
* - \code ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); \endcode
* -# Set the button GPIO as input:
* - \code ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); \endcode
* -# Enable pull-up for the button GPIO:
* - \code ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); \endcode
*
* \section ioport_quickstart_basic_usage Usage steps
*
* \subsection ioport_quickstart_basic_usage_code Example code
* \code
* bool value;
*
* value = ioport_get_pin_level(MY_BUTTON);
* ioport_set_pin_level(MY_LED, value);
* \endcode
*
* \subsection ioport_quickstart_basic_usage_flow Workflow
* -# Define a boolean variable for state storage:
* - \code bool value; \endcode
* -# Read out the button level into variable value:
* - \code value = ioport_get_pin_level(MY_BUTTON); \endcode
* -# Set the LED to read out value from the button:
* - \code ioport_set_pin_level(MY_LED, value); \endcode
*
* \section ioport_quickstart_advanced Advanced use cases
* - \subpage ioport_quickstart_use_case_1 : Port access
*/
/**
* \page ioport_quickstart_use_case_1 Advanced use case doing port access
*
* In this case we will read out the pins from one whole port and write the
* read value to another port.
*
* \section ioport_quickstart_use_case_1_setup Setup steps
*
* \subsection ioport_quickstart_use_case_1_setup_code Example code
* \code
* #define IN_PORT IOPORT_PORTA
* #define OUT_PORT IOPORT_PORTB
* #define MASK 0x00000060
*
* ioport_init();
*
* ioport_set_port_dir(IN_PORT, MASK, IOPORT_DIR_INPUT);
* ioport_set_port_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT);
* \endcode
*
* \subsection ioport_quickstart_basic_setup_flow Workflow
* -# It's useful to give the ports symbolic names:
* - \code
* #define IN_PORT IOPORT_PORTA
* #define OUT_PORT IOPORT_PORTB
* \endcode
* - \note The port names differ between architectures:
* - MEGA_RF, MEGA and XMEGA: There are predefined names for ports: IOPORT_PORTA,
* IOPORT_PORTB ...
* - UC3: Use the index value of the different IO blocks: 0, 1 ...
* - SAM: There are predefined names for ports: IOPORT_PIOA, IOPORT_PIOB
* ...
* -# Also useful to define a mask for the bits to work with:
* - \code #define MASK 0x00000060 \endcode
* -# Initialize the ioport service. This typically enables the IO module if
* needed.
* - \code ioport_init(); \endcode
* -# Set one of the ports as input:
* - \code ioport_set_pin_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); \endcode
* -# Set the other port as output:
* - \code ioport_set_pin_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); \endcode
*
* \section ioport_quickstart_basic_usage Usage steps
*
* \subsection ioport_quickstart_basic_usage_code Example code
* \code
* ioport_port_mask_t value;
*
* value = ioport_get_port_level(IN_PORT, MASK);
* ioport_set_port_level(OUT_PORT, MASK, value);
* \endcode
*
* \subsection ioport_quickstart_basic_usage_flow Workflow
* -# Define a variable for port date storage:
* - \code ioport_port_mask_t value; \endcode
* -# Read out from one port:
* - \code value = ioport_get_port_level(IN_PORT, MASK); \endcode
* -# Put the read data out on the other port:
* - \code ioport_set_port_level(OUT_PORT, MASK, value); \endcode
*/
#ifdef __cplusplus
}
#endif
#endif /* IOPORT_H */
bacnet-stack/ports/xplained/ASF/common/services/ioport/xmega/ioport.h
+367
View File
@@ -0,0 +1,367 @@
/**
* \file
*
* \brief XMEGA architecture specific IOPORT service implementation header file.
*
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef IOPORT_XMEGA_H
#define IOPORT_XMEGA_H
#define IOPORT_CREATE_PIN(port, pin) ((IOPORT_ ## port) * 8 + (pin))
#define IOPORT_BASE_ADDRESS 0x600
#define IOPORT_PORT_OFFSET 0x20
/** \name IOPORT port numbers */
/** @{ */
#if !XMEGA_B3
# define IOPORT_PORTA 0
#endif
#define IOPORT_PORTB 1
#define IOPORT_PORTC 2
#define IOPORT_PORTD 3
#if !XMEGA_B3
# define IOPORT_PORTE 4
#endif
#if XMEGA_A1 || XMEGA_A1U || XMEGA_A3 || XMEGA_A3U || XMEGA_A3B || XMEGA_A3BU ||\
XMEGA_C3 || XMEGA_D3
# define IOPORT_PORTF 5
#endif
#if XMEGA_B1 || XMEGA_B3
# define IOPORT_PORTG 6
#endif
#if XMEGA_A1 || XMEGA_A1U
# define IOPORT_PORTH 7
# define IOPORT_PORTJ 8
# define IOPORT_PORTK 9
#endif
#if XMEGA_B1 || XMEGA_B3
# define IOPORT_PORTM 11
#endif
#if XMEGA_A1 || XMEGA_A1U
# define IOPORT_PORTQ 14
#endif
#define IOPORT_PORTR 15
/** @} */
/**
* \weakgroup ioport_group
* \section ioport_modes IOPORT Modes
*
* For details on these please see the XMEGA Manual.
*
* @{
*/
/** \name IOPORT Mode bit definitions */
/** @{ */
#define IOPORT_MODE_TOTEM (0x00 << 3) /*!< Totem-pole */
#define IOPORT_MODE_BUSKEEPER (0x01 << 3) /*!< Buskeeper */
#define IOPORT_MODE_PULLDOWN (0x02 << 3) /*!< Pull-down */
#define IOPORT_MODE_PULLUP (0x03 << 3) /*!< Pull-up */
#define IOPORT_MODE_WIREDOR (0x04 << 3) /*!< Wired OR */
#define IOPORT_MODE_WIREDAND (0x05 << 3) /*!< Wired AND */
#define IOPORT_MODE_WIREDORPULL (0x06 << 3) /*!< Wired OR with pull-down */
#define IOPORT_MODE_WIREDANDPULL (0x07 << 3) /*!< Wired AND with pull-up */
#define IOPORT_MODE_INVERT_PIN (0x01 << 6) /*!< Invert output and input */
#define IOPORT_MODE_SLEW_RATE_LIMIT (0x01 << 7) /*!< Slew rate limiting */
/** @} */
/** @} */
typedef uint8_t ioport_mode_t;
typedef uint8_t ioport_pin_t;
typedef uint8_t ioport_port_t;
typedef uint8_t ioport_port_mask_t;
__always_inline static ioport_port_t
arch_ioport_pin_to_port_id (ioport_pin_t pin)
{
return pin >> 3;
}
__always_inline static PORT_t *
arch_ioport_port_to_base (ioport_port_t port)
{
return (PORT_t *) ((uintptr_t) IOPORT_BASE_ADDRESS +
(port * IOPORT_PORT_OFFSET));
}
__always_inline static PORT_t *
arch_ioport_pin_to_base (ioport_pin_t pin)
{
return arch_ioport_port_to_base (arch_ioport_pin_to_port_id (pin));
}
__always_inline static ioport_port_mask_t
arch_ioport_pin_to_mask (ioport_pin_t pin)
{
return 1U << (pin & 0x07);
}
__always_inline static ioport_port_mask_t
arch_ioport_pin_to_index (ioport_pin_t pin)
{
return (pin & 0x07);
}
__always_inline static void
arch_ioport_init (void)
{
}
__always_inline static void
arch_ioport_enable_port (ioport_port_t port, ioport_port_mask_t mask)
{
PORT_t *base = arch_ioport_port_to_base (port);
volatile uint8_t *pin_ctrl = &base->PIN0CTRL;
uint8_t flags = cpu_irq_save ();
for (uint8_t i = 0; i < 8; i++)
{
if (mask & arch_ioport_pin_to_mask (i))
{
pin_ctrl[i] &= ~PORT_ISC_gm;
}
}
cpu_irq_restore (flags);
}
__always_inline static void
arch_ioport_enable_pin (ioport_pin_t pin)
{
PORT_t *base = arch_ioport_pin_to_base (pin);
volatile uint8_t *pin_ctrl =
(&base->PIN0CTRL + arch_ioport_pin_to_index (pin));
uint8_t flags = cpu_irq_save ();
*pin_ctrl &= ~PORT_ISC_gm;
cpu_irq_restore (flags);
}
__always_inline static void
arch_ioport_disable_port (ioport_port_t port, ioport_port_mask_t mask)
{
PORT_t *base = arch_ioport_port_to_base (port);
volatile uint8_t *pin_ctrl = &base->PIN0CTRL;
uint8_t flags = cpu_irq_save ();
for (uint8_t i = 0; i < 8; i++)
{
if (mask & arch_ioport_pin_to_mask (i))
{
pin_ctrl[i] |= PORT_ISC_INPUT_DISABLE_gc;
}
}
cpu_irq_restore (flags);
}
__always_inline static void
arch_ioport_disable_pin (ioport_pin_t pin)
{
PORT_t *base = arch_ioport_pin_to_base (pin);
volatile uint8_t *pin_ctrl =
(&base->PIN0CTRL + arch_ioport_pin_to_index (pin));
uint8_t flags = cpu_irq_save ();
*pin_ctrl |= PORT_ISC_INPUT_DISABLE_gc;
cpu_irq_restore (flags);
}
__always_inline static void
arch_ioport_set_port_mode (ioport_port_t port,
ioport_port_mask_t mask, ioport_mode_t mode)
{
PORT_t *base = arch_ioport_port_to_base (port);
PORTCFG.MPCMASK = mask;
base->PIN0CTRL = mode;
}
__always_inline static void
arch_ioport_set_pin_mode (ioport_pin_t pin, ioport_mode_t mode)
{
PORT_t *base = arch_ioport_pin_to_base (pin);
PORTCFG.MPCMASK = arch_ioport_pin_to_mask (pin);
base->PIN0CTRL = mode;
}
__always_inline static void
arch_ioport_set_port_dir (ioport_port_t port,
ioport_port_mask_t mask, enum ioport_direction dir)
{
PORT_t *base = arch_ioport_port_to_base (port);
if (dir == IOPORT_DIR_OUTPUT)
{
base->DIRSET = mask;
}
else if (dir == IOPORT_DIR_INPUT)
{
base->DIRCLR = mask;
}
}
__always_inline static void
arch_ioport_set_pin_dir (ioport_pin_t pin, enum ioport_direction dir)
{
PORT_t *base = arch_ioport_pin_to_base (pin);
if (dir == IOPORT_DIR_OUTPUT)
{
base->DIRSET = arch_ioport_pin_to_mask (pin);
}
else if (dir == IOPORT_DIR_INPUT)
{
base->DIRCLR = arch_ioport_pin_to_mask (pin);
}
}
__always_inline static void
arch_ioport_set_pin_level (ioport_pin_t pin, bool level)
{
PORT_t *base = arch_ioport_pin_to_base (pin);
if (level)
{
base->OUTSET = arch_ioport_pin_to_mask (pin);
}
else
{
base->OUTCLR = arch_ioport_pin_to_mask (pin);
}
}
__always_inline static void
arch_ioport_set_port_level (ioport_port_t port,
ioport_port_mask_t mask, ioport_port_mask_t level)
{
PORT_t *base = arch_ioport_port_to_base (port);
base->OUTSET = mask & level;
base->OUTCLR = mask & ~level;
}
__always_inline static bool
arch_ioport_get_pin_level (ioport_pin_t pin)
{
PORT_t *base = arch_ioport_pin_to_base (pin);
return base->IN & arch_ioport_pin_to_mask (pin);
}
__always_inline static ioport_port_mask_t
arch_ioport_get_port_level (ioport_port_t port, ioport_port_mask_t mask)
{
PORT_t *base = arch_ioport_port_to_base (port);
return base->IN & mask;
}
__always_inline static void
arch_ioport_toggle_pin_level (ioport_pin_t pin)
{
PORT_t *base = arch_ioport_pin_to_base (pin);
base->OUTTGL = arch_ioport_pin_to_mask (pin);
}
__always_inline static void
arch_ioport_toggle_port_level (ioport_port_t port, ioport_port_mask_t mask)
{
PORT_t *base = arch_ioport_port_to_base (port);
base->OUTTGL = mask;
}
__always_inline static void
arch_ioport_set_pin_sense_mode (ioport_pin_t pin, enum ioport_sense pin_sense)
{
PORT_t *base = arch_ioport_pin_to_base (pin);
volatile uint8_t *pin_ctrl =
(&base->PIN0CTRL + arch_ioport_pin_to_index (pin));
uint8_t flags = cpu_irq_save ();
*pin_ctrl &= ~PORT_ISC_gm;
*pin_ctrl |= (pin_sense & PORT_ISC_gm);
cpu_irq_restore (flags);
}
__always_inline static void
arch_ioport_set_port_sense_mode (ioport_port_t port,
ioport_port_mask_t mask,
enum ioport_sense pin_sense)
{
PORT_t *base = arch_ioport_port_to_base (port);
volatile uint8_t *pin_ctrl = &base->PIN0CTRL;
uint8_t new_sense_bits = (pin_sense & PORT_ISC_gm);
uint8_t flags = cpu_irq_save ();
for (uint8_t i = 0; i < 8; i++)
{
if (mask & arch_ioport_pin_to_mask (i))
{
pin_ctrl[i] = (pin_ctrl[i] & ~PORT_ISC_gm) | new_sense_bits;
}
}
cpu_irq_restore (flags);
}
#endif /* IOPORT_XMEGA_H */
bacnet-stack/ports/xplained/ASF/common/services/ioport/xmega/ioport_compat.c
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/**
* \file
*
* \brief XMEGA legacy IOPORT software compatibility driver interface.
*
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "ioport_compat.h"
#if defined(IOPORT_XMEGA_COMPAT)
void ioport_configure_port_pin(void *port,
pin_mask_t pin_mask,
port_pin_flags_t flags)
{
uint8_t pin;
for (pin = 0; pin < 8; pin++) {
if (pin_mask & (1 << pin)) {
*((uint8_t *) port + PORT_PIN0CTRL + pin) = flags >> 8;
}
}
/* Select direction and initial pin state */
if (flags & IOPORT_DIR_OUTPUT) {
if (flags & IOPORT_INIT_HIGH) {
*((uint8_t *) port + PORT_OUTSET) = pin_mask;
} else {
*((uint8_t *) port + PORT_OUTCLR) = pin_mask;
}
*((uint8_t *) port + PORT_DIRSET) = pin_mask;
} else {
*((uint8_t *) port + PORT_DIRCLR) = pin_mask;
}
}
#endif
bacnet-stack/ports/xplained/ASF/common/services/ioport/xmega/ioport_compat.h
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/**
* \file
*
* \brief XMEGA legacy IOPORT software compatibility driver interface header
* file.
*
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef IOPORT_XMEGA_COMPAT_H_
#define IOPORT_XMEGA_COMPAT_H_
#include "../ioport.h"
/**
* \brief A pin mask
*
* This type is used to describe the port pin mask on the part.
*/
typedef uint8_t pin_mask_t;
/**
* \brief A PORT pin
*
* This type is used to describe the PORT pins on the part.
*/
typedef uint8_t port_pin_t;
/**
* \brief Pin configuration flags
*
* This is a bitmask containing configuration flags for the pins that shall be
* configured.
*/
typedef uint16_t port_pin_flags_t;
/**
* \brief A port id
*
* This type is used to describe the port id on the part (0 is PORTA).
*/
typedef uint8_t port_id_t;
/** \name Initial Output State Flags */
/** @{ */
#define IOPORT_INIT_LOW (0 << 1) /*!< Initial Output State Low */
#define IOPORT_INIT_HIGH (1 << 1) /*!< Initial Output State High */
/** @} */
/** \name Input/Sense Configuration Flags */
/** @{ */
#define IOPORT_BOTHEDGES (0 << 8) /*!< Sense Both Edges */
#define IOPORT_RISING (1 << 8) /*!< Sense Rising Edge */
#define IOPORT_FALLING (2 << 8) /*!< Sense Falling Edge */
#define IOPORT_LEVEL (3 << 8) /*!< Sense Low Level */
#if XMEGA_E
# define IOPORT_FORCE_ENABLE (6 << 8) /*!< Sense Force Input Enable Low Level */
#endif
#define IOPORT_INPUT_DISABLE (7 << 8) /*!< Input Buffer Disabled */
/** @} */
/** \name Output and Pull Configuration Flags */
/** @{ */
#define IOPORT_TOTEM (0 << 11) /*!< Normal push/pull output */
#define IOPORT_BUSKEEPER (1 << 11) /*!< Bus Keeper */
#define IOPORT_PULL_DOWN (2 << 11) /*!< Pull-Down (when input) */
#define IOPORT_PULL_UP (3 << 11) /*!< Pull-Up (when input) */
#define IOPORT_WIRED_OR (4 << 11) /*!< Wired OR */
#define IOPORT_WIRED_AND (5 << 11) /*!< Wired AND */
#define IOPORT_WIRED_OR_PULL_DOWN (6 << 11) /*!< Wired OR and Pull-Down */
#define IOPORT_WIRED_AND_PULL_UP (7 << 11) /*!< Wired AND and Pull-Up */
/** @} */
/** \name Inverted I/O Configuration Flags */
/** @{ */
#define IOPORT_INV_ENABLED (1 << 14) /*!< I/O is Inverted */
#define IOPORT_INV_DISABLE (0 << 14) /*!< I/O is Not Inverted */
/** @} */
/** \name Slew Rate Limit Configuration Flags */
/** @{ */
#define IOPORT_SRL_ENABLED (1 << 15) /*!< Slew Rate Limit Enabled */
#define IOPORT_SRL_DISABLED (0 << 15) /*!< Slew Rate Limit Disabled */
/** @} */
/**
* \internal
* \name PORT fields structure offset
*
* These macros are used to compute the field offset number with the PORT_t
* structure.
*/
/** @{ */
#define PORT_DIR 0x00 /*!< Data Direction */
#define PORT_DIRSET 0x01 /*!< Data Direction Set */
#define PORT_DIRCLR 0x02 /*!< Data Direction Clear */
#define PORT_DIRTGL 0x03 /*!< Data Direction Toggle */
#define PORT_OUT 0x04 /*!< Data Output Value */
#define PORT_OUTSET 0x05 /*!< Data Output Value Set */
#define PORT_OUTCLR 0x06 /*!< Data Output Value Clear */
#define PORT_OUTTGL 0x07 /*!< Data Output Value Toggle */
#define PORT_IN 0x08 /*!< Data Input Value */
#define PORT_INTCTRL 0x09 /*!< Interrupt Control */
#define PORT_INT0MASK 0x0A /*!< Interrupt 0 Mask */
#define PORT_INT1MASK 0x0B /*!< Interrupt 1 Mask */
#define PORT_INTFLAGS 0x0C /*!< Interrupt Flags */
#define PORT_PIN0CTRL 0x10 /*!< Pin 0 Configuration */
#define PORT_PIN1CTRL 0x11 /*!< Pin 1 Configuration */
#define PORT_PIN2CTRL 0x12 /*!< Pin 2 Configuration */
#define PORT_PIN3CTRL 0x13 /*!< Pin 3 Configuration */
#define PORT_PIN4CTRL 0x14 /*!< Pin 4 Configuration */
#define PORT_PIN5CTRL 0x15 /*!< Pin 5 Configuration */
#define PORT_PIN6CTRL 0x16 /*!< Pin 6 Configuration */
#define PORT_PIN7CTRL 0x17 /*!< Pin 7 Configuration */
/** @} */
static inline PORT_t *
ioport_pin_to_port (port_pin_t pin)
{
return arch_ioport_pin_to_base (pin);
}
static inline PORT_t *
ioport_id_pin_to_port (port_id_t port)
{
return arch_ioport_port_to_base (port);
}
/**
* \brief Configure the IO PORT pin function for a set of pins on a port
*
* \param port Pointer to the port
* \param pin_mask Mask containing the pins that should be configured
* \param flags Bitmask of flags specifying additional configuration
* parameters.
*/
void ioport_configure_port_pin (void *port, pin_mask_t pin_mask,
port_pin_flags_t flags);
/**
* \brief Select the port function for a single pin
*
* \param pin The pin to configure
* \param flags Bitmask of flags specifying additional configuration
* parameters.
*/
static inline void
ioport_configure_pin (port_pin_t pin, port_pin_flags_t flags)
{
ioport_configure_port_pin (arch_ioport_pin_to_base (pin),
arch_ioport_pin_to_mask (pin), flags);
}
/**
* \brief Configure a group of I/O pins on a specified port number
*
* \param port The port number
* \param pin_mask The pin mask to configure
* \param flags Bitmask of flags specifying additional configuration
* parameters.
*/
static inline void
ioport_configure_group (port_id_t port, pin_mask_t pin_mask,
port_pin_flags_t flags)
{
ioport_configure_port_pin (arch_ioport_port_to_base (port), pin_mask,
flags);
}
/**
* \brief Drive a PORT pin to a given state
*
* This function will only have an effect if \a pin is configured as
* an output.
*
* \param pin A number identifying the pin to act on.
* \param value The desired state of the pin. \a true means drive the
* pin high (towards Vdd), while \a false means drive the pin low
* (towards Vss).
*/
static inline void
ioport_set_value (port_pin_t pin, bool value)
{
arch_ioport_set_pin_level (pin, value);
}
/**
* \brief Drive a PORT pin to a low level
*
* This function will only have an effect if \a pin is configured as
* an output.
*
* \param pin A number identifying the pin to act on.
*/
static inline void
ioport_set_pin_low (port_pin_t pin)
{
arch_ioport_set_pin_level (pin, false);
}
/**
* \brief Drive a PORT pin to a high level
*
* This function will only have an effect if \a pin is configured as
* an output.
*
* \param pin A number identifying the pin to act on.
*/
static inline void
ioport_set_pin_high (port_pin_t pin)
{
arch_ioport_set_pin_level (pin, true);
}
/**
* \brief Read the current state of a PORT pin
*
* \param pin A number identifying the pin to read.
* \retval true The pin is currently high (close to Vdd)
* \retval false The pin is currently low (close to Vss)
*/
static inline bool
ioport_get_value (port_pin_t pin)
{
return arch_ioport_get_pin_level (pin);
}
/**
* \brief Read the current state of a PORT pin and test high level
*
* \param pin A number identifying the pin to read.
* \retval true The pin is currently high (close to Vdd)
* \retval false The pin is currently low (close to Vss)
*/
static inline bool
ioport_pin_is_high (port_pin_t pin)
{
return (arch_ioport_get_pin_level (pin) == true);
}
/**
* \brief Read the current state of a PORT pin and test high level
*
* \param pin A number identifying the pin to read.
* \retval true The pin is currently high (close to Vdd)
* \retval false The pin is currently low (close to Vss)
*/
static inline bool
ioport_pin_is_low (port_pin_t pin)
{
return (arch_ioport_get_pin_level (pin) == false);
}
/**
* \brief Toggle the current state of a PORT pin
*
* \param pin A number identifying the pin to act on.
*/
static inline void
ioport_toggle_pin (port_pin_t pin)
{
arch_ioport_toggle_pin_level (pin);
}
/*! \brief Drives a group of I/O pin of a port to high level.
*
* \param port_id The port number.
* \param port_mask The mask.
*/
static inline void
ioport_set_group_high (port_id_t port_id, pin_mask_t port_mask)
{
arch_ioport_set_port_level (port_id, port_mask, port_mask);
}
/*! \brief Drives a group of I/O pin of a port to low level.
*
* \param port_id The port number.
* \param port_mask The mask.
*/
static inline void
ioport_set_group_low (port_id_t port_id, pin_mask_t port_mask)
{
arch_ioport_set_port_level (port_id, port_mask, 0);
}
/*! \brief Toggles a group of I/O pin of a port.
*
* \param port_id The port number.
* \param port_mask The mask.
*/
static inline void
ioport_tgl_group (port_id_t port_id, pin_mask_t port_mask)
{
arch_ioport_toggle_port_level (port_id, port_mask);
}
#endif /* IOPORT_COMPAT_H_ */
bacnet-stack/ports/xplained/ASF/common/services/serial/serial.h
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/**
* \file
*
* \brief Serial Mode management
*
* Copyright (c) 2010 - 2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SERIAL_H_INCLUDED
#define SERIAL_H_INCLUDED
#include <parts.h>
#include "status_codes.h"
/**
* \typedef usart_if
*
* This type can be used independently to refer to USART module for the
* architecture used. It refers to the correct type definition for the
* architecture, ie. USART_t* for XMEGA or avr32_usart_t* for UC3.
*/
#if XMEGA
# include "xmega_usart/usart_serial.h"
#elif MEGA_RF
# include "megarf_usart/usart_serial.h"
#elif UC3
# include "uc3_usart/usart_serial.h"
#elif SAM
# include "sam_uart/uart_serial.h"
#else
# error Unsupported chip type
#endif
/**
*
* \defgroup serial_group Serial Interface (Serial)
*
* See \ref serial_quickstart.
*
* This is the common API for serial interface. Additional features are available
* in the documentation of the specific modules.
*
* \section serial_group_platform Platform Dependencies
*
* The serial API is partially chip- or platform-specific. While all
* platforms provide mostly the same functionality, there are some
* variations around how different bus types and clock tree structures
* are handled.
*
* The following functions are available on all platforms, but there may
* be variations in the function signature (i.e. parameters) and
* behaviour. These functions are typically called by platform-specific
* parts of drivers, and applications that aren't intended to be
* portable:
* - usart_serial_init()
* - usart_serial_putchar()
* - usart_serial_getchar()
* - usart_serial_write_packet()
* - usart_serial_read_packet()
*
*
* @{
*/
//! @}
/**
* \page serial_quickstart Quick start guide for Serial Interface service
*
* This is the quick start guide for the \ref serial_group "Serial Interface module", with
* step-by-step instructions on how to configure and use the serial in a
* selection of use cases.
*
* The use cases contain several code fragments. The code fragments in the
* steps for setup can be copied into a custom initialization function, while
* the steps for usage can be copied into, e.g., the main application function.
*
* \section serial_use_cases Serial use cases
* - \ref serial_basic_use_case
* - \subpage serial_use_case_1
*
* \section serial_basic_use_case Basic use case - transmit a character
* In this use case, the serial module is configured for:
* - Using USARTD0
* - Baudrate: 9600
* - Character length: 8 bit
* - Parity mode: Disabled
* - Stop bit: None
* - RS232 mode
*
* The use case waits for a received character on the configured USART and
* echoes the character back to the same USART.
*
* \section serial_basic_use_case_setup Setup steps
*
* \subsection serial_basic_use_case_setup_prereq Prerequisites
* -# \ref sysclk_group "System Clock Management (sysclk)"
*
* \subsection serial_basic_use_case_setup_code Example code
* The following configuration must be added to the project (typically to a
* conf_serial.h file, but it can also be added to your main application file.)
* \code
* #define USART_SERIAL &USARTD0
* #define USART_SERIAL_BAUDRATE 9600
* #define USART_SERIAL_CHAR_LENGTH USART_CHSIZE_8BIT_gc
* #define USART_SERIAL_PARITY USART_PMODE_DISABLED_gc
* #define USART_SERIAL_STOP_BIT false
* \endcode
*
* A variable for the received byte must be added:
* \code uint8_t received_byte; \endcode
*
* Add to application initialization:
* \code
* sysclk_init();
*
* static usart_serial_options_t usart_options = {
* .baudrate = USART_SERIAL_BAUDRATE,
* .charlength = USART_SERIAL_CHAR_LENGTH,
* .paritytype = USART_SERIAL_PARITY,
* .stopbits = USART_SERIAL_STOP_BIT
* };
*
* usart_serial_init(USART_SERIAL, &usart_options);
* \endcode
*
* \subsection serial_basic_use_case_setup_flow Workflow
* -# Initialize system clock:
* - \code sysclk_init(); \endcode
* -# Create serial USART options struct:
* - \code
* static usart_serial_options_t usart_options = {
* .baudrate = USART_SERIAL_BAUDRATE,
* .charlength = USART_SERIAL_CHAR_LENGTH,
* .paritytype = USART_SERIAL_PARITY,
* .stopbits = USART_SERIAL_STOP_BIT
* };
* \endcode
* -# Initialize the serial service:
* - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode
*
* \section serial_basic_use_case_usage Usage steps
*
* \subsection serial_basic_use_case_usage_code Example code
* Add to application C-file:
* \code
* usart_serial_getchar(USART_SERIAL, &received_byte);
* usart_serial_putchar(USART_SERIAL, received_byte);
* \endcode
*
* \subsection serial_basic_use_case_usage_flow Workflow
* -# Wait for reception of a character:
* - \code usart_serial_getchar(USART_SERIAL, &received_byte); \endcode
* -# Echo the character back:
* - \code usart_serial_putchar(USART_SERIAL, received_byte); \endcode
*/
/**
* \page serial_use_case_1 Advanced use case - Send a packet of serial data
*
* In this use case, the USART module is configured for:
* - Using USARTD0
* - Baudrate: 9600
* - Character length: 8 bit
* - Parity mode: Disabled
* - Stop bit: None
* - RS232 mode
*
* The use case sends a string of text through the USART.
*
* \section serial_use_case_1_setup Setup steps
*
* \subsection serial_use_case_1_setup_prereq Prerequisites
* -# \ref sysclk_group "System Clock Management (sysclk)"
*
* \subsection serial_use_case_1_setup_code Example code
* The following configuration must be added to the project (typically to a
* conf_serial.h file, but it can also be added to your main application file.):
* \code
* #define USART_SERIAL &USARTD0
* #define USART_SERIAL_BAUDRATE 9600
* #define USART_SERIAL_CHAR_LENGTH USART_CHSIZE_8BIT_gc
* #define USART_SERIAL_PARITY USART_PMODE_DISABLED_gc
* #define USART_SERIAL_STOP_BIT false
* \endcode
*
* Add to application initialization:
* \code
* sysclk_init();
*
* static usart_serial_options_t usart_options = {
* .baudrate = USART_SERIAL_BAUDRATE,
* .charlength = USART_SERIAL_CHAR_LENGTH,
* .paritytype = USART_SERIAL_PARITY,
* .stopbits = USART_SERIAL_STOP_BIT
* };
*
* usart_serial_init(USART_SERIAL, &usart_options);
* \endcode
*
* \subsection serial_use_case_1_setup_flow Workflow
* -# Initialize system clock:
* - \code sysclk_init(); \endcode
* -# Create USART options struct:
* - \code
* static usart_serial_options_t usart_options = {
* .baudrate = USART_SERIAL_BAUDRATE,
* .charlength = USART_SERIAL_CHAR_LENGTH,
* .paritytype = USART_SERIAL_PARITY,
* .stopbits = USART_SERIAL_STOP_BIT
* };
* \endcode
* -# Initialize in RS232 mode:
* - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode
*
* \section serial_use_case_1_usage Usage steps
*
* \subsection serial_use_case_1_usage_code Example code
* Add to, e.g., main loop in application C-file:
* \code
* usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String"));
* \endcode
*
* \subsection serial_use_case_1_usage_flow Workflow
* -# Write a string of text to the USART:
* - \code usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); \endcode
*/
#endif /* SERIAL_H_INCLUDED */
bacnet-stack/ports/xplained/ASF/common/services/serial/usart_serial.c
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/**
*
* \file
*
* \brief USART Serial driver functions.
*
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "serial.h"
/**
* \brief Send a sequence of bytes to USART device
*
* \param usart Base address of the USART instance.
* \param data Data buffer to read
* \param len Length of data
*
*/
status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data,
size_t len)
{
while (len) {
usart_serial_putchar(usart, *data);
len--;
data++;
}
return STATUS_OK;
}
/**
* \brief Receive a sequence of bytes from USART device
*
* \param usart Base address of the USART instance.
* \param data Data buffer to write
* \param len Length of data
*
*/
status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data,
size_t len)
{
while (len) {
usart_serial_getchar(usart, data);
len--;
data++;
}
return STATUS_OK;
}
bacnet-stack/ports/xplained/ASF/common/services/serial/xmega_usart/usart_serial.h
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/**
* \file
*
* This file defines a useful set of functions for the Serial interface on AVR
* XMEGA devices.
*
* Copyright (c) 2009-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _USART_SERIAL_H_
#define _USART_SERIAL_H_
#include "compiler.h"
#include "sysclk.h"
#include "status_codes.h"
#include "usart.h"
/*! \name Serial Management Configuration
*/
//! @{
#include "conf_usart_serial.h"
//! @}
typedef usart_rs232_options_t usart_serial_options_t;
typedef USART_t *usart_if;
/*! \brief Initializes the Usart in master mode.
*
* \param usart Base address of the USART instance.
* \param options Options needed to set up RS232 communication (see \ref usart_serial_options_t).
*
* \retval true if the initialization was successful
* \retval false if initialization failed (error in baud rate calculation)
*/
static inline bool usart_serial_init(usart_if usart, const
usart_serial_options_t *options)
{
// USART options.
usart_rs232_options_t usart_rs232_options;
usart_rs232_options.charlength = options->charlength;
usart_rs232_options.paritytype = options->paritytype;
usart_rs232_options.stopbits = options->stopbits;
usart_rs232_options.baudrate = options->baudrate;
#ifdef USARTC0
if((uint16_t)usart == (uint16_t)&USARTC0) {
sysclk_enable_module(SYSCLK_PORT_C,PR_USART0_bm);
}
#endif
#ifdef USARTC1
if((uint16_t)usart == (uint16_t)&USARTC1) {
sysclk_enable_module(SYSCLK_PORT_C,PR_USART1_bm);
}
#endif
#ifdef USARTD0
if((uint16_t)usart == (uint16_t)&USARTD0) {
sysclk_enable_module(SYSCLK_PORT_D,PR_USART0_bm);
}
#endif
#ifdef USARTD1
if((uint16_t)usart == (uint16_t)&USARTD1) {
sysclk_enable_module(SYSCLK_PORT_D,PR_USART1_bm);
}
#endif
#ifdef USARTE0
if((uint16_t)usart == (uint16_t)&USARTE0) {
sysclk_enable_module(SYSCLK_PORT_E,PR_USART0_bm);
}
#endif
#ifdef USARTE1
if((uint16_t)usart == (uint16_t)&USARTE1) {
sysclk_enable_module(SYSCLK_PORT_E,PR_USART1_bm);
}
#endif
#ifdef USARTF0
if((uint16_t)usart == (uint16_t)&USARTF0) {
sysclk_enable_module(SYSCLK_PORT_F,PR_USART0_bm);
}
#endif
#ifdef USARTF1
if((uint16_t)usart == (uint16_t)&USARTF1) {
sysclk_enable_module(SYSCLK_PORT_F,PR_USART1_bm);
}
#endif
if (usart_init_rs232(usart, &usart_rs232_options)) {
return true;
}
else {
return false;
}
}
/*! \brief Sends a character with the USART.
*
* \param usart Base address of the USART instance.
* \param c Character to write.
*
* \return Status code
*/
static inline enum status_code usart_serial_putchar(usart_if usart, uint8_t c)
{
return usart_putchar(usart, c);
}
/*! \brief Waits until a character is received, and returns it.
*
* \param usart Base address of the USART instance.
* \param data Data to read
*
*/
static inline void usart_serial_getchar(usart_if usart, uint8_t *data)
{
*data = usart_getchar(usart);
}
/**
* \brief Send a sequence of bytes to USART device
*
* \param usart Base address of the USART instance.
* \param data Data buffer to read
* \param len Length of data
*
*/
extern status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data, size_t len);
/**
* \brief Receive a sequence of bytes from USART device
*
* \param usart Base address of the USART instance.
* \param data Data buffer to write
* \param len Length of data
*
*/
extern status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data, size_t len);
#endif // _USART_SERIAL_H_
bacnet-stack/ports/xplained/ASF/common/services/sleepmgr/sleepmgr.h
+252
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/**
* \file
*
* \brief Sleep manager
*
* Copyright (c) 2010 - 2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SLEEPMGR_H
#define SLEEPMGR_H
#include <compiler.h>
#include <parts.h>
#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E)
# include "sam/sleepmgr.h"
#elif XMEGA
# include "xmega/sleepmgr.h"
#elif UC3
# include "uc3/sleepmgr.h"
#elif SAM4L
# include "sam4l/sleepmgr.h"
#else
# error Unsupported device.
#endif
/**
* \defgroup sleepmgr_group Sleep manager
*
* The sleep manager is a service for ensuring that the device is not put to
* sleep in deeper sleep modes than the system (e.g., peripheral drivers,
* services or the application) allows at any given time.
*
* It is based on the use of lock counting for the individual sleep modes, and
* will put the device to sleep in the shallowest sleep mode that has a non-zero
* lock count. The drivers/services/application can change these counts by use
* of \ref sleepmgr_lock_mode and \ref sleepmgr_unlock_mode.
* Refer to \ref sleepmgr_mode for a list of the sleep modes available for
* locking, and the device datasheet for information on their effect.
*
* The application must supply the file \ref conf_sleepmgr.h.
*
* For the sleep manager to be enabled, the symbol \ref CONFIG_SLEEPMGR_ENABLE
* must be defined, e.g., in \ref conf_sleepmgr.h. If this symbol is not
* defined, the functions are replaced with dummy functions and no RAM is used.
*
* @{
*/
/**
* \def CONFIG_SLEEPMGR_ENABLE
* \brief Configuration symbol for enabling the sleep manager
*
* If this symbol is not defined, the functions of this service are replaced
* with dummy functions. This is useful for reducing code size and execution
* time if the sleep manager is not needed in the application.
*
* This symbol may be defined in \ref conf_sleepmgr.h.
*/
#if defined(__DOXYGEN__) && !defined(CONFIG_SLEEPMGR_ENABLE)
# define CONFIG_SLEEPMGR_ENABLE
#endif
/**
* \enum sleepmgr_mode
* \brief Sleep mode locks
*
* Identifiers for the different sleep mode locks.
*/
/**
* \brief Initialize the lock counts
*
* Sets all lock counts to 0, except the very last one, which is set to 1. This
* is done to simplify the algorithm for finding the deepest allowable sleep
* mode in \ref sleepmgr_enter_sleep.
*/
static inline void
sleepmgr_init (void)
{
#ifdef CONFIG_SLEEPMGR_ENABLE
uint8_t i;
for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++)
{
sleepmgr_locks[i] = 0;
}
sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1;
#endif /* CONFIG_SLEEPMGR_ENABLE */
}
/**
* \brief Increase lock count for a sleep mode
*
* Increases the lock count for \a mode to ensure that the sleep manager does
* not put the device to sleep in the deeper sleep modes.
*
* \param mode Sleep mode to lock.
*/
static inline void
sleepmgr_lock_mode (enum sleepmgr_mode mode)
{
#ifdef CONFIG_SLEEPMGR_ENABLE
irqflags_t flags;
Assert (sleepmgr_locks[mode] < 0xff);
// Enter a critical section
flags = cpu_irq_save ();
++sleepmgr_locks[mode];
// Leave the critical section
cpu_irq_restore (flags);
#else
UNUSED (mode);
#endif /* CONFIG_SLEEPMGR_ENABLE */
}
/**
* \brief Decrease lock count for a sleep mode
*
* Decreases the lock count for \a mode. If the lock count reaches 0, the sleep
* manager can put the device to sleep in the deeper sleep modes.
*
* \param mode Sleep mode to unlock.
*/
static inline void
sleepmgr_unlock_mode (enum sleepmgr_mode mode)
{
#ifdef CONFIG_SLEEPMGR_ENABLE
irqflags_t flags;
Assert (sleepmgr_locks[mode]);
// Enter a critical section
flags = cpu_irq_save ();
--sleepmgr_locks[mode];
// Leave the critical section
cpu_irq_restore (flags);
#else
UNUSED (mode);
#endif /* CONFIG_SLEEPMGR_ENABLE */
}
/**
* \brief Retrieves the deepest allowable sleep mode
*
* Searches through the sleep mode lock counts, starting at the shallowest sleep
* mode, until the first non-zero lock count is found. The deepest allowable
* sleep mode is then returned.
*/
static inline enum sleepmgr_mode
sleepmgr_get_sleep_mode (void)
{
enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE;
#ifdef CONFIG_SLEEPMGR_ENABLE
uint8_t *lock_ptr = sleepmgr_locks;
// Find first non-zero lock count, starting with the shallowest modes.
while (!(*lock_ptr))
{
lock_ptr++;
sleep_mode++;
}
// Catch the case where one too many sleepmgr_unlock_mode() call has been
// performed on the deepest sleep mode.
Assert ((uintptr_t) (lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES);
#endif /* CONFIG_SLEEPMGR_ENABLE */
return sleep_mode;
}
/**
* \fn sleepmgr_enter_sleep
* \brief Go to sleep in the deepest allowed mode
*
* Searches through the sleep mode lock counts, starting at the shallowest sleep
* mode, until the first non-zero lock count is found. The device is then put to
* sleep in the sleep mode that corresponds to the lock.
*
* \note This function enables interrupts before going to sleep, and will leave
* them enabled upon return. This also applies if sleep is skipped due to ACTIVE
* mode being locked.
*/
static inline void
sleepmgr_enter_sleep (void)
{
#ifdef CONFIG_SLEEPMGR_ENABLE
enum sleepmgr_mode sleep_mode;
cpu_irq_disable ();
// Find the deepest allowable sleep mode
sleep_mode = sleepmgr_get_sleep_mode ();
// Return right away if first mode (ACTIVE) is locked.
if (sleep_mode == SLEEPMGR_ACTIVE)
{
cpu_irq_enable ();
return;
}
// Enter the deepest allowable sleep mode with interrupts enabled
sleepmgr_sleep (sleep_mode);
#else
cpu_irq_enable ();
#endif /* CONFIG_SLEEPMGR_ENABLE */
}
//! @}
#endif /* SLEEPMGR_H */
bacnet-stack/ports/xplained/ASF/common/services/sleepmgr/xmega/sleepmgr.c
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/**
* \file
*
* \brief Sleep manager
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <compiler.h>
#include <sleepmgr.h>
#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES];
enum SLEEP_SMODE_enum sleepmgr_configs[SLEEPMGR_NR_OF_MODES] = {
SLEEP_SMODE_IDLE_gc,
SLEEP_SMODE_ESTDBY_gc,
SLEEP_SMODE_PSAVE_gc,
SLEEP_SMODE_STDBY_gc,
SLEEP_SMODE_PDOWN_gc,
};
#endif /* CONFIG_SLEEPMGR_ENABLE */
bacnet-stack/ports/xplained/ASF/common/services/sleepmgr/xmega/sleepmgr.h
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/**
* \file
*
* \brief AVR XMEGA Sleep manager implementation
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef XMEGA_SLEEPMGR_H
#define XMEGA_SLEEPMGR_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <compiler.h>
#include <conf_sleepmgr.h>
#include <sleep.h>
/**
* \weakgroup sleepmgr_group
* @{
*/
enum sleepmgr_mode
{
//! Active mode.
SLEEPMGR_ACTIVE = 0,
//! Idle mode.
SLEEPMGR_IDLE,
//! Extended Standby mode.
SLEEPMGR_ESTDBY,
//! Power Save mode.
SLEEPMGR_PSAVE,
//! Standby mode.
SLEEPMGR_STDBY,
//! Power Down mode.
SLEEPMGR_PDOWN,
SLEEPMGR_NR_OF_MODES,
};
/**
* \internal
* \name Internal arrays
* @{
*/
#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
//! Sleep mode lock counters
extern uint8_t sleepmgr_locks[];
/**
* \brief Look-up table with sleep mode configurations
* \note This is located in program memory (Flash) as it is constant.
*/
extern enum SLEEP_SMODE_enum sleepmgr_configs[];
#endif /* CONFIG_SLEEPMGR_ENABLE */
//! @}
static inline void sleepmgr_sleep (const enum sleepmgr_mode sleep_mode)
{
Assert (sleep_mode != SLEEPMGR_ACTIVE);
#ifdef CONFIG_SLEEPMGR_ENABLE
sleep_set_mode (sleepmgr_configs[sleep_mode - 1]);
sleep_enable ();
cpu_irq_enable ();
sleep_enter ();
sleep_disable ();
#else
cpu_irq_enable ();
#endif /* CONFIG_SLEEPMGR_ENABLE */
}
//! @}
#ifdef __cplusplus
}
#endif
#endif /* XMEGA_SLEEPMGR_H */