Added demo port for BACnetDevelopmentKit.com board.

2009-05-04 22:14:45 +00:00
parent 68bdca6fbe
commit eb06ee919a
30 changed files with 5632 additions and 0 deletions
@@ -0,0 +1,63 @@
+/**************************************************************************
+*
+* Copyright (C) 2009 Steve Karg <skarg@users.sourceforge.net>
+*
+* Permission is hereby granted, free of charge, to any person obtaining
+* a copy of this software and associated documentation files (the
+* "Software"), to deal in the Software without restriction, including
+* without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to
+* permit persons to whom the Software is furnished to do so, subject to
+* the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*********************************************************************/
+#include "hardware.h"
+
+void init(
+    void)
+{
+    /* Initialize the Clock Prescaler for ATmega48/88/168 */
+    /* The default CLKPSx bits are factory set to 0011 */
+    /* Enbable the Clock Prescaler */
+    CLKPR = _BV(CLKPCE);
+    /* CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
+       ------ ------ ------ ------ ---------------------
+       0      0      0      0             1
+       0      0      0      1             2
+       0      0      1      0             4
+       0      0      1      1             8
+       0      1      0      0            16
+       0      1      0      1            32
+       0      1      1      0            64
+       0      1      1      1           128
+       1      0      0      0           256
+       1      x      x      x      Reserved
+     */
+    /* Set the CLKPS3..0 bits to Prescaler of 1 */
+    CLKPR = 0;
+    /* Initialize I/O ports */
+    /* For Port DDRx (Data Direction) Input=0, Output=1 */
+    /* For Port PORTx (Bit Value) TriState=0, High=1 */
+    DDRA = 0;
+    PORTA = 0;
+    DDRB = 0;
+    PORTB = 0;
+    DDRC = 0;
+    PORTC = 0;
+    DDRD = 0;
+    PORTD = 0;
+    /* Configure the watchdog timer - Disabled for testing */
+    BIT_CLEAR(MCUSR, WDRF);
+    WDTCSR = 0;
+}