Add clear of MCU status registers at initialization.
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@@ -147,8 +147,8 @@ DEFINES =
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OPTIMIZE_FLAGS = -mcall-prologues
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OPTIMIZE_FLAGS = -mcall-prologues
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OPTIMIZE_FLAGS += -finline-functions-called-once
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OPTIMIZE_FLAGS += -finline-functions-called-once
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# default is for debugging from AVR Studio
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# default is for building from AVR Studio
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OPTIMIZATION = -O0 $(OPTIMIZE_FLAGS)
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OPTIMIZATION = -Os $(OPTIMIZE_FLAGS)
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DEBUGGING = -g
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DEBUGGING = -g
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ifeq (${BUILD},debug)
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ifeq (${BUILD},debug)
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OPTIMIZATION = -O0
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OPTIMIZATION = -O0
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File diff suppressed because one or more lines are too long
@@ -1208,6 +1208,7 @@ uint16_t dlmstp_receive(
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MSTP_Flag.ReceivedValidFrameNotForUs = false;
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MSTP_Flag.ReceivedValidFrameNotForUs = false;
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}
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}
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if (Receive_State == MSTP_RECEIVE_STATE_IDLE) {
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if (Receive_State == MSTP_RECEIVE_STATE_IDLE) {
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/* only do master state machine while rx is idle */
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while (MSTP_Master_Node_FSM()) {
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while (MSTP_Master_Node_FSM()) {
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/* do nothing while some states fast transition */
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/* do nothing while some states fast transition */
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};
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};
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@@ -30,7 +30,9 @@
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void init(
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void init(
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void)
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void)
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{
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{
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/* Initialize the Clock Prescaler for ATmega48/88/168 */
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/* clear the MCU Status Register */
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MCUSR = 0;
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/* Initialize the Clock Prescaler */
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/* The default CLKPSx bits are factory set to 0011 */
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/* The default CLKPSx bits are factory set to 0011 */
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/* Enbable the Clock Prescaler */
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/* Enbable the Clock Prescaler */
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CLKPR = _BV(CLKPCE);
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CLKPR = _BV(CLKPCE);
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@@ -99,7 +99,6 @@ void watchdog_init(
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}
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}
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wdt_enable(value);
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wdt_enable(value);
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} else {
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} else {
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MCUSR = 0;
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wdt_disable();
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wdt_disable();
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}
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}
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}
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}
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