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Steve Karg
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/**
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* \file
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*
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* \brief XMEGA TWI master source file.
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*
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* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#include "twim.h"
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/* Master Transfer Descriptor */
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static struct {
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TWI_t *bus; // Bus register interface
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twi_package_t *pkg; // Bus message descriptor
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int addr_count; // Bus transfer address data counter
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unsigned int data_count; // Bus transfer payload data counter
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bool read; // Bus transfer direction
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bool locked; // Bus busy or unavailable
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volatile status_code_t status; // Transfer status
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} transfer;
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/**
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* \internal
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*
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* \brief TWI Master Interrupt Vectors
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*
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* The TWI master interrupt request entry points are conditionally compiled
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* for the TWI interfaces supported by the XMEGA MCU variant. All of these
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* entry points call a common service function, twim_interrupt_handler(),
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* to handle bus events. This handler uses the bus interface and message
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* parameters specified in the global \c transfer structure.
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*/
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static void twim_interrupt_handler(void);
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#ifdef TWIC
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ISR(TWIC_TWIM_vect)
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{
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twim_interrupt_handler();
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}
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#endif
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#ifdef TWID
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ISR(TWID_TWIM_vect)
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{
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twim_interrupt_handler();
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}
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#endif
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#ifdef TWIE
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ISR(TWIE_TWIM_vect)
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{
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twim_interrupt_handler();
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}
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#endif
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#ifdef TWIF
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ISR(TWIF_TWIM_vect)
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{
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twim_interrupt_handler();
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}
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#endif
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/**
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* \internal
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*
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* \brief Test for an idle bus state.
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*
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* Software can determine the TWI master bus state (unknown, idle, owner, or
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* busy) by reading the bus master status register:
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*
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* TWI_MASTER_BUSSTATE_UNKNOWN_gc Bus state is unknown.
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* TWI_MASTER_BUSSTATE_IDLE_gc Bus state is idle.
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* TWI_MASTER_BUSSTATE_OWNER_gc Bus state is owned by the master.
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* TWI_MASTER_BUSSTATE_BUSY_gc Bus state is busy.
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*
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* \param twi Base address of the TWI (i.e. &TWI_t).
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*
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* \retval true The bus is currently idle.
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* \retval false The bus is currently busy.
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*/
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static inline bool twim_idle(const TWI_t * twi)
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{
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return ((twi->MASTER.STATUS & TWI_MASTER_BUSSTATE_gm)
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== TWI_MASTER_BUSSTATE_IDLE_gc);
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}
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/**
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* \internal
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*
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* \brief Get exclusive access to global TWI resources.
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*
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* Wait to acquire bus hardware interface and ISR variables.
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*
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* \param no_wait Set \c true to return instead of doing busy-wait (spin-lock).
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*
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* \return STATUS_OK if the bus is acquired, else ERR_BUSY.
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*/
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static inline status_code_t twim_acquire(bool no_wait)
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{
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while (transfer.locked) {
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if (no_wait) {
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return ERR_BUSY;
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}
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}
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irqflags_t const flags = cpu_irq_save();
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transfer.locked = true;
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transfer.status = OPERATION_IN_PROGRESS;
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cpu_irq_restore(flags);
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return STATUS_OK;
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}
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/**
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* \internal
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*
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* \brief Release exclusive access to global TWI resources.
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*
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* Release bus hardware interface and ISR variables previously locked by
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* a call to \ref twim_acquire(). This function will busy-wait for
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* pending driver operations to complete.
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*
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* \return status_code_t
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* - STATUS_OK if the transfer completes
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* - ERR_BUSY to indicate an unavailable bus
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* - ERR_IO_ERROR to indicate a bus transaction error
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* - ERR_NO_MEMORY to indicate buffer errors
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* - ERR_PROTOCOL to indicate an unexpected bus state
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*/
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static inline status_code_t twim_release(void)
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{
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/* First wait for the driver event handler to indicate something
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* other than a transfer in-progress, then test the bus interface
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* for an Idle bus state.
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*/
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while (OPERATION_IN_PROGRESS == transfer.status);
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while (!twim_idle(transfer.bus)) {
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barrier();
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}
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status_code_t const status = transfer.status;
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transfer.locked = false;
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return status;
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}
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/**
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* \internal
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*
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* \brief TWI master write interrupt handler.
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*
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* Handles TWI transactions (master write) and responses to (N)ACK.
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*/
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static inline void twim_write_handler(void)
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{
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TWI_t *const bus = transfer.bus;
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twi_package_t *const pkg = transfer.pkg;
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if (transfer.addr_count < pkg->addr_length) {
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const uint8_t *const data = pkg->addr;
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bus->MASTER.DATA = data[transfer.addr_count++];
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} else if (transfer.data_count < pkg->length) {
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if (transfer.read) {
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/* Send repeated START condition (Address|R/W=1). */
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bus->MASTER.ADDR |= 0x01;
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} else {
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const uint8_t *const data = pkg->buffer;
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bus->MASTER.DATA = data[transfer.data_count++];
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}
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} else {
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/* Send STOP condition to complete the transaction. */
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bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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transfer.status = STATUS_OK;
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}
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}
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/**
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* \internal
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*
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* \brief TWI master read interrupt handler.
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*
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* This is the master read interrupt handler that takes care of
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* reading bytes from the TWI slave.
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*/
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static inline void twim_read_handler(void)
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{
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TWI_t *const bus = transfer.bus;
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twi_package_t *const pkg = transfer.pkg;
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if (transfer.data_count < pkg->length) {
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uint8_t *const data = pkg->buffer;
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data[transfer.data_count++] = bus->MASTER.DATA;
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/* If there is more to read, issue ACK and start a byte read.
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* Otherwise, issue NACK and STOP to complete the transaction.
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*/
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if (transfer.data_count < pkg->length) {
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bus->MASTER.CTRLC = TWI_MASTER_CMD_RECVTRANS_gc;
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} else {
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bus->MASTER.CTRLC = TWI_MASTER_ACKACT_bm | TWI_MASTER_CMD_STOP_gc;
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transfer.status = STATUS_OK;
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}
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} else {
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/* Issue STOP and buffer overflow condition. */
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bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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transfer.status = ERR_NO_MEMORY;
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}
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}
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/**
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* \internal
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*
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* \brief Common TWI master interrupt service routine.
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*
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* Check current status and calls the appropriate handler.
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*/
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static void twim_interrupt_handler(void)
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{
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uint8_t const master_status = transfer.bus->MASTER.STATUS;
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if (master_status & TWI_MASTER_ARBLOST_bm) {
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transfer.bus->MASTER.STATUS = master_status | TWI_MASTER_ARBLOST_bm;
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transfer.bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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transfer.status = ERR_BUSY;
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} else if ((master_status & TWI_MASTER_BUSERR_bm) ||
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(master_status & TWI_MASTER_RXACK_bm)) {
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transfer.bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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transfer.status = ERR_IO_ERROR;
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} else if (master_status & TWI_MASTER_WIF_bm) {
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twim_write_handler();
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} else if (master_status & TWI_MASTER_RIF_bm) {
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twim_read_handler();
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} else {
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transfer.status = ERR_PROTOCOL;
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}
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}
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/**
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* \brief Initialize the twi master module
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*
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* \param twi Base address of the TWI (i.e. &TWIC).
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* \param *opt Options for initializing the twi module
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* (see \ref twi_options_t)
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* \retval STATUS_OK Transaction is successful
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* \retval ERR_INVALID_ARG Invalid arguments in \c opt.
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*/
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status_code_t twi_master_init(TWI_t * twi,
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const twi_options_t * opt)
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{
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uint8_t const ctrla =
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CONF_TWIM_INTLVL | TWI_MASTER_RIEN_bm | TWI_MASTER_WIEN_bm |
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TWI_MASTER_ENABLE_bm;
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twi->MASTER.BAUD = opt->speed_reg;
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twi->MASTER.CTRLA = ctrla;
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twi->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc;
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transfer.locked = false;
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transfer.status = STATUS_OK;
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/* Enable configured PMIC interrupt level. */
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PMIC.CTRL |= CONF_PMIC_INTLVL;
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cpu_irq_enable();
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return STATUS_OK;
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}
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/**
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* \brief Perform a TWI master write or read transfer.
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*
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* This function is a TWI Master write or read transaction.
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*
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* \param twi Base address of the TWI (i.e. &TWI_t).
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* \param package Package information and data
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* (see \ref twi_package_t)
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* \param read Selects the transfer direction
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*
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* \return status_code_t
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* - STATUS_OK if the transfer completes
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* - ERR_BUSY to indicate an unavailable bus
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* - ERR_IO_ERROR to indicate a bus transaction error
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* - ERR_NO_MEMORY to indicate buffer errors
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* - ERR_PROTOCOL to indicate an unexpected bus state
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* - ERR_INVALID_ARG to indicate invalid arguments.
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*/
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status_code_t twi_master_transfer(TWI_t * twi,
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const twi_package_t * package,
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bool read)
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{
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/* Do a sanity check on the arguments. */
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if ((twi == NULL) || (package == NULL)) {
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return ERR_INVALID_ARG;
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}
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/* Initiate a transaction when the bus is ready. */
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status_code_t status = twim_acquire(package->no_wait);
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if (STATUS_OK == status) {
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transfer.bus = (TWI_t *) twi;
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transfer.pkg = (twi_package_t *) package;
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transfer.addr_count = 0;
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transfer.data_count = 0;
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transfer.read = read;
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uint8_t const chip = (package->chip) << 1;
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if (package->addr_length || (false == read)) {
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transfer.bus->MASTER.ADDR = chip;
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} else if (read) {
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transfer.bus->MASTER.ADDR = chip | 0x01;
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}
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status = twim_release();
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}
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return status;
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}
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