dali/bacnet_stack
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

adjust root folder

Browse Source
This commit is contained in:
Steve Karg
2019-10-08 23:47:53 -05:00
parent b6fc50ddea
commit a42e8f507c
1258 changed files with 26 additions and 214 deletions
Download Patch File Download Diff File Expand all files Collapse all files
ports/xplained/ASF/xmega/drivers/adc/adc.c
+297
View File
@@ -0,0 +1,297 @@
/**
* \file
*
* \brief AVR XMEGA Analog to Digital Converter driver
*
* Copyright (C) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <compiler.h>
#include <adc.h>
/**
* \ingroup adc_module_group
* @{
*/
/** \name ADC interrupt callback function */
/** @{ */
#ifdef ADCA
/**
* \internal
* \brief ADC A enable counter
*
* This is used to ensure that ADC A is not inadvertently disabled when its
* module or channel configurations are updated.
*/
static uint8_t adca_enable_count;
# ifdef CONFIG_ADC_CALLBACK_ENABLE
/**
* \internal
* \brief ADC A interrupt callback function pointer
*/
adc_callback_t adca_callback;
# endif
#endif
#ifdef ADCB
/**
* \internal
* \brief ADC B enable counter
*
* This is used to ensure that ADC B is not inadvertently disabled when its
* module or channel configurations are updated.
*/
static uint8_t adcb_enable_count;
# ifdef CONFIG_ADC_CALLBACK_ENABLE
/**
* \internal
* \brief ADC B interrupt callback function pointer
*/
adc_callback_t adcb_callback;
# endif
#endif
#if defined(CONFIG_ADC_CALLBACK_ENABLE) || defined(__DOXYGEN__)
/**
* \brief Set ADC interrupt callback function
*
* Sets a new callback function for interrupts on the specified ADC.
*
* \param adc Pointer to ADC module.
* \param callback Pointer to the callback function to set.
*/
void adc_set_callback(ADC_t * adc,
adc_callback_t callback)
{
irqflags_t flags;
Assert(callback);
flags = cpu_irq_save();
#ifdef ADCA
if ((uintptr_t) adc == (uintptr_t) & ADCA) {
adca_callback = callback;
} else
#endif
#ifdef ADCB
if ((uintptr_t) adc == (uintptr_t) & ADCB) {
adcb_callback = callback;
} else
#endif
{
Assert(0);
}
cpu_irq_restore(flags);
}
#endif /* CONFIG_ADC_CALLBACK_ENABLE */
/** @} */
/** \name Internal functions for driver */
/** @{ */
/**
* \internal
* \brief Enable peripheral clock for ADC
*
* Checks if the enable count for the ADC is zero, then increments it. If the
* count was zero, the peripheral clock is enabled. Otherwise, it is already
* enabled.
*
* \param adc Pointer to ADC module.
*/
void adc_enable_clock(ADC_t * adc);
void adc_enable_clock(ADC_t * adc)
{
#ifdef ADCA
if ((uintptr_t) adc == (uintptr_t) (&ADCA)) {
Assert(adca_enable_count < 0xff);
if (!adca_enable_count++) {
sysclk_enable_module(SYSCLK_PORT_A, SYSCLK_ADC);
}
} else
#endif
#ifdef ADCB
if ((uintptr_t) adc == (uintptr_t) (&ADCB)) {
Assert(adcb_enable_count < 0xff);
if (!adcb_enable_count++) {
sysclk_enable_module(SYSCLK_PORT_B, SYSCLK_ADC);
}
} else
#endif
{
Assert(0);
}
}
/**
* \internal
* \brief Disable peripheral clock for ADC
*
* Decrements the enable count for the ADC, then disables its peripheral clock
* if the count hit zero. If the count did not hit zero, it indicates the ADC is
* enabled.
*
* \param adc Pointer to ADC module
*/
void adc_disable_clock(ADC_t * adc);
void adc_disable_clock(ADC_t * adc)
{
#ifdef ADCA
if ((uintptr_t) adc == (uintptr_t) (&ADCA)) {
Assert(adca_enable_count);
if (!--adca_enable_count) {
sysclk_disable_module(SYSCLK_PORT_A, SYSCLK_ADC);
}
} else
#endif
#ifdef ADCB
if ((uintptr_t) adc == (uintptr_t) (&ADCB)) {
Assert(adcb_enable_count);
if (!--adcb_enable_count) {
sysclk_disable_module(SYSCLK_PORT_B, SYSCLK_ADC);
}
} else
#endif
{
Assert(0);
}
}
/** @} */
/** \name ADC module management */
/** @{ */
/**
* \brief Enable ADC
*
* Enables the ADC and locks IDLE mode for the sleep manager.
*
* \param adc Pointer to ADC module
*
* \note To ensure accurate conversions, please wait for at least
* the specified start-up time between enabling the ADC module, and starting
* a conversion. For most XMEGA devices the start-up time is specified
* to be a maximum of 24 ADC clock cycles. Please verify the start-up time for
* the device in use.
*/
void adc_enable(ADC_t * adc)
{
irqflags_t flags = cpu_irq_save();
adc_enable_clock(adc);
adc->CTRLA |= ADC_ENABLE_bm;
cpu_irq_restore(flags);
sleepmgr_lock_mode(SLEEPMGR_IDLE);
}
/**
* \brief Disable ADC
*
* Disables the ADC and unlocks IDLE mode for the sleep manager.
*
* \param adc Pointer to ADC module
*/
void adc_disable(ADC_t * adc)
{
irqflags_t flags = cpu_irq_save();
adc->CTRLA &= ~ADC_ENABLE_bm;
adc_disable_clock(adc);
cpu_irq_restore(flags);
sleepmgr_unlock_mode(SLEEPMGR_IDLE);
}
/**
* \brief Check if the ADC is enabled
*
* \param adc Pointer to ADC module.
*
* \retval true if ADC is enabled.
* \retval false if ADC is disabled.
*/
bool adc_is_enabled(ADC_t * adc)
{
/* It is sufficient to return the state of the ADC enable counters
* since all driver functions that change the counts are protected
* against interrupts and only the enable/disable functions leave the
* counts incremented/decremented upon return.
*/
#ifdef ADCA
if ((uintptr_t) adc == (uintptr_t) & ADCA) {
return adca_enable_count;
} else
#endif
#ifdef ADCB
if ((uintptr_t) adc == (uintptr_t) & ADCB) {
return adcb_enable_count;
} else
#endif
{
Assert(0);
return false;
}
}
/** @} */
/** @} */
ports/xplained/ASF/xmega/drivers/adc/adc.h
+2375
View File
File diff suppressed because it is too large Load Diff
ports/xplained/ASF/xmega/drivers/adc/xmega_aau/adc_aau.c
+370
View File
@@ -0,0 +1,370 @@
/**
* \file
*
* \brief AVR XMEGA A/AU specific ADC driver implementation
*
* Copyright (C) 2012-2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "../adc.h"
/**
* \ingroup adc_module_group
* @{
*/
/** \name Internal functions for driver */
/** @{ */
extern void adc_enable_clock(ADC_t * adc);
extern void adc_disable_clock(ADC_t * adc);
/** @} */
/** \name ADC interrupt callback function */
/** @{ */
#ifdef ADCA
# ifdef CONFIG_ADC_CALLBACK_ENABLE
extern adc_callback_t adca_callback;
/**
* \internal
* \brief ISR for channel 0 on ADC A
*
* Calls the callback function that has been set for the ADC when the channel's
* interrupt flag is set, if its interrupt has been enabled.
*/
ISR(ADCA_CH0_vect)
{
adca_callback(&ADCA, ADC_CH0, adc_get_result(&ADCA, ADC_CH0));
}
/**
* \internal
* \brief ISR for channel 1 on ADC A
*
* Calls the callback function that has been set for the ADC when the channel's
* interrupt flag is set, if its interrupt has been enabled.
*/
ISR(ADCA_CH1_vect)
{
adca_callback(&ADCA, ADC_CH1, adc_get_result(&ADCA, ADC_CH1));
}
/**
* \internal
* \brief ISR for channel 2 on ADC A
*
* Calls the callback function that has been set for the ADC when the channel's
* interrupt flag is set, if its interrupt has been enabled.
*/
ISR(ADCA_CH2_vect)
{
adca_callback(&ADCA, ADC_CH2, adc_get_result(&ADCA, ADC_CH2));
}
/**
* \internal
* \brief ISR for channel 3 on ADC A
*
* Calls the callback function that has been set for the ADC when the channel's
* interrupt flag is set, if its interrupt has been enabled.
*/
ISR(ADCA_CH3_vect)
{
adca_callback(&ADCA, ADC_CH3, adc_get_result(&ADCA, ADC_CH3));
}
# endif
#endif
#ifdef ADCB
# ifdef CONFIG_ADC_CALLBACK_ENABLE
extern adc_callback_t adcb_callback;
/**
* \internal
* \brief ISR for channel 0 on ADC B
*
* Calls the callback function that has been set for the ADC when the channel's
* interrupt flag is set, if its interrupt has been enabled.
*/
ISR(ADCB_CH0_vect)
{
adcb_callback(&ADCB, ADC_CH0, adc_get_result(&ADCB, ADC_CH0));
}
/**
* \internal
* \brief ISR for channel 1 on ADC B
*
* Calls the callback function that has been set for the ADC when the channel's
* interrupt flag is set, if its interrupt has been enabled.
*/
ISR(ADCB_CH1_vect)
{
adcb_callback(&ADCB, ADC_CH1, adc_get_result(&ADCB, ADC_CH1));
}
/**
* \internal
* \brief ISR for channel 2 on ADC B
*
* Calls the callback function that has been set for the ADC when the channel's
* interrupt flag is set, if its interrupt has been enabled.
*/
ISR(ADCB_CH2_vect)
{
adcb_callback(&ADCB, ADC_CH2, adc_get_result(&ADCB, ADC_CH2));
}
/**
* \internal
* \brief ISR for channel 3 on ADC B
*
* Calls the callback function that has been set for the ADC when the channel's
* interrupt flag is set, if its interrupt has been enabled.
*/
ISR(ADCB_CH3_vect)
{
adcb_callback(&ADCB, ADC_CH3, adc_get_result(&ADCB, ADC_CH3));
}
# endif
#endif
/** @} */
/** \name ADC module configuration */
/** @{ */
/**
* \brief Write configuration to ADC module
*
* Disables the ADC and flushes its pipeline before writing the specified
* configuration and factory calibration value to it. If the ADC was enabled
* upon entry of the function, it is enabled upon function return.
*
* \param adc Pointer to ADC module.
* \param conf Pointer to ADC module configuration.
*/
void adc_write_configuration(ADC_t * adc,
const struct adc_config *conf)
{
uint16_t cal;
uint8_t enable;
irqflags_t flags;
#ifdef ADCA
if ((uintptr_t) adc == (uintptr_t) & ADCA) {
cal = adc_get_calibration_data(ADC_CAL_ADCA);
} else
#endif
#ifdef ADCB
if ((uintptr_t) adc == (uintptr_t) & ADCB) {
cal = adc_get_calibration_data(ADC_CAL_ADCB);
} else
#endif
{
Assert(0);
return;
}
flags = cpu_irq_save();
adc_enable_clock(adc);
enable = adc->CTRLA & ADC_ENABLE_bm;
adc->CTRLA = ADC_FLUSH_bm;
adc->CAL = cal;
adc->CMP = conf->cmp;
adc->REFCTRL = conf->refctrl;
adc->PRESCALER = conf->prescaler;
adc->EVCTRL = conf->evctrl;
adc->CTRLB = conf->ctrlb;
adc->CTRLA = enable | conf->ctrla;
adc_disable_clock(adc);
cpu_irq_restore(flags);
}
/**
* \brief Read configuration from ADC module
*
* Reads out the current configuration of the ADC module to the specified
* buffer.
*
* \param adc Pointer to ADC module.
* \param conf Pointer to ADC module configuration.
*/
void adc_read_configuration(ADC_t * adc,
struct adc_config *conf)
{
irqflags_t flags = cpu_irq_save();
adc_enable_clock(adc);
conf->ctrla = adc->CTRLA & ADC_DMASEL_gm;
conf->cmp = adc->CMP;
conf->refctrl = adc->REFCTRL;
conf->prescaler = adc->PRESCALER;
conf->evctrl = adc->EVCTRL;
conf->ctrlb = adc->CTRLB;
adc_disable_clock(adc);
cpu_irq_restore(flags);
}
/** @} */
/** @} */
/**
* \ingroup adc_channel_group
* @{
*/
/** \name ADC channel configuration */
/** @{ */
/**
* \brief Write configuration to ADC channel
*
* Writes the specified configuration to the ADC channel.
*
* \param adc Pointer to ADC module.
* \param ch_mask Mask of ADC channel(s):
* \arg \c ADC_CHn , where \c n specifies the channel. (Only a single channel
* can be given in mask)
* \param ch_conf Pointer to ADC channel configuration.
*
* \note The specified ADC's callback function must be set before this function
* is called if callbacks are enabled and interrupts are enabled in the
* channel configuration.
*/
void adcch_write_configuration(ADC_t * adc,
uint8_t ch_mask,
const struct adc_channel_config *ch_conf)
{
ADC_CH_t *adc_ch;
irqflags_t flags;
adc_ch = adc_get_channel(adc, ch_mask);
flags = cpu_irq_save();
#if defined(CONFIG_ADC_CALLBACK_ENABLE) && defined(_ASSERT_ENABLE_)
if ((adc_ch->INTCTRL & ADC_CH_INTLVL_gm) != ADC_CH_INTLVL_OFF_gc) {
# ifdef ADCA
if ((uintptr_t) adc == (uintptr_t) & ADCA) {
Assert(adca_callback);
} else
# endif
# ifdef ADCB
if ((uintptr_t) adc == (uintptr_t) & ADCB) {
Assert(adcb_callback);
} else
# endif
{
Assert(0);
return;
}
}
#endif
adc_enable_clock(adc);
adc_ch->CTRL = ch_conf->ctrl;
adc_ch->INTCTRL = ch_conf->intctrl;
adc_ch->MUXCTRL = ch_conf->muxctrl;
if (ch_mask & ADC_CH0) {
/* USB devices has channel scan available on ADC channel 0 */
adc_ch->SCAN = ch_conf->scan;
}
adc_disable_clock(adc);
cpu_irq_restore(flags);
}
/**
* \brief Read configuration from ADC channel
*
* Reads out the current configuration from the ADC channel to the specified
* buffer.
*
* \param adc Pointer to ADC module.
* \param ch_mask Mask of ADC channel(s):
* \arg \c ADC_CHn , where \c n specifies the channel. (Only a single channel
* can be given in mask)
* \param ch_conf Pointer to ADC channel configuration.
*/
void adcch_read_configuration(ADC_t * adc,
uint8_t ch_mask,
struct adc_channel_config *ch_conf)
{
ADC_CH_t *adc_ch;
irqflags_t flags;
adc_ch = adc_get_channel(adc, ch_mask);
flags = cpu_irq_save();
adc_enable_clock(adc);
ch_conf->ctrl = adc_ch->CTRL;
ch_conf->intctrl = adc_ch->INTCTRL;
ch_conf->muxctrl = adc_ch->MUXCTRL;
if (ch_mask & ADC_CH0) {
/* USB devices has channel scan available on ADC channel 0 */
ch_conf->scan = adc_ch->SCAN;
}
adc_disable_clock(adc);
cpu_irq_restore(flags);
}
/** @} */
/** @} */
ports/xplained/ASF/xmega/drivers/cpu/ccp.h
+120
View File
@@ -0,0 +1,120 @@
/**
* \file
*
* \brief Configuration Change Protection write functions
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef CPU_CCP_H
#define CPU_CCP_H
#include <compiler.h>
/**
* \defgroup ccp_group Configuration Change Protection
*
* See \ref xmega_ccp_quickstart.
*
* Function for writing to protected IO registers.
* @{
*/
#if defined(__DOXYGEN__)
//! \name IAR Memory Model defines.
//@{
/**
* \def CONFIG_MEMORY_MODEL_TINY
* \brief Configuration symbol to enable 8 bit pointers.
*
*/
# define CONFIG_MEMORY_MODEL_TINY
/**
* \def CONFIG_MEMORY_MODEL_SMALL
* \brief Configuration symbol to enable 16 bit pointers.
* \note If no memory model is defined, SMALL is default.
*
*/
# define CONFIG_MEMORY_MODEL_SMALL
/**
* \def CONFIG_MEMORY_MODEL_LARGE
* \brief Configuration symbol to enable 24 bit pointers.
*
*/
# define CONFIG_MEMORY_MODEL_LARGE
//@}
#endif
/**
* \brief Write to a CCP-protected 8-bit I/O register
*
* \param addr Address of the I/O register
* \param value Value to be written
*
* \note Using IAR Embedded workbench, the choice of memory model has an impact
* on calling convention. The memory model is not visible to the
* preprocessor, so it must be defined in the Assembler preprocessor directives.
*/
extern void ccp_write_io (void *addr, uint8_t value);
/** @} */
/**
* \page xmega_ccp_quickstart Quick start guide for CCP driver
*
* This is the quick start guide for the \ref ccp_group
* "Configuration Change Protection (CCP) driver", with step-by-step
* instructions on how to use the driver.
*
* The use case contains a code fragment, and this can be copied into, e.g.,
* the main application function.
*
* \section ccp_basic_use_case Basic use case
* In this use case, the CCP is used to write to the protected XMEGA Clock
* Control register.
*
* \subsection ccp_basic_use_case_setup_flow Workflow
* -# call CCP write io to change system clock selection:
* - \code ccp_write_io((uint8_t *)&CLK.CTRL, CLK_SCLKSEL_RC32M_gc); \endcode
*/
#endif /* CPU_CCP_H */
ports/xplained/ASF/xmega/drivers/cpu/ccp.s
+100
View File
@@ -0,0 +1,100 @@
/**
* \file
*
* \brief Configuration Change Protection
*
* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <assembler.h>
//! Value to write to CCP for access to protected IO registers.
#define CCP_IOREG 0xd8
/*
* GNU and IAR use different calling conventions. Since this is
* a very small and simple function to begin with, it's easier
* to implement it twice than to deal with the differences
* within a single implementation.
*
* Interrupts are disabled by hardware during the timed
* sequence, so there's no need to save/restore interrupt state.
*/
PUBLIC_FUNCTION(ccp_write_io)
#if defined(__GNUC__)
out RAMPZ, r1 // Reset bits 23:16 of Z
movw r30, r24 // Load addr into Z
ldi r18, CCP_IOREG // Load magic CCP value
out CCP, r18 // Start CCP handshake
st Z, r22 // Write value to I/O register
ret // Return to caller
#elif defined(__IAR_SYSTEMS_ASM__)
# if !defined(CONFIG_MEMORY_MODEL_TINY) && !defined(CONFIG_MEMORY_MODEL_SMALL) \
&& !defined(CONFIG_MEMORY_MODEL_LARGE)
# define CONFIG_MEMORY_MODEL_SMALL
# endif
ldi r20, 0
out RAMPZ, r20 // Reset bits 23:16 of Z
# if defined(CONFIG_MEMORY_MODEL_TINY)
mov r31, r20 // Reset bits 8:15 of Z
mov r30, r16 // Load addr into Z
# else
movw r30, r16 // Load addr into Z
# endif
ldi r21, CCP_IOREG // Load magic CCP value
out CCP, r21 // Start CCP handshake
# if defined(CONFIG_MEMORY_MODEL_TINY)
st Z, r17 // Write value to I/O register
# elif defined(CONFIG_MEMORY_MODEL_SMALL)
st Z, r18 // Write value to I/O register
# elif defined(CONFIG_MEMORY_MODEL_LARGE)
st Z, r19 // Write value to I/O register
# else
# error Unknown memory model in use, no idea how registers should be accessed
# endif
ret
#else
# error Unknown assembler
#endif
END_FUNC(ccp_write_io)
END_FILE()
ports/xplained/ASF/xmega/drivers/cpu/xmega_reset_cause.h
+109
View File
@@ -0,0 +1,109 @@
/**
* \file
*
* \brief Chip-specific reset cause functions
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef XMEGA_DRIVERS_CPU_RESET_CAUSE_H
#define XMEGA_DRIVERS_CPU_RESET_CAUSE_H
#include "compiler.h"
#include "ccp.h"
/**
* \ingroup reset_cause_group
* \defgroup xmega_reset_cause_group XMEGA reset cause
*
* See \ref reset_cause_quickstart
*
* @{
*/
/**
* \brief Chip-specific reset cause type capable of holding all chip reset
* causes. Typically reflects the size of the reset cause register.
*/
typedef uint8_t reset_cause_t;
//! \internal \name Chip-specific reset causes
//@{
//! \internal External reset cause
#define CHIP_RESET_CAUSE_EXTRST RST_EXTRF_bm
//! \internal brown-out detected reset cause, same as for CPU
#define CHIP_RESET_CAUSE_BOD_IO RST_BORF_bm
//! \internal Brown-out detected reset cause, same as for I/O
#define CHIP_RESET_CAUSE_BOD_CPU RST_BORF_bm
//! \internal On-chip debug system reset cause
#define CHIP_RESET_CAUSE_OCD RST_PDIRF_bm
//! \internal Power-on-reset reset cause
#define CHIP_RESET_CAUSE_POR RST_PORF_bm
//! \internal Software reset reset cause
#define CHIP_RESET_CAUSE_SOFT RST_SRF_bm
//! \internal Spike detected reset cause
#define CHIP_RESET_CAUSE_SPIKE RST_SDRF_bm
//! \internal Watchdog timeout reset cause
#define CHIP_RESET_CAUSE_WDT RST_WDRF_bm
//@}
static inline reset_cause_t
reset_cause_get_causes (void)
{
return (reset_cause_t) RST.STATUS;
}
static inline void
reset_cause_clear_causes (reset_cause_t causes)
{
RST.STATUS = causes;
}
static inline void
reset_do_soft_reset (void)
{
ccp_write_io ((void *) &RST.CTRL, RST_SWRST_bm);
while (1)
{
/* Intentionally empty. */
}
}
//! @}
#endif /* XMEGA_DRIVERS_CPU_RESET_CAUSE_H */
ports/xplained/ASF/xmega/drivers/nvm/nvm.c
+732
View File
@@ -0,0 +1,732 @@
/**
* \file
*
* \brief Non Volatile Memory controller driver
*
* Copyright (C) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "compiler.h"
#include "ccp.h"
#include "nvm.h"
#include <string.h>
/**
* \weakgroup nvm_signature_group
* @{
*/
/**
* \brief Read the device serial
*
* This function returns the device serial stored in the device.
*
* \note This function is modifying the NVM.CMD register.
* If the application are using program space access in interrupts
* (__flash pointers in IAR EW or pgm_read_byte in GCC) interrupts
* needs to be disabled when running EEPROM access functions. If not
* the program space reads will be corrupted.
*
* \retval storage Pointer to the structure where to store the device serial
*/
void nvm_read_device_serial(struct nvm_device_serial *storage)
{
storage->lotnum0 =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(LOTNUM0));
storage->lotnum1 =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(LOTNUM1));
storage->lotnum2 =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(LOTNUM2));
storage->lotnum3 =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(LOTNUM3));
storage->lotnum4 =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(LOTNUM4));
storage->lotnum5 =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(LOTNUM5));
storage->wafnum =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(WAFNUM));
storage->coordx0 =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(COORDX0));
storage->coordx1 =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(COORDX1));
storage->coordy0 =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(COORDY0));
storage->coordy1 =
nvm_read_production_signature_row
(nvm_get_production_signature_row_offset(COORDY1));
}
//! @}
/**
* \weakgroup nvm_eeprom_group
* @{
*/
/**
* \brief Read one byte from EEPROM using mapped access.
*
* This function reads one byte from EEPROM using mapped access.
*
* \param addr EEPROM address, between 0 and EEPROM_SIZE
*
* \return Byte value read from EEPROM.
*/
uint8_t nvm_eeprom_read_byte(eeprom_addr_t addr)
{
uint8_t data;
Assert(addr <= EEPROM_SIZE);
/* Wait until NVM is ready */
nvm_wait_until_ready();
eeprom_enable_mapping();
data = *(uint8_t *) (addr + MAPPED_EEPROM_START), eeprom_disable_mapping();
return data;
}
/**
* \brief Read buffer within the eeprom
*
* \param address the address to where to read
* \param buf pointer to the data
* \param len the number of bytes to read
*/
void nvm_eeprom_read_buffer(eeprom_addr_t address,
void *buf,
uint16_t len)
{
nvm_wait_until_ready();
eeprom_enable_mapping();
memcpy(buf, (void *) (address + MAPPED_EEPROM_START), len);
eeprom_disable_mapping();
}
/**
* \brief Write one byte to EEPROM using IO mapping.
*
* This function writes one byte to EEPROM using IO-mapped access.
* This function will cancel all ongoing EEPROM page buffer loading
* operations, if any.
*
* \param address EEPROM address (max EEPROM_SIZE)
* \param value Byte value to write to EEPROM.
*/
void nvm_eeprom_write_byte(eeprom_addr_t address,
uint8_t value)
{
uint8_t old_cmd;
Assert(address <= EEPROM_SIZE);
/* Flush buffer to make sure no unintentional data is written and load
* the "Page Load" command into the command register.
*/
old_cmd = NVM.CMD;
nvm_eeprom_flush_buffer();
// Wait until NVM is ready
nvm_wait_until_ready();
nvm_eeprom_load_byte_to_buffer(address, value);
// Set address to write to
NVM.ADDR2 = 0x00;
NVM.ADDR1 = (address >> 8) & 0xFF;
NVM.ADDR0 = address & 0xFF;
/* Issue EEPROM Atomic Write (Erase&Write) command. Load command, write
* the protection signature and execute command.
*/
NVM.CMD = NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc;
nvm_exec();
NVM.CMD = old_cmd;
}
/**
* \brief Write buffer within the eeprom
*
* \param address the address to where to write
* \param buf pointer to the data
* \param len the number of bytes to write
*/
void nvm_eeprom_erase_and_write_buffer(eeprom_addr_t address,
const void *buf,
uint16_t len)
{
while (len) {
if (((address % EEPROM_PAGE_SIZE) == 0) && (len >= EEPROM_PAGE_SIZE)) {
// A full page can be written
nvm_eeprom_load_page_to_buffer((uint8_t *) buf);
nvm_eeprom_atomic_write_page(address / EEPROM_PAGE_SIZE);
address += EEPROM_PAGE_SIZE;
buf = (uint8_t *) buf + EEPROM_PAGE_SIZE;
len -= EEPROM_PAGE_SIZE;
} else {
nvm_eeprom_write_byte(address++, *(uint8_t *) buf);
buf = (uint8_t *) buf + 1;
len--;
}
}
}
/**
* \brief Flush temporary EEPROM page buffer.
*
* This function flushes the EEPROM page buffers. This function will cancel
* any ongoing EEPROM page buffer loading operations, if any.
* This function also works for memory mapped EEPROM access.
*
* \note An EEPROM write operations will automatically flush the buffer for you.
* \note The function does not preserve the value of the NVM.CMD register
*/
void nvm_eeprom_flush_buffer(void)
{
// Wait until NVM is ready
nvm_wait_until_ready();
// Flush EEPROM page buffer if necessary
if ((NVM.STATUS & NVM_EELOAD_bm) != 0) {
NVM.CMD = NVM_CMD_ERASE_EEPROM_BUFFER_gc;
nvm_exec();
}
}
/**
* \brief Load single byte into temporary page buffer.
*
* This function loads one byte into the temporary EEPROM page buffers.
* If memory mapped EEPROM is enabled, this function will not work.
* Make sure that the buffer is flushed before starting to load bytes.
* Also, if multiple bytes are loaded into the same location, they will
* be ANDed together, thus 0x55 and 0xAA will result in 0x00 in the buffer.
*
* \note Only one page buffer exist, thus only one page can be loaded with
* data and programmed into one page. If data needs to be written to
* different pages, the loading and writing needs to be repeated.
*
* \param byte_addr EEPROM Byte address, between 0 and EEPROM_PAGE_SIZE.
* \param value Byte value to write to buffer.
*/
void nvm_eeprom_load_byte_to_buffer(uint8_t byte_addr,
uint8_t value)
{
// Wait until NVM is ready
nvm_wait_until_ready();
eeprom_enable_mapping();
*(uint8_t *) (byte_addr + MAPPED_EEPROM_START) = value;
eeprom_disable_mapping();
}
/**
* \brief Load entire page into temporary EEPROM page buffer.
*
* This function loads an entire EEPROM page from an SRAM buffer to
* the EEPROM page buffers. If memory mapped EEPROM is enabled, this
* function will not work. Make sure that the buffer is flushed before
* starting to load bytes.
*
* \note Only the lower part of the address is used to address the buffer.
* Therefore, no address parameter is needed. In the end, the data
* is written to the EEPROM page given by the address parameter to the
* EEPROM write page operation.
*
* \param values Pointer to SRAM buffer containing an entire page.
*/
void nvm_eeprom_load_page_to_buffer(const uint8_t * values)
{
// Wait until NVM is ready
nvm_wait_until_ready();
// Load multiple bytes into page buffer
uint8_t i;
for (i = 0; i < EEPROM_PAGE_SIZE; ++i) {
nvm_eeprom_load_byte_to_buffer(i, *values);
++values;
}
}
/**
* \brief Erase and write bytes from page buffer into EEPROM.
*
* This function writes the contents of an already loaded EEPROM page
* buffer into EEPROM memory.
*
* As this is an atomic write, the page in EEPROM will be erased
* automatically before writing. Note that only the page buffer locations
* that have been loaded will be used when writing to EEPROM. Page buffer
* locations that have not been loaded will be left untouched in EEPROM.
*
* \param page_addr EEPROM Page address, between 0 and EEPROM_SIZE/EEPROM_PAGE_SIZE
*/
void nvm_eeprom_atomic_write_page(uint8_t page_addr)
{
// Wait until NVM is ready
nvm_wait_until_ready();
// Calculate page address
uint16_t address = (uint16_t) (page_addr * EEPROM_PAGE_SIZE);
Assert(address <= EEPROM_SIZE);
// Set address
NVM.ADDR2 = 0x00;
NVM.ADDR1 = (address >> 8) & 0xFF;
NVM.ADDR0 = address & 0xFF;
// Issue EEPROM Atomic Write (Erase&Write) command
nvm_issue_command(NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc);
}
/**
* \brief Write (without erasing) EEPROM page.
*
* This function writes the contents of an already loaded EEPROM page
* buffer into EEPROM memory.
*
* As this is a split write, the page in EEPROM will _not_ be erased
* before writing.
*
* \param page_addr EEPROM Page address, between 0 and EEPROM_SIZE/EEPROM_PAGE_SIZE
*/
void nvm_eeprom_split_write_page(uint8_t page_addr)
{
// Wait until NVM is ready
nvm_wait_until_ready();
// Calculate page address
uint16_t address = (uint16_t) (page_addr * EEPROM_PAGE_SIZE);
Assert(address <= EEPROM_SIZE);
// Set address
NVM.ADDR2 = 0x00;
NVM.ADDR1 = (address >> 8) & 0xFF;
NVM.ADDR0 = address & 0xFF;
// Issue EEPROM Split Write command
nvm_issue_command(NVM_CMD_WRITE_EEPROM_PAGE_gc);
}
/**
* \brief Fill temporary EEPROM page buffer with value.
*
* This fills the the EEPROM page buffers with a given value.
* If memory mapped EEPROM is enabled, this function will not work.
*
* \note Only the lower part of the address is used to address the buffer.
* Therefore, no address parameter is needed. In the end, the data
* is written to the EEPROM page given by the address parameter to the
* EEPROM write page operation.
*
* \param value Value to copy to the page buffer.
*/
void nvm_eeprom_fill_buffer_with_value(uint8_t value)
{
nvm_eeprom_flush_buffer();
// Wait until NVM is ready
nvm_wait_until_ready();
// Load multiple bytes into page buffer
uint8_t i;
for (i = 0; i < EEPROM_PAGE_SIZE; ++i) {
nvm_eeprom_load_byte_to_buffer(i, value);
}
}
/**
* \brief Erase bytes from EEPROM page.
*
* This function erases bytes from one EEPROM page, so that every location
* written to in the page buffer reads 0xFF.
*
* \param page_addr EEPROM Page address, between 0 and EEPROM_SIZE/EEPROM_PAGE_SIZE
*/
void nvm_eeprom_erase_bytes_in_page(uint8_t page_addr)
{
// Wait until NVM is ready
nvm_wait_until_ready();
// Calculate page address
uint16_t address = (uint16_t) (page_addr * EEPROM_PAGE_SIZE);
Assert(address <= EEPROM_SIZE);
// Set address
NVM.ADDR2 = 0x00;
NVM.ADDR1 = (address >> 8) & 0xFF;
NVM.ADDR0 = address & 0xFF;
// Issue EEPROM Erase command
nvm_issue_command(NVM_CMD_ERASE_EEPROM_PAGE_gc);
}
/**
* \brief Erase EEPROM page.
*
* This function erases one EEPROM page, so that every location reads 0xFF.
*
* \param page_addr EEPROM Page address, between 0 and EEPROM_SIZE/EEPROM_PAGE_SIZE
*/
void nvm_eeprom_erase_page(uint8_t page_addr)
{
// Mark all addresses to be deleted
nvm_eeprom_fill_buffer_with_value(0xff);
// Erase bytes
nvm_eeprom_erase_bytes_in_page(page_addr);
}
/**
* \brief Erase bytes from all EEPROM pages.
*
* This function erases bytes from all EEPROM pages, so that every location
* written to in the page buffer reads 0xFF.
*/
void nvm_eeprom_erase_bytes_in_all_pages(void)
{
// Wait until NVM is ready
nvm_wait_until_ready();
// Issue EEPROM Erase All command
nvm_issue_command(NVM_CMD_ERASE_EEPROM_gc);
}
/**
* \brief Erase entire EEPROM memory.
*
* This function erases the entire EEPROM memory block to 0xFF.
*/
void nvm_eeprom_erase_all(void)
{
// Mark all addresses to be deleted
nvm_eeprom_fill_buffer_with_value(0xff);
// Erase all pages
nvm_eeprom_erase_bytes_in_all_pages();
}
//! @}
//! @}
/**
* \weakgroup nvm_flash_group
* @{
*/
/**
* \brief Issue flash range CRC command
*
* This function sets the FLASH range CRC command in the NVM.CMD register.
* It then loads the start and end byte address of the part of FLASH to
* generate a CRC-32 for into the ADDR and DATA registers and finally performs
* the execute command.
*
* \note Should only be called from the CRC module. The function saves and
* restores the NVM.CMD register, but if this
* function is called from an interrupt, interrupts must be disabled
* before this function is called.
*
* \param start_addr end byte address
* \param end_addr start byte address
*/
void nvm_issue_flash_range_crc(flash_addr_t start_addr,
flash_addr_t end_addr)
{
uint8_t old_cmd;
// Save current nvm command
old_cmd = NVM.CMD;
// Load the NVM CMD register with the Flash Range CRC command
NVM.CMD = NVM_CMD_FLASH_RANGE_CRC_gc;
// Load the start byte address in the NVM Address Register
NVM.ADDR0 = start_addr & 0xFF;
NVM.ADDR1 = (start_addr >> 8) & 0xFF;
#if (FLASH_SIZE >= 0x10000UL)
NVM.ADDR2 = (start_addr >> 16) & 0xFF;
#endif
// Load the end byte address in NVM Data Register
NVM.DATA0 = end_addr & 0xFF;
NVM.DATA1 = (end_addr >> 8) & 0xFF;
#if (FLASH_SIZE >= 0x10000UL)
NVM.DATA2 = (end_addr >> 16) & 0xFF;
#endif
// Execute command
ccp_write_io((uint8_t *) & NVM.CTRLA, NVM_CMDEX_bm);
// Restore command register
NVM.CMD = old_cmd;
}
/**
* \brief Read buffer within the application section
*
* \param address the address to where to read
* \param buf pointer to the data
* \param len the number of bytes to read
*/
void nvm_flash_read_buffer(flash_addr_t address,
void *buf,
uint16_t len)
{
#if (FLASH_SIZE>0x10000)
uint32_t opt_address = address;
#else
uint16_t opt_address = (uint16_t) address;
#endif
nvm_wait_until_ready();
while (len) {
*(uint8_t *) buf = nvm_flash_read_byte(opt_address);
buf = (uint8_t *) buf + 1;
opt_address++;
len--;
}
}
/**
* \brief Read buffer within the user section
*
* \param address the address to where to read
* \param buf pointer to the data
* \param len the number of bytes to read
*/
void nvm_user_sig_read_buffer(flash_addr_t address,
void *buf,
uint16_t len)
{
uint16_t opt_address = (uint16_t) address & (FLASH_PAGE_SIZE - 1);
while (len) {
*(uint8_t *) buf = nvm_read_user_signature_row(opt_address);
buf = (uint8_t *) buf + 1;
opt_address++;
len--;
}
}
/**
* \brief Write specific parts of user flash section
*
* \param address the address to where to write
* \param buf pointer to the data
* \param len the number of bytes to write
* \param b_blank_check if True then the page flash is checked before write
* to run or not the erase page command.
*
* Set b_blank_check to false if all application flash is erased before.
*/
void nvm_user_sig_write_buffer(flash_addr_t address,
const void *buf,
uint16_t len,
bool b_blank_check)
{
uint16_t w_value;
uint16_t page_pos;
uint16_t opt_address = (uint16_t) address;
bool b_flag_erase = false;
while (len) {
for (page_pos = 0; page_pos < FLASH_PAGE_SIZE; page_pos += 2) {
if (b_blank_check) {
// Read flash to know if the erase command is mandatory
LSB(w_value) = nvm_read_user_signature_row(page_pos);
MSB(w_value) = nvm_read_user_signature_row(page_pos + 1);
if (w_value != 0xFFFF) {
b_flag_erase = true; // The page is not empty
}
} else {
w_value = 0xFFFF;
}
// Update flash buffer
if (len) {
if (opt_address == page_pos) {
// The MSB of flash word must be changed
// because the address is even
len--;
opt_address++;
LSB(w_value) = *(uint8_t *) buf;
buf = (uint8_t *) buf + 1;
}
}
if (len) {
if (opt_address == (page_pos + 1)) {
// The LSB of flash word must be changed
// because the user buffer is not empty
len--;
opt_address++;
MSB(w_value) = *(uint8_t *) buf;
buf = (uint8_t *) buf + 1;
}
}
// Load flash buffer
nvm_flash_load_word_to_buffer(page_pos, w_value);
}
}
// Write flash buffer
if (b_flag_erase) {
nvm_flash_erase_user_section();
}
nvm_flash_write_user_page();
}
/**
* \brief Erase and write specific parts of application flash section
*
* \param address the address to where to write
* \param buf pointer to the data
* \param len the number of bytes to write
* \param b_blank_check if True then the page flash is checked before write
* to run or not the erase page command.
*
* Set b_blank_check to false if all application flash is erased before.
*/
void nvm_flash_erase_and_write_buffer(flash_addr_t address,
const void *buf,
uint16_t len,
bool b_blank_check)
{
uint16_t w_value;
uint16_t page_pos;
bool b_flag_erase;
#if (FLASH_SIZE>0x10000)
uint32_t page_address;
uint32_t opt_address = address;
#else
uint16_t page_address;
uint16_t opt_address = (uint16_t) address;
#endif
// Compute the start of the page to be modified
page_address = opt_address - (opt_address % FLASH_PAGE_SIZE);
// For each page
while (len) {
b_flag_erase = false;
nvm_wait_until_ready();
for (page_pos = 0; page_pos < FLASH_PAGE_SIZE; page_pos += 2) {
if (b_blank_check) {
// Read flash to know if the erase command is mandatory
w_value = nvm_flash_read_word(page_address);
if (w_value != 0xFFFF) {
b_flag_erase = true; // The page is not empty
}
} else {
w_value = 0xFFFF;
}
// Update flash buffer
if (len) {
if (opt_address == page_address) {
// The MSB of flash word must be changed
// because the address is even
len--;
opt_address++;
LSB(w_value) = *(uint8_t *) buf;
buf = (uint8_t *) buf + 1;
}
}
if (len) {
if (opt_address == (page_address + 1)) {
// The LSB of flash word must be changed
// because the user buffer is not empty
len--;
opt_address++;
MSB(w_value) = *(uint8_t *) buf;
buf = (uint8_t *) buf + 1;
}
}
// Load flash buffer
nvm_flash_load_word_to_buffer(page_address, w_value);
page_address += 2;
}
// Write flash buffer
if (b_flag_erase) {
nvm_flash_atomic_write_app_page(page_address - FLASH_PAGE_SIZE);
} else {
nvm_flash_split_write_app_page(page_address - FLASH_PAGE_SIZE);
}
}
}
//! @}
/**
* \weakgroup nvm_fuse_lock_group
* @{
*/
/**
* \brief Read a fuse byte.
*
* This function reads and returns the value of a given fuse byte.
*
* \param fuse Fuse byte to read.
*
* \return Byte value of fuse.
*/
uint8_t nvm_fuses_read(enum fuse_byte_t fuse)
{
// Wait until NVM is ready
nvm_wait_until_ready();
// Set address
NVM.ADDR0 = fuse;
// Issue READ_FUSES command
nvm_issue_command(NVM_CMD_READ_FUSES_gc);
return NVM.DATA0;
}
//! @}
ports/xplained/ASF/xmega/drivers/nvm/nvm.h
+1093
View File
File diff suppressed because it is too large Load Diff
ports/xplained/ASF/xmega/drivers/nvm/nvm_asm.s
+197
View File
@@ -0,0 +1,197 @@
/**
* \file
*
* \brief Non Volatile Memory controller driver
*
* Copyright (c) 2010 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <assembler.h>
#if defined(__GNUC__)
//! Value to write to CCP for access to protected IO registers.
# define CCP_SPM_gc 0x9D
//! NVM busy flag
# define NVM_NVMBUSY_bp 7
//! NVM command for loading flash buffer
# define NVM_CMD_LOAD_FLASH_BUFFER_gc 0x23
#elif defined(__IAR_SYSTEMS_ASM__)
// All values are defined for IAR
#else
# error Unknown assembler
#endif
#ifndef __DOXYGEN__
PUBLIC_FUNCTION(nvm_read_byte)
#if defined(__GNUC__)
lds r20, NVM_CMD ; Store NVM command register
mov ZL, r22 ; Load byte index into low byte of Z.
mov ZH, r23 ; Load high byte into Z.
sts NVM_CMD, r24 ; Load prepared command into NVM Command register.
lpm r24, Z ; Perform an LPM to read out byte
sts NVM_CMD, r20 ; Restore NVM command register
#elif defined(__IAR_SYSTEMS_ASM__)
lds r20, NVM_CMD ; Store NVM command register
mov ZL, r18 ; Load byte index into low byte of Z.
mov ZH, r19 ; Load high byte into Z.
sts NVM_CMD, r16 ; Load prepared command into NVM Command register.
lpm r16, Z ; Perform an LPM to read out byte
sts NVM_CMD, r20 ; Restore NVM command register
#endif
ret
END_FUNC(nvm_read_byte)
// IAR forgets about include files after each module, so need to include again
#if defined(__IAR_SYSTEMS_ASM__)
# include <ioavr.h>
#endif
/**
* \brief Perform SPM command
*/
PUBLIC_FUNCTION_SEGMENT(nvm_common_spm, BOOT)
#if defined(__GNUC__)
/**
* For GCC:
* \param address uint32_t r22:r25
* \param nvm_cmd uint8_t r20
*/
in r25, RAMPZ ; Store RAMPZ. Highest address byte is ignored, so using that
out RAMPZ, r24 ; Load R24 into RAMPZ
movw ZL, r22 ; Load R22:R23 into Z.
lds r24, NVM_CMD ; Store NVM command register (r24 is no longer needed)
sts NVM_CMD, r20 ; Load prepared command into NVM Command register.
ldi r23, CCP_SPM_gc ; Prepare Protect SPM signature (r23 is no longer needed)
sts CCP, r23 ; Enable SPM operation (this disables interrupts for 4 cycles).
spm ; Self-program.
sts NVM_CMD, r24 ; Restore NVM command register
out RAMPZ, r25 ; Restore RAMPZ register.
#elif defined(__IAR_SYSTEMS_ASM__)
/**
* For IAR:
* \param address uint32_t r16:r19
* \param nvm_cmd uint8_t r20
*/
in r19, RAMPZ ; Store RAMPZ. Highest address byte is ignored, so using that
out RAMPZ, r18 ; Load R18 into RAMPZ
movw ZL, r16 ; Load R16:R17 into Z.
lds r18, NVM_CMD ; Store NVM command register (r18 is no longer needed)
sts NVM_CMD, r20 ; Load prepared command into NVM Command register.
ldi r19, CCP_SPM_gc ; Prepare Protect SPM signature (r19 is no longer needed)
sts CCP, r19 ; Enable SPM operation (this disables interrupts for 4 cycles).
spm ; Self-program.
sts NVM_CMD, r18 ; Restore NVM command register
out RAMPZ, r19 ; Restore RAMPZ register.
#endif
ret
END_FUNC(nvm_common_spm)
// IAR forgets about include files after each module, so need to include again
#if defined(__IAR_SYSTEMS_ASM__)
# include <ioavr.h>
#endif
/**
* \brief Load byte to page buffer
*
*/
PUBLIC_FUNCTION_SEGMENT(nvm_flash_load_word_to_buffer, BOOT)
#if defined(__GNUC__)
/**
* For GCC:
* \param word_addr uint32_t r22:r25
* \param data uint16_t r20:r21
*/
wait_nvm:
lds r18, NVM_STATUS
sbrc r18, NVM_NVMBUSY_bp
rjmp wait_nvm
in r25, RAMPZ ; Store RAMPZ. Highest address byte is ignored, so using that
out RAMPZ, r24 ; Load R24 into RAMPZ
movw ZL, r22 ; Load R22:R23 into Z.
lds r24, NVM_CMD ; Store NVM command register (r24 is no longer needed)
ldi r18, NVM_CMD_LOAD_FLASH_BUFFER_gc
sts NVM_CMD, r18 ; Load prepared command into NVM Command register.
movw r0, r20 ; Load R20:R21 into R0:R1
spm ; Self-program.
clr r1 ; Clear R1 for GCC _zero_reg_ to function properly.
sts NVM_CMD, r24 ; Restore NVM command register
out RAMPZ, r25 ; Restore RAMPZ register.
#elif defined(__IAR_SYSTEMS_ASM__)
/**
* For IAR:
* \param word_addr uint32_t r16:r19
* \param data uint16_t r20:r21
*/
wait_nvm:
lds r19, NVM_STATUS
sbrc r19, NVM_NVMBUSY_bp
rjmp wait_nvm
in r19, RAMPZ ; Store RAMPZ. Highest byte is ignored, so using that
out RAMPZ, r18 ; Load R18 into RAMPZ
movw ZL, r16 ; Load R16:R17 into Z.
lds r18, NVM_CMD ; Store NVM command register (r18 is no longer needed)
ldi r17, NVM_CMD_LOAD_FLASH_BUFFER_gc
sts NVM_CMD, r17 ; Load prepared command into NVM Command register.
movw r0, r20 ; Load R20:R21 into R0:R1
spm ; Self-program.
sts NVM_CMD, r18 ; Restore NVM command register
out RAMPZ, r19 ; Restore RAMPZ register.
#endif
ret
END_FUNC(nvm_flash_load_word_to_buffer)
END_FILE()
#endif // __DOXYGEN__
ports/xplained/ASF/xmega/drivers/pmic/pmic.h
+361
View File
@@ -0,0 +1,361 @@
/**
* \file
*
* \brief Programmable Multilevel Interrupt Controller driver
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef PMIC_H
#define PMIC_H
#include <compiler.h>
#include <ccp.h>
/**
* \defgroup pmic_group Programmable Multilevel Interrupt Controller
*
* See \ref xmega_pmic_quickstart.
*
* This is a low-level driver implementation for the AVR XMEGA Programmable
* Multilevel Interrupt Controller.
*
* \note If these functions are used in interrupt service routines (ISRs), any
* non-ISR code or ISR code for lower level interrupts must ensure that the
* operations are atomic, i.e., by disabling interrupts during the function
* calls.
* @{
*/
/**
* \brief Interrupt level bitmasks
*
* \note These may be OR'ed, e.g., if multiple levels are to be enabled or
* disabled.
*/
enum pmic_level
{
PMIC_LVL_LOW = PMIC_LOLVLEN_bm, //!< Low-level interrupts
PMIC_LVL_MEDIUM = PMIC_MEDLVLEN_bm, //!< Medium-level interrupts
PMIC_LVL_HIGH = PMIC_HILVLEN_bm, //!< High-level interrupts
/**
* \brief Non-maskable interrupts
* \note These cannot be enabled nor disabled.
*/
PMIC_LVL_NMI = PMIC_NMIEX_bp,
};
//! Interrupt vector locations
enum pmic_vector
{
PMIC_VEC_APPLICATION, //!< Application section
PMIC_VEC_BOOT, //!< Boot section
PMIC_NR_OF_VECTORS, //!< Number of interrupt vector locations
};
//! Interrupt scheduling schemes
enum pmic_schedule
{
PMIC_SCH_FIXED_PRIORITY, //!< Default, fixed priority scheduling
PMIC_SCH_ROUND_ROBIN, //!< Round-robin scheduling
PMIC_NR_OF_SCHEDULES, //!< Number of interrupt scheduling schemes
};
/**
* \brief Initialize the PMIC
*
* Enables all interrupt levels, with vectors located in the application section
* and fixed priority scheduling.
*/
static inline void
pmic_init (void)
{
PMIC.CTRL = PMIC_LVL_LOW | PMIC_LVL_MEDIUM | PMIC_LVL_HIGH;
}
/**
* \brief Enable interrupts with specified \a level(s).
*
* \param level Interrupt level(s) to enable.
*/
static inline void
pmic_enable_level (enum pmic_level level)
{
Assert ((level & PMIC_LVL_NMI));
PMIC.CTRL |= level;
}
/**
* \brief Disable interrupts with specified \a level(s).
*
* \param level Interrupt level(s) to disable.
*/
static inline void
pmic_disable_level (enum pmic_level level)
{
Assert ((level & PMIC_LVL_NMI));
PMIC.CTRL &= ~level;
}
/**
* \brief Check if specified interrupt \a level(s) is enabled.
*
* \param level Interrupt level(s) to check.
*
* \return True if interrupt level(s) is enabled.
*/
static inline bool
pmic_level_is_enabled (enum pmic_level level)
{
Assert ((level & PMIC_LVL_NMI));
return PMIC.CTRL & level;
}
/**
* \brief Get currently enabled level(s)
*
* \return Bitmask with currently enabled levels.
*/
static inline enum pmic_level
pmic_get_enabled_levels (void)
{
return (enum pmic_level) (PMIC.CTRL & (PMIC_LVL_LOW | PMIC_LVL_MEDIUM
| PMIC_LVL_HIGH));
}
/**
* \brief Check if an interrupt level(s) is currently executing.
*
* \param level Interrupt level(s) to check.
*
* \return True if interrupt level(s) is currently executing.
*/
static inline bool
pmic_level_is_executing (enum pmic_level level)
{
return PMIC.STATUS & level;
}
/**
* \brief Set interrupt scheduling for low-level interrupts.
*
* \param schedule Interrupt scheduling method to set.
*
* \note The low-priority vector, INTPRI, must be set to 0 when round-robin
* scheduling is disabled to return to default interrupt priority order.
*/
static inline void
pmic_set_scheduling (enum pmic_schedule schedule)
{
Assert (schedule < PMIC_NR_OF_SCHEDULES);
switch (schedule)
{
case PMIC_SCH_FIXED_PRIORITY:
PMIC.CTRL &= ~PMIC_RREN_bm;
PMIC.INTPRI = 0;
break;
case PMIC_SCH_ROUND_ROBIN:
PMIC.CTRL |= PMIC_RREN_bm;
break;
default:
break;
};
}
/**
* \brief Set location of interrupt vectors.
*
* \param vector Location to use for interrupt vectors.
*/
static inline void
pmic_set_vector_location (enum pmic_vector vector)
{
uint8_t ctrl = PMIC.CTRL;
Assert (vector < PMIC_NR_OF_VECTORS);
switch (vector)
{
case PMIC_VEC_APPLICATION:
ctrl &= ~PMIC_IVSEL_bm;
break;
case PMIC_VEC_BOOT:
ctrl |= PMIC_IVSEL_bm;
break;
default:
break;
}
ccp_write_io ((uint8_t *) & PMIC.CTRL, ctrl);
}
//! @}
/**
* \page xmega_pmic_quickstart Quick start guide for PMIC driver
*
* This is the quick start guide for the \ref pmic_group "PMIC driver" and
* the closely related \ref interrupt_group "global interrupt driver", with
* step-by-step instructions on how to configure and use the drivers in a
* selection of use cases.
*
* The use cases contain several code fragments. The code fragments in the
* steps for setup can be copied into a custom initialization function, while
* the steps for usage can be copied into, e.g., the main application function.
*
* \section pmic_basic_use_case Basic use case
* In this basic use case, the PMIC is configured for:
* - all interrupt levels enabled
* - round-robin scheduling
*
* This will allow for interrupts from other modules being used.
*
* \section pmic_basic_use_case_setup Setup steps
*
* \subsection pmic_basic_use_case_setup_prereq Prerequisites
* For the setup code of this use case to work, the following must
* be added to the project:
* -# Interrupts for the module requiring the PMIC module have to be
* enabled.
* -# An Interrupt Service Routine (ISR) for a given interrupt vector has to be
* defined, where the interrupt vectors available are defined by toolchain and
* listed in the subsection 'Interrupt Vector Summary' in the data sheet.
* \code
* ISR(interrupt_vector){
* //Interrupt Service Routine
* }
* \endcode
*
* \subsection pmic_basic_use_case_setup_code Example code
* Add to the initialization code:
* \code
* pmic_init();
* pmic_set_scheduling(PMIC_SCH_ROUND_ROBIN);
* cpu_irq_enable();
* \endcode
*
* \subsection pmic_basic_use_case_setup_flow Workflow
* -# call the PMIC driver's own init function to enable all interrupt levels:
* - \code pmic_init(); \endcode
* -# enable round-robin instead of fixed priority interrupt scheduling:
* - \code pmic_set_scheduling(PMIC_SCH_ROUND_ROBIN); \endcode
* -# enable interrupts globally:
* - \code cpu_irq_enable(); \endcode
* - \attention Interrupts will not trigger without this step.
*
* \section pmic_use_cases Advanced use cases
* For more advanced use of the PMIC driver, see the following use cases:
* - \subpage pmic_use_case_1 : atomic operations
*/
/**
* \page pmic_use_case_1 Use case #1
*
* In this use case, the PMIC is configured for:
* - all interrupt levels enabled
*
* This will allow for interrupts from other modules being used.
*
* This use case shows how to make an operation which consists of multiple
* instructions uninterruptible, i.e., into an atomic operation. This is often
* necessary if there is a risk that data can be accessed by interrupt handlers
* while other code is accessing it, and at least one of them modifies it.
*
* \section pmic_use_case_1_setup Setup steps
*
* \subsection pmic_basic_use_case_setup_prereq Prerequisites
* For the setup code of this use case to work, the following must
* be added to the project:
* -# Interrupts for the module requiring the PMIC module have to be
* enabled.
* -# An Interrupt Service Routine (ISR) for a given interrupt vector has to be
* defined, where the interrupt vectors available are defined by toolchain and
* listed in the subsection 'Interrupt Vector Summary' in the data sheet.
* \code
* ISR(interrupt_vector){
* //Interrupt Service Routine
* }
* \endcode
*
* \subsection pmic_use_case_1_setup_code Example code
* Add to application initialization:
* \code
* pmic_init();
* cpu_irq_enable();
* \endcode
*
* \subsection pmic_use_case_1_setup_flow Workflow
* -# call the PMIC driver's own init function to enable all interrupt levels:
* - \code pmic_init(); \endcode
* -# set global interrupt enable flag:
* - \code cpu_irq_enable(); \endcode
*
* \section pmic_use_case_1_usage Usage steps
*
* \subsection pmic_use_case_1_usage_code Example code
* \code
* Add to application:
* void atomic_operation(void)
* {
* irqflags_t flags;
*
* flags = cpu_irq_save();
*
* // Uninterruptible block of code
*
* cpu_irq_restore(flags);
* }
* \endcode
*
* \subsection pmic_use_case_1_usage_flow Workflow
* -# allocate temporary storage for interrupt enable:
* - \code irqflags_t flags; \endcode
* -# clear global interrupt enable flag while saving its previous state:
* - \code flags = cpu_irq_save(); \endcode
* -# restore the previous state of global interrupt flag after operation:
* - \code cpu_irq_restore(flags); \endcode
*/
#endif /* PMIC_H */
ports/xplained/ASF/xmega/drivers/rtc32/rtc32.c
+327
View File
@@ -0,0 +1,327 @@
/**
* \file
*
* \brief AVR XMEGA 32-bit Real Time Counter driver
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <compiler.h>
#include <parts.h>
#include <sysclk.h>
#include <delay.h>
#include "rtc32.h"
#ifdef __ICCAVR__
# define _DWORDREGISTER DWORDREGISTER
#endif
/**
* \internal
* Workaround for missing CNT, PER and COMP in WinAVR header files
* \todo Remove when header files are fixed if WinAVR release
*/
typedef struct RTC32_struct2 {
register8_t CTRL;
register8_t SYNCCTRL;
register8_t INTCTRL;
register8_t INTFLAGS;
_DWORDREGISTER(CNT);
_DWORDREGISTER(PER);
_DWORDREGISTER(COMP);
} RTC32_t2;
#undef RTC32
/**
* \internal
* Workaround for missing CNT, PER and COMP in WinAVR header files
* \todo Remove when header files are fixed if WinAVR release
*/
#define RTC32 (*(RTC32_t2 *)0x0420)
#ifdef CONFIG_RTC32_COMPARE_INT_LEVEL
# define RTC32_COMPARE_INT_LEVEL CONFIG_RTC32_COMPARE_INT_LEVEL
#else
# define RTC32_COMPARE_INT_LEVEL RTC32_COMPINTLVL_LO_gc
#endif
#ifdef CONFIG_RTC32_CLOCK_1024HZ
# define RTC32_CLOCK VBAT_XOSCSEL_bm
#else
# define RTC32_CLOCK 0
#endif
/**
* \internal
* \brief Driver private struct
*/
struct rtc_data_struct {
//! Callback function to use on alarm
rtc_callback_t callback;
};
/**
* \internal
* \brief Driver private data
*/
struct rtc_data_struct rtc_data;
/**
* \internal
* \brief Check if RTC32 is busy synchronizing
*
* \retval true Is busy
* \retval false Is ready
*/
static __always_inline bool rtc_is_busy(void)
{
return RTC32.SYNCCTRL & RTC32_SYNCBUSY_bm;
}
/**
* \internal
* \brief Get counter
*
* \return Counter value
*/
static inline uint32_t rtc_get_counter(void)
{
RTC32.SYNCCTRL = RTC32_SYNCCNT_bm;
while (RTC32.SYNCCTRL & RTC32_SYNCCNT_bm);
return RTC32.CNT;
}
/**
* \brief Set current time
*
* \param time Time value to set
*/
void rtc_set_time(uint32_t time)
{
RTC32.CTRL = 0;
while (rtc_is_busy());
RTC32.CNT = time;
RTC32.CTRL = RTC32_ENABLE_bm;
}
/**
* \brief Get current time
*
* \return Current time value
*/
uint32_t rtc_get_time(void)
{
return rtc_get_counter();
}
/**
* \brief Set alarm time
*
* Will set absolute time of the alarm that will call the callback function
* specified by \ref rtc_set_callback on expiration. Alternatively, you may
* use \ref rtc_alarm_has_triggered to check if the alarm has expired.
*
* Any pending alarm will be overwritten with this function.
*
* \param time Absolute time value. See also \ref rtc32_min_alarm_time
* \pre Needs interrupts disabled if used from several contexts
*/
void rtc_set_alarm(uint32_t time)
{
RTC32.INTCTRL = RTC32_COMPARE_INT_LEVEL;
RTC32.COMP = time;
RTC32.INTFLAGS = RTC32_COMPIF_bm;
}
/**
* \brief Check if pending alarm has triggered
*
* \retval true Alarm has triggered
* \retval false Alarm is pending
*/
bool rtc_alarm_has_triggered(void)
{
// Interrupt enable is used on pending alarm
return !(RTC32.INTCTRL & RTC32_COMPARE_INT_LEVEL);
}
/**
* \brief Set callback to call on alarm
*
* \param callback Callback function pointer
*/
void rtc_set_callback(rtc_callback_t callback)
{
rtc_data.callback = callback;
}
/**
* \brief Checks battery backup system status.
*
* This function should be called once after each reset of the device in order
* to determine the current battery backup status.
* This function can not be used to continuously poll the status of the backup
* system during normal operation since most status flags are only latched
* during the power up sequence of the device.
*
* \param first_time_startup Indicates whether or not the VBAT system has been
* started previously. This should be set to \c true upon the first call to this
* function, and \c false upon later calls. Typically, the value for this
* parameter should be stored in, e.g., EEPROM, in order to preserve the value
* when main system power is lost.
*
* \returns Battery backup system status.
*/
enum vbat_status_code rtc_vbat_system_check(bool first_time_startup)
{
enum vbat_status_code vbat_status;
uint8_t flags = VBAT.STATUS;
/* Ensure the module is clocked to be able to check the registers */
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_RTC);
/*
* Check if a sufficient voltage was detected on the VBAT input.
* The brown-out detector (BBBOD) will be sampled once when the
* device starts up and the result is visible as the BBPWR flag.
*/
if (flags & VBAT_BBPWR_bm) {
vbat_status = VBAT_STATUS_NO_POWER;
} else {
/*
* We have sufficient power, now we check if a power-on-reset
* (BBPOR) was detected on VBAT. This is visible from the BBPORF
* flag which is also only updated once when the device starts.
*/
if (flags & VBAT_BBPORF_bm) {
if (first_time_startup) {
vbat_status = VBAT_STATUS_INIT;
} else {
vbat_status = VBAT_STATUS_BBPOR;
}
} else if (flags & VBAT_BBBORF_bm) {
vbat_status = VBAT_STATUS_BBBOD;
} else {
VBAT.CTRL = VBAT_ACCEN_bm;
if (flags & VBAT_XOSCFAIL_bm) {
vbat_status = VBAT_STATUS_XOSCFAIL;
} else {
vbat_status = VBAT_STATUS_OK;
}
}
}
return vbat_status;
}
/**
* \internal
* \brief Initialize VBAT and start 32kHz oscillator
*
* Enables access to the VBAT system, performs a reset, enables the failure
* detection, and starts the oscillator.
*
* The default clock rate to the RTC32 is 1Hz but this can be changed to 1024Hz
* by the user in the module configuration by defining
* \ref CONFIG_RTC32_CLOCK_1024HZ.
*/
static void vbat_init(void)
{
// Enable access to VBAT
VBAT.CTRL |= VBAT_ACCEN_bm;
ccp_write_io((void *) &VBAT.CTRL, VBAT_RESET_bm);
VBAT.CTRL |= VBAT_XOSCFDEN_bm;
/* This delay is needed to give the voltage in the backup system some
* time to stabilize before we turn on the oscillator. If we do not
* have this delay we may get a failure detection.
*/
delay_us(200);
VBAT.CTRL |= VBAT_XOSCEN_bm | RTC32_CLOCK;
while (!(VBAT.STATUS & VBAT_XOSCRDY_bm));
}
/**
* \brief Initialize the 32kHz oscillator and RTC32
*
* Starts up the 32kHz oscillator in the backup system and initializes the
* RTC32.
*
* \note When the backup system is used, the function \ref
* rtc_vbat_system_check should be called to determine if a re-initialization
* must be done.
*/
void rtc_init(void)
{
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_RTC);
// Set up VBAT system and start oscillator
vbat_init();
// Disable the RTC32 module before setting it up
RTC32.CTRL = 0;
while (rtc_is_busy());
// Set up maximum period and start at 0
RTC32.PER = 0xffffffff;
RTC32.CNT = 0;
while (rtc_is_busy());
RTC32.INTCTRL = 0;
RTC32.CTRL = RTC32_ENABLE_bm;
// Make sure it's sync'ed before return
while (rtc_is_busy());
}
/**
* \internal
* \brief Compare interrupt used for alarm
*
* Disables the RTC32 interrupts, then calls the alarm callback function if one
* has been set.
*/
ISR(RTC32_COMP_vect)
{
RTC32.INTCTRL = 0;
if (rtc_data.callback)
rtc_data.callback(rtc_get_time());
}
ports/xplained/ASF/xmega/drivers/rtc32/rtc32.h
+324
View File
@@ -0,0 +1,324 @@
/**
* \file
*
* \brief AVR XMEGA 32-bit Real Time Counter driver definitions
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef DRIVERS_RTC32_RTC32_H
#define DRIVERS_RTC32_RTC32_H
#include <compiler.h>
#include <conf_rtc32.h>
/**
* \defgroup rtc32_group 32-bit Real Time Counter (RTC32)
*
* See \ref xmega_rtc32_quickstart.
*
* This is a driver implementation for the XMEGA RTC32.
*
* This driver can be used to keep track of time; setting alarms, with or
* without function callbacks; initializing and checking the battery backup
* system.
*
* \section rtc32_min_alarm_time Minimum allowed alarm time
*
* Due to the RTC32 clock synchronization, there is a minimum alarm time that
* will generate a interrupt. This minimum time is 2 RTC32 clock cycles.
*
* Also, if a new RTC32 clock cycle is imminent at the time of setting the
* alarm, there is a risk that it will be missed even with the value 2. If there
* is a risk that this may occur, it is recommended to use a minimum alarm time
* of 3.
*
* @{
*/
/**
* \def CONFIG_RTC32_COMPARE_INT_LEVEL
* \brief Configuration symbol for interrupt level to use on alarm
*
* Define this in \ref conf_rtc32.h as the desired interrupt level, or leave it
* undefined to use the default.
*/
#ifdef __DOXYGEN__
# define CONFIG_RTC32_COMPARE_INT_LEVEL
#endif
/**
* \def CONFIG_RTC32_CLOCK_1024HZ
* \brief Configuration symbol for selecting 1024Hz clock instead of 1Hz
*
* Define this in \ref conf_rtc32.h if 1024Hz clock is desired. Otherwise, leave
* it undefined.
*/
#ifdef __DOXYGEN__
# define CONFIG_RTC32_CLOCK_1024HZ
#endif
//! \brief Battery backup system status codes
enum vbat_status_code
{
/**
* \brief Backup system is operating and no errors were detected.
*
* The backup system is configured and had no issues while main power was
* lost. Hence, all data stored in the backup domain is valid.
*/
VBAT_STATUS_OK,
/**
* \brief No power detected on VBAT.
*
* No power was detected on the VBAT pin and therefore all data within the
* backup system is invalid.
*
* The voltage on the VBAT pin is only sampled after a POR of the device,
* therefore it is not possible to detect any voltage loss on the VBAT pin
* during normal operation of the device.
*/
VBAT_STATUS_NO_POWER,
/**
* \brief The backup system must be initialized.
*
* A POR was detected on VBAT input, indicating that a supply was connected to
* the VBAT pin. Since this is also the first start-up of the device, it is
* necessary to initialize the RTC32.
*/
VBAT_STATUS_INIT,
/**
* \brief A POR was detected on the VBAT input.
*
* POR detection also works while the VBAT system is powered from main power,
* but the detection flag is only latched after a POR of the main system.
* A POR can happen when the power is lost and restored again on the VBAT pin
* while main power was also not present, or even when main power was present,
* but in this case the flag will only be latched after the next POR of the main
* system.
* If a POR is detected on VBAT, it should always be treated as if the backup
* system is in an unknown state, i.e., that all data is invalid.
*/
VBAT_STATUS_BBPOR,
/**
* \brief A brown-out was detected on the VBAT input.
*
* The backup system is in an unknown state and therefore the time in the RTC32
* is invalid. This can happen when the voltage on VBAT drops below the
* brown-out detection level while main power is absent.
*/
VBAT_STATUS_BBBOD,
/**
* \brief A failure was detected on the oscillator.
*
* The oscillator stopped for at least TBD period of time and because of that
* we can not rely on the RTC time any more.
*
* \todo Determine minimum period for detection of oscillator outage.
*/
VBAT_STATUS_XOSCFAIL,
};
enum vbat_status_code rtc_vbat_system_check (bool first_time_init);
/**
* \brief Callback definition for alarm callback
*
* \param time The time of the alarm
*/
typedef void (*rtc_callback_t) (uint32_t time);
void rtc_set_callback (rtc_callback_t callback);
void rtc_set_time (uint32_t time);
uint32_t rtc_get_time (void);
void rtc_set_alarm (uint32_t time);
bool rtc_alarm_has_triggered (void);
/**
* \brief Set alarm relative to current time
*
* \param offset Offset to current time. This is minimum value, so the alarm
* might happen at up to one time unit later. See also \ref
* rtc32_min_alarm_time
*/
static inline void
rtc_set_alarm_relative (uint32_t offset)
{
Assert (offset >= 2);
rtc_set_alarm (rtc_get_time () + offset);
}
void rtc_init (void);
//! @}
/**
* \page xmega_rtc32_quickstart Quick start guide for RTC32 driver
*
* This is the quick start guide for the \ref rtc32_group "RTC32 driver", with
* step-by-step instructions on how to configure and use the drivers in a
* selection of use cases.
*
* The use cases contain several code fragments. The code fragments in the
* steps for setup can be copied into a custom initialization function, while
* the steps for usage can be copied into, e.g., the main application function.
*
* \section rtc32_basic_use_case Basic use case
*
* \section rtc32_basic_use_case_setup Setup steps
*
* \subsection rtc32_basic_use_case_setup_code Example code
* Add to the initialization code:
* \code
* sysclk_init();
* rtc_init();
* \endcode
*
* \subsection rtc32_basic_use_case_setup_flow Workflow
* -# Ensure that conf_rtc.h is present for the driver.
* - \note This configuration file is used by the driver and
* should not be included by the user.
* -# Initialize system clock:
* - \code sysclk_init(); \endcode
* -# Call RTC32 driver's own init function to initialize the 32kHz oscillator
* and RTC32:
* - \code rtc_init(); \endcode
*
* \section rtc32_basic_use_case_usage Usage steps
*
* \subsection rtc32_basic_use_case_usage_code Example code
* Add to, e.g., main loop in application C-file:
* \code
* rtc_get_time();
* \endcode
*
* \subsection rtc32_basic_use_case_usage_flow Workflow
* -# Get current time of the RTC32:
* - \code rtc_get_time(); \endcode
*
* \section rtc32_use_cases Advanced use cases
* For more advanced use of the RTC32 driver, see the following use cases:
* - \subpage rtc32_use_case_1 :
*/
/**
* \page rtc32_use_case_1 Use case #1
*
* This use case shows how to set an alarm for the RTC32.
*
* \section rtc32_use_case_1_setup Setup steps
*
* \subsection rtc32_basic_use_case_setup_prereq Prerequisites
* For the setup code of this use case to work, the following must
* be added to the project:
* -# PMIC for interrupt handling.
* -# Sleep Manager.
* -# A \ref rtc_callback_t "callback" function, called alarm, that
* reschedules the alarm must be provided
* by the user.
* \code
* static void alarm(uint32_t time)
* {
* rtc_set_alarm(2);
* }
* \endcode
* \note Since the next alarm will be rounded up to the next second pass, this
* will actually happen in 3 seconds.
*
* \subsection rtc32_use_case_1_setup_code Example code
* Add to application initialization:
* \code
* pmic_init();
* sysclk_init();
* sleepmgr_init();
* rtc_init();
* rtc_set_callback(alarm);
* cpu_irq_enable();
* \endcode
*
* \subsection rtc32_use_case_1_setup_flow Workflow
* -# Ensure that conf_rtc32.h is present for the driver.
* - \note This configuration file is used by the driver and
* should not be included by the user.
* -# Call the init function of the PMIC driver to enable all interrupt levels:
* - \code pmic_init(); \endcode
* -# Initialize system clock:
* - \code sysclk_init(); \endcode
* -# Call the init function of the sleep manager driver to be able to sleep
* waiting for alarm:
* - \code sleepmgr_init(); \endcode
* -# Call RTC32 driver's own init function to initialize the 32kHz oscillator
* and RTC32:
* - \code rtc_init(); \endcode
* -# Set callback function to call on alarm:
* - \code rtc_set_callback(alarm); \endcode
* - \note The callback function alarm must be defined by the user.
* -# Enable interrupts globally:
* - \code cpu_irq_enable(); \endcode
*
* \section rtc32_use_case_1_usage Usage steps
*
* \subsection rtc32_use_case_1_usage_code Example code
* \code
* rtc_set_alarm_relative(3);
* while (true) {
* sleepmgr_enter_sleep();
* }
* \endcode
*
* \subsection rtc32_use_case_1_usage_flow Workflow
* -# Set the alarm to trigger on next time unit roll over:
* - \code rtc_set_alarm_relative(3); \endcode
* \note The lowest value which is safe to use is 3. The use of 2 could
* happen in a second change, and we would not get an interrupt. A
* value of 3 causes the alarm to be set of in 3-4 seconds.
* -# Sleep between each triggered alarm:
* - \code
* while (true) {
* sleepmgr_enter_sleep();
* }
* \endcode
*/
#endif /* DRIVERS_RTC32_RTC32_H */
ports/xplained/ASF/xmega/drivers/sleep/sleep.h
+169
View File
@@ -0,0 +1,169 @@
/**
* \file
*
* \brief Sleep controller driver
*
* Copyright (c) 2010 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SLEEP_H
#define SLEEP_H
#include <compiler.h>
/**
* \defgroup sleep_group Sleep controller driver
*
* This is a low-level driver implementation for the AVR XMEGA sleep controller.
*
* \note To minimize the code overhead, these functions do not feature
* interrupt-protected access since they are likely to be called inside
* interrupt handlers or in applications where such protection is not
* necessary. If such protection is needed, it must be ensured by the calling
* code.
*
* \section xmega_sleep_quickstart_section Quick Start Guide
* See \ref xmega_sleep_quickstart
* @{
*/
#if defined(__ICCAVR__) || defined(__DOXYGEN__)
# include <intrinsics.h>
//! Macro for issuing the sleep instruction.
# define sleep_enter() __sleep()
/**
* \brief Enable sleep
*/
static inline void
sleep_enable (void)
{
SLEEP.CTRL |= SLEEP_SEN_bm;
}
/**
* \brief Disable sleep
*/
static inline void
sleep_disable (void)
{
SLEEP.CTRL &= ~SLEEP_SEN_bm;
}
#elif defined(__GNUC__)
# include <avr/sleep.h>
# define sleep_enter() sleep_cpu()
#else
# error Unsupported compiler.
#endif
/**
* \brief Set new sleep mode
*
* \param mode Sleep mode, from the device IO header file.
*/
static inline void
sleep_set_mode (enum SLEEP_SMODE_enum mode)
{
SLEEP.CTRL = mode | (SLEEP.CTRL & ~SLEEP_SMODE_gm);
}
//! @}
/**
* \page xmega_sleep_quickstart Quick Start Guide for the XMEGA Sleep Driver
*
* This is the quick start guide for the \ref sleep_group "Sleep Driver", with
* step-by-step instructions on how to configure and use the driver for a
* specific use case.
*
* The section described below can be copied into, e.g. the main application
* loop or any other function that will need to control and execute different
* sleep modes on the device.
*
* \section xmega_sleep_quickstart_basic Basic usage of the sleep driver
* This use case will prepare the device to enter the Power Down sleep mode and
* then enter the sleep mode. After waking up it will disable sleep.
*
* \section xmega_sleep_basic_usage Usage steps
* \subsection xmega_sleep_basic_usage_code Example code
* Add to, e.g., the main loop in the application C-file:
* \code
* sleep_set_mode(SLEEP_SMODE_PDOWN_gc);
* sleep_enable();
* sleep_enter();
* sleep_disable();
* \endcode
*
* \subsection xmega_sleep_basic_usage Workflow
* -# Set what sleep mode to use, the different sleep modes can be found in the
* device header file under the enum definition SLEEP_SMODE_enum:
* - \code sleep_set_mode(SLEEP_SMODE_PDOWN_gc); \endcode
* -# Enable that the device are allowed to go to sleep:
* - \code sleep_enable(); \endcode
* - \note This function has to be called in order for the device to go to
* sleep. This is a safety feature to stop the device to go to sleep
* unintentionally, even though it is possible to have this enabled at all times
* it is recommended to enable sleep mode only when you intend to go to sleep
* within a few clock cycles.
* -# Enter sleep mode:
* - \code sleep_enter(); \endcode
* - \attention Make sure to enable global interrupt and the interrupt you
* plan to use as wake-up source for your device, do also pay special
* attention to what wake-up sources are available for the different sleep
* modes. Failing to enable interrupts may result in indefinite sleep until
* power is cycled!
* -# When the device is woken from sleep it will execute the interrupt handler
* related to the wakeup-source (interrupt source) and continue on the next line
* of code after the \ref sleep_enter() call. Make sure to disable sleep when
* waking up.
* - \code sleep_disable(); \endcode
*
* \subsection xmega_sleep_basic_sleep_modes Sleep Modes
* Possible sleep modes depend on the device that is used. Please refer to the
* device datasheet and header file to find these definitions.
*
* As an example the ATxmega32A4U device has the following sleep modes:
* - Idle sleep: SLEEP_SMODE_IDLE_gc
* - Power Down: SLEEP_SMODE_PDOWN_gc
* - Power Save: SLEEP_SMODE_PSAVE_gc
* - Standby: SLEEP_SMODE_STDBY_gc
* - Extended standby: SLEEP_SMODE_ESTDBY_gc
*/
#endif /* SLEEP_H */
ports/xplained/ASF/xmega/drivers/tc/tc.c
+1089
View File
File diff suppressed because it is too large Load Diff
ports/xplained/ASF/xmega/drivers/tc/tc.h
+1684
View File
File diff suppressed because it is too large Load Diff
ports/xplained/ASF/xmega/drivers/twi/twi_common.h
+672
View File
@@ -0,0 +1,672 @@
/**
* \file
*
* \brief AVR XMEGA TWI driver common definitions
*
* Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef TWI_COMMON_H
#define TWI_COMMON_H
/* Fix header error in iox32e5.h */
#ifndef TWI_BRIDGEEN_bm
#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */
#endif
#ifndef TWI_BRIDGEEN_bp
#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */
#endif
#ifndef TWI_SFMPEN_bm
#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */
#endif
#ifndef TWI_SFMPEN_bp
#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */
#endif
/* End of: Fix header error in iox32e5.h */
/**
* \defgroup group_xmega_drivers_twi TWI - Two-Wire Interface
*
* See \ref xmega_twi_quickstart
*
* Driver for the Two-Wire Interface (TWI).
* Provides functions for configuring and using the TWI in both master and
* slave mode.
*
* \section xmega_twi_quickstart_guide Quick start guide
* See \ref xmega_twi_quickstart
*
* \{
*/
/*!
* \brief Input parameters when initializing the twi module mode
*/
typedef struct
{
//! The baudrate of the TWI bus.
unsigned long speed;
//! The baudrate register value of the TWI bus.
unsigned long speed_reg;
//! The desired address.
char chip;
}
twi_options_t;
/*!
* \brief Information concerning the data transmission
*/
typedef struct
{
//! TWI chip address to communicate with.
char chip;
//! TWI address/commands to issue to the other chip (node).
uint8_t addr[3];
//! Length of the TWI data address segment (1-3 bytes).
int addr_length;
//! Where to find the data to be written.
void *buffer;
//! How many bytes do we want to write.
unsigned int length;
//! Whether to wait if bus is busy (false) or return immediately (true)
bool no_wait;
}
twi_package_t;
/**
* \}
*/
/**
* \page xmega_twi_quickstart Quick start guide for XMEGA TWI driver
*
* This is the quick start guide for the
*\ref group_xmega_drivers_twi "TWI Driver", with step-by-step instructions on
* how to configure and use the driver for specific use cases.
*
* The section described below can be compiled into e.g. the main application
* loop or any other function that might use the TWI functionality.
*
* \section xmega_twi_quickstart_basic Basic use case of the TWI driver
* In our basic use case, the TWI driver is used to set up internal
* communication between two TWI modules on the XMEGA A1 Xplained board, since
* this is the most simple way to show functionality without external
* dependencies. TWIC is set up in master mode, and TWIF is set up in slave
* mode, and these are connected together on the board by placing a connection
* between SDA/SCL on J1 to SDA/SCL on J4.
*
* \section xmega_twi_qs_use_cases Specific use case for XMEGA E devices
* - \subpage xmega_twi_xmegae
*
* \section xmega_twi_quickstart_prereq Prerequisites
* The \ref sysclk_group module is required to enable the clock to the TWI
* modules. The \ref group_xmega_drivers_twi_twim "TWI Master" driver and
* \ref group_xmega_drivers_twi_twis "TWI Slave" driver must also be included.
*
* \section xmega_twi_quickstart_setup Setup
* When the \ref sysclk_group module has been included, it must be initialized:
* \code
* sysclk_init();
* \endcode
*
* \section xmega_twi_quickstart_use_case Use case
*
* \subsection xmega_twi_quickstart_use_case_example_code Example code
*
* \code
* #define TWI_MASTER TWIC
* #define TWI_MASTER_PORT PORTC
* #define TWI_SLAVE TWIF
* #define TWI_SPEED 50000
* #define TWI_MASTER_ADDR 0x50
* #define TWI_SLAVE_ADDR 0x60
*
* #define DATA_LENGTH 8
*
* TWI_Slave_t slave;
*
* uint8_t data[DATA_LENGTH] = {
* 0x0f, 0x1f, 0x2f, 0x3f, 0x4f, 0x5f, 0x6f, 0x7f
* };
*
* uint8_t recv_data[DATA_LENGTH] = {
* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
* };
*
* twi_options_t m_options = {
* .speed = TWI_SPEED,
* .chip = TWI_MASTER_ADDR,
* .speed_reg = TWI_BAUD(sysclk_get_cpu_hz(), TWI_SPEED)
* };
*
* static void slave_process(void) {
* int i;
*
* for(i = 0; i < DATA_LENGTH; i++) {
* recv_data[i] = slave.receivedData[i];
* }
* }
*
* ISR(TWIF_TWIS_vect) {
* TWI_SlaveInterruptHandler(&slave);
* }
*
* void send_and_recv_twi()
* {
* twi_package_t packet = {
* .addr_length = 0,
* .chip = TWI_SLAVE_ADDR,
* .buffer = (void *)data,
* .length = DATA_LENGTH,
* .no_wait = false
* };
*
* uint8_t i;
*
* TWI_MASTER_PORT.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
* TWI_MASTER_PORT.PIN1CTRL = PORT_OPC_WIREDANDPULL_gc;
*
* irq_initialize_vectors();
*
* sysclk_enable_peripheral_clock(&TWI_MASTER);
* twi_master_init(&TWI_MASTER, &m_options);
* twi_master_enable(&TWI_MASTER);
*
* sysclk_enable_peripheral_clock(&TWI_SLAVE);
* TWI_SlaveInitializeDriver(&slave, &TWI_SLAVE, *slave_process);
* TWI_SlaveInitializeModule(&slave, TWI_SLAVE_ADDR,
* TWI_SLAVE_INTLVL_MED_gc);
*
* for (i = 0; i < TWIS_SEND_BUFFER_SIZE; i++) {
* slave.receivedData[i] = 0;
* }
*
* cpu_irq_enable();
*
* twi_master_write(&TWI_MASTER, &packet);
*
* do {
* // Nothing
* } while(slave.result != TWIS_RESULT_OK);
* }
* \endcode
*
* \subsection xmega_twi_quickstart_use_case_workflow Workflow
* We first create some definitions. TWI master and slave, speed, and
* addresses:
* \code
* #define TWI_MASTER TWIC
* #define TWI_MASTER_PORT PORTC
* #define TWI_SLAVE TWIF
* #define TWI_SPEED 50000
* #define TWI_MASTER_ADDR 0x50
* #define TWI_SLAVE_ADDR 0x60
*
* #define DATA_LENGTH 8
* \endcode
*
* We create a handle to contain information about the slave module:
* \code
* TWI_Slave_t slave;
* \endcode
*
* We create two variables, one which contains data that will be transmitted,
* and one which will contain the received data:
* \code
* uint8_t data[DATA_LENGTH] = {
* 0x0f, 0x1f, 0x2f, 0x3f, 0x4f, 0x5f, 0x6f, 0x7f
* };
*
* uint8_t recv_data[DATA_LENGTH] = {
* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
* };
* \endcode
*
* Options for the TWI module initialization procedure are given below:
* \code
* twi_options_t m_options = {
* .speed = TWI_SPEED,
* .chip = TWI_MASTER_ADDR,
* .speed_reg = TWI_BAUD(sysclk_get_cpu_hz(), TWI_SPEED)
* };
* \endcode
*
* The TWI slave will fire an interrupt when it has received data, and the
* function below will be called, which will copy the data from the driver
* to our recv_data buffer:
* \code
* static void slave_process(void) {
* int i;
*
* for(i = 0; i < DATA_LENGTH; i++) {
* recv_data[i] = slave.receivedData[i];
* }
* }
* \endcode
*
* Set up the interrupt handler:
* \code
* ISR(TWIF_TWIS_vect) {
* TWI_SlaveInterruptHandler(&slave);
* }
* \endcode
*
* We create a packet for the data that we will send to the slave TWI:
* \code
* twi_package_t packet = {
* .addr_length = 0,
* .chip = TWI_SLAVE_ADDR,
* .buffer = (void *)data,
* .length = DATA_LENGTH,
* .no_wait = false
* };
* \endcode
*
* We need to set SDA/SCL pins for the master TWI to be wired and
* enable pull-up:
* \code
* TWI_MASTER_PORT.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
* TWI_MASTER_PORT.PIN1CTRL = PORT_OPC_WIREDANDPULL_gc;
* \endcode
*
* We enable all interrupt levels:
* \code
* irq_initialize_vectors();
* \endcode
*
* We enable the clock to the master module, and initialize it with the
* options we described before:
* \code
* sysclk_enable_peripheral_clock(&TWI_MASTER);
* twi_master_init(&TWI_MASTER, &m_options);
* twi_master_enable(&TWI_MASTER);
* \endcode
*
* We do the same for the slave, using the slave portion of the driver,
* passing through the slave_process function, its address, and set medium
* interrupt level:
* \code
* sysclk_enable_peripheral_clock(&TWI_SLAVE);
* TWI_SlaveInitializeDriver(&slave, &TWI_SLAVE, *slave_process);
* TWI_SlaveInitializeModule(&slave, TWI_SLAVE_ADDR,
* TWI_SLAVE_INTLVL_MED_gc);
* \endcode
*
* We zero out the receive buffer in the slave handle:
* \code
* for (i = 0; i < TWIS_SEND_BUFFER_SIZE; i++) {
* slave.receivedData[i] = 0;
* }
* \endcode
*
* And enable interrupts:
* \code
* cpu_irq_enable();
* \endcode
*
* Finally, we write our packet through the master TWI module:
* \code
* twi_master_write(&TWI_MASTER, &packet);
* \endcode
*
* We wait for the slave to finish receiving:
* \code
* do {
* // Waiting
* } while(slave.result != TWIS_RESULT_OK);
* \endcode
* \note When the slave has finished receiving, the slave_process()
* function will copy the received data into our recv_data buffer,
* which now contains what was sent through the master.
*
*/
/**
* \page xmega_twi_xmegae XMEGA E TWI additions with Bridge and Fast Mode Plus
*
* XMEGA E TWI module provides two additionnnal features compare to regular
* XMEGA TWI module:
* - Fast Mode Plus communication speed
* - Bridge Mode
*
* The following use case will set up the TWI module to be used in in Fast Mode
* Plus together with bridge mode.
* This use case is similar to the regular XMEGA TWI initialization, it only
* differs by the activation of both Bridge and Fast Mode Plus mode.
*
* \subsection xmegae_twi_quickstart_use_case_example_code Example code
*
* \code
* #define TWI_MASTER TWIC
* #define TWI_MASTER_PORT PORTC
* #define TWI_SLAVE TWIC
* #define TWI_SPEED 1000000
* #define TWI_MASTER_ADDR 0x50
* #define TWI_SLAVE_ADDR 0x50
*
* #define DATA_LENGTH 8
*
* TWI_Slave_t slave;
*
* uint8_t data[DATA_LENGTH] = {
* 0x0f, 0x1f, 0x2f, 0x3f, 0x4f, 0x5f, 0x6f, 0x7f
* };
*
* uint8_t recv_data[DATA_LENGTH] = {
* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
* };
*
* twi_options_t m_options = {
* .speed = TWI_SPEED,
* .chip = TWI_MASTER_ADDR,
* .speed_reg = TWI_BAUD(sysclk_get_cpu_hz(), TWI_SPEED)
* };
*
* static void slave_process(void) {
* int i;
*
* for(i = 0; i < DATA_LENGTH; i++) {
* recv_data[i] = slave.receivedData[i];
* }
* }
*
* ISR(TWIC_TWIS_vect) {
* TWI_SlaveInterruptHandler(&slave);
* }
*
* void send_and_recv_twi()
* {
* twi_package_t packet = {
* .addr_length = 0,
* .chip = TWI_SLAVE_ADDR,
* .buffer = (void *)data,
* .length = DATA_LENGTH,
* .no_wait = false
* };
*
* uint8_t i;
*
* TWI_MASTER_PORT.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
* TWI_MASTER_PORT.PIN1CTRL = PORT_OPC_WIREDANDPULL_gc;
*
* irq_initialize_vectors();
*
* sysclk_enable_peripheral_clock(&TWI_MASTER);
*
* twi_bridge_enable(&TWI_MASTER);
* twi_fast_mode_enable(&TWI_MASTER);
* twi_slave_fast_mode_enable(&TWI_SLAVE);
*
* twi_master_init(&TWI_MASTER, &m_options);
* twi_master_enable(&TWI_MASTER);
*
* sysclk_enable_peripheral_clock(&TWI_SLAVE);
* TWI_SlaveInitializeDriver(&slave, &TWI_SLAVE, *slave_process);
* TWI_SlaveInitializeModule(&slave, TWI_SLAVE_ADDR,
* TWI_SLAVE_INTLVL_MED_gc);
*
* for (i = 0; i < TWIS_SEND_BUFFER_SIZE; i++) {
* slave.receivedData[i] = 0;
* }
*
* cpu_irq_enable();
*
* twi_master_write(&TWI_MASTER, &packet);
*
* do {
* // Nothing
* } while(slave.result != TWIS_RESULT_OK);
* }
* \endcode
*
* \subsection xmegae_twi_quickstart_use_case_workflow Workflow
* We first create some definitions. TWI master and slave, speed, and
* addresses:
* \code
* #define TWI_MASTER TWIC
* #define TWI_MASTER_PORT PORTC
* #define TWI_SLAVE TWIC
* #define TWI_SPEED 1000000
* #define TWI_MASTER_ADDR 0x50
* #define TWI_SLAVE_ADDR 0x50
*
* #define DATA_LENGTH 8
* \endcode
*
* We create a handle to contain information about the slave module:
* \code
* TWI_Slave_t slave;
* \endcode
*
* We create two variables, one which contains data that will be transmitted,
* and one which will contain the received data:
* \code
* uint8_t data[DATA_LENGTH] = {
* 0x0f, 0x1f, 0x2f, 0x3f, 0x4f, 0x5f, 0x6f, 0x7f
* };
*
* uint8_t recv_data[DATA_LENGTH] = {
* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
* };
* \endcode
*
* Options for the TWI module initialization procedure are given below:
* \code
* twi_options_t m_options = {
* .speed = TWI_SPEED,
* .chip = TWI_MASTER_ADDR,
* .speed_reg = TWI_BAUD(sysclk_get_cpu_hz(), TWI_SPEED)
* };
* \endcode
*
* The TWI slave will fire an interrupt when it has received data, and the
* function below will be called, which will copy the data from the driver
* to our recv_data buffer:
* \code
* static void slave_process(void) {
* int i;
*
* for(i = 0; i < DATA_LENGTH; i++) {
* recv_data[i] = slave.receivedData[i];
* }
* }
* \endcode
*
* Set up the interrupt handler:
* \code
* ISR(TWIC_TWIS_vect) {
* TWI_SlaveInterruptHandler(&slave);
* }
* \endcode
*
* We create a packet for the data that we will send to the slave TWI:
* \code
* twi_package_t packet = {
* .addr_length = 0,
* .chip = TWI_SLAVE_ADDR,
* .buffer = (void *)data,
* .length = DATA_LENGTH,
* .no_wait = false
* };
* \endcode
*
* We need to set SDA/SCL pins for the master TWI to be wired and
* enable pull-up:
* \code
* TWI_MASTER_PORT.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
* TWI_MASTER_PORT.PIN1CTRL = PORT_OPC_WIREDANDPULL_gc;
* \endcode
*
* We enable all interrupt levels:
* \code
* irq_initialize_vectors();
* \endcode
*
* We enable the clock to the master module:
* \code
* sysclk_enable_peripheral_clock(&TWI_MASTER);
* \endcode
*
* We enable the global TWI bridge mode as well as the Fast Mode Plus
* communication speed for both master and slave:
* \code
* twi_bridge_enable(&TWI_MASTER);
* twi_fast_mode_enable(&TWI_MASTER);
* twi_slave_fast_mode_enable(&TWI_SLAVE);
* \endcode
*
* Initialize the master module with the options we described before:
* \code
* twi_master_init(&TWI_MASTER, &m_options);
* twi_master_enable(&TWI_MASTER);
* \endcode
*
* We do the same for the slave, using the slave portion of the driver,
* passing through the slave_process function, its address, and set medium
* interrupt level:
* \code
* sysclk_enable_peripheral_clock(&TWI_SLAVE);
* TWI_SlaveInitializeDriver(&slave, &TWI_SLAVE, *slave_process);
* TWI_SlaveInitializeModule(&slave, TWI_SLAVE_ADDR,
* TWI_SLAVE_INTLVL_MED_gc);
* \endcode
*
* We zero out the receive buffer in the slave handle:
* \code
* for (i = 0; i < TWIS_SEND_BUFFER_SIZE; i++) {
* slave.receivedData[i] = 0;
* }
* \endcode
*
* And enable interrupts:
* \code
* cpu_irq_enable();
* \endcode
*
* Finally, we write our packet through the master TWI module:
* \code
* twi_master_write(&TWI_MASTER, &packet);
* \endcode
*
* We wait for the slave to finish receiving:
* \code
* do {
* // Waiting
* } while(slave.result != TWIS_RESULT_OK);
* \endcode
* \note When the slave has finished receiving, the slave_process()
* function will copy the received data into our recv_data buffer,
* which now contains what was sent through the master.
*
*/
#if XMEGA_E
/*! \brief Enable bridge mode on TWIC.
* SDA and SCL are on PORTC for Master and on PORTD for slave
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_bridge_enable (TWI_t * twi)
{
twi->CTRL |= TWI_BRIDGEEN_bm;
}
/*! \brief Disable bridge mode on TWIC.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_bridge_disable (TWI_t * twi)
{
twi->CTRL &= (~TWI_BRIDGEEN_bm);
}
/*! \brief Enable Fast mode plus on TWIC (1MHz).
* FMPEN bit enables 1MHz on master and slave.
* In bridge mode, it enables only 1MHz on master.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_fast_mode_enable (TWI_t * twi)
{
twi->CTRL |= TWI_FMPEN_bm;
}
/*! \brief Disable Fast mode plus on TWIC (1MHz).
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_fast_mode_disable (TWI_t * twi)
{
twi->CTRL &= (~TWI_FMPEN_bm);
}
/*! \brief Enable Fast mode plus for slave.
* If set in bridge mode, it enables 1MHz on slave.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_slave_fast_mode_enable (TWI_t * twi)
{
twi->CTRL |= TWI_SFMPEN_bm;
}
/*! \brief Disable Fast mode plus for slave.
* If reset in bridge mode, it disables 1MHz on slave.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_slave_fast_mode_disable (TWI_t * twi)
{
twi->CTRL &= (~TWI_SFMPEN_bm);
}
#endif
#endif // TWI_COMMON_H
ports/xplained/ASF/xmega/drivers/twi/twim.c
+389
View File
@@ -0,0 +1,389 @@
/**
* \file
*
* \brief XMEGA TWI master source file.
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "twim.h"
/* Master Transfer Descriptor */
static struct {
TWI_t *bus; // Bus register interface
twi_package_t *pkg; // Bus message descriptor
int addr_count; // Bus transfer address data counter
unsigned int data_count; // Bus transfer payload data counter
bool read; // Bus transfer direction
bool locked; // Bus busy or unavailable
volatile status_code_t status; // Transfer status
} transfer;
/**
* \internal
*
* \brief TWI Master Interrupt Vectors
*
* The TWI master interrupt request entry points are conditionally compiled
* for the TWI interfaces supported by the XMEGA MCU variant. All of these
* entry points call a common service function, twim_interrupt_handler(),
* to handle bus events. This handler uses the bus interface and message
* parameters specified in the global \c transfer structure.
*/
static void twim_interrupt_handler(void);
#ifdef TWIC
ISR(TWIC_TWIM_vect)
{
twim_interrupt_handler();
}
#endif
#ifdef TWID
ISR(TWID_TWIM_vect)
{
twim_interrupt_handler();
}
#endif
#ifdef TWIE
ISR(TWIE_TWIM_vect)
{
twim_interrupt_handler();
}
#endif
#ifdef TWIF
ISR(TWIF_TWIM_vect)
{
twim_interrupt_handler();
}
#endif
/**
* \internal
*
* \brief Test for an idle bus state.
*
* Software can determine the TWI master bus state (unknown, idle, owner, or
* busy) by reading the bus master status register:
*
* TWI_MASTER_BUSSTATE_UNKNOWN_gc Bus state is unknown.
* TWI_MASTER_BUSSTATE_IDLE_gc Bus state is idle.
* TWI_MASTER_BUSSTATE_OWNER_gc Bus state is owned by the master.
* TWI_MASTER_BUSSTATE_BUSY_gc Bus state is busy.
*
* \param twi Base address of the TWI (i.e. &TWI_t).
*
* \retval true The bus is currently idle.
* \retval false The bus is currently busy.
*/
static inline bool twim_idle(const TWI_t * twi)
{
return ((twi->MASTER.STATUS & TWI_MASTER_BUSSTATE_gm)
== TWI_MASTER_BUSSTATE_IDLE_gc);
}
/**
* \internal
*
* \brief Get exclusive access to global TWI resources.
*
* Wait to acquire bus hardware interface and ISR variables.
*
* \param no_wait Set \c true to return instead of doing busy-wait (spin-lock).
*
* \return STATUS_OK if the bus is acquired, else ERR_BUSY.
*/
static inline status_code_t twim_acquire(bool no_wait)
{
while (transfer.locked) {
if (no_wait) {
return ERR_BUSY;
}
}
irqflags_t const flags = cpu_irq_save();
transfer.locked = true;
transfer.status = OPERATION_IN_PROGRESS;
cpu_irq_restore(flags);
return STATUS_OK;
}
/**
* \internal
*
* \brief Release exclusive access to global TWI resources.
*
* Release bus hardware interface and ISR variables previously locked by
* a call to \ref twim_acquire(). This function will busy-wait for
* pending driver operations to complete.
*
* \return status_code_t
* - STATUS_OK if the transfer completes
* - ERR_BUSY to indicate an unavailable bus
* - ERR_IO_ERROR to indicate a bus transaction error
* - ERR_NO_MEMORY to indicate buffer errors
* - ERR_PROTOCOL to indicate an unexpected bus state
*/
static inline status_code_t twim_release(void)
{
/* First wait for the driver event handler to indicate something
* other than a transfer in-progress, then test the bus interface
* for an Idle bus state.
*/
while (OPERATION_IN_PROGRESS == transfer.status);
while (!twim_idle(transfer.bus)) {
barrier();
}
status_code_t const status = transfer.status;
transfer.locked = false;
return status;
}
/**
* \internal
*
* \brief TWI master write interrupt handler.
*
* Handles TWI transactions (master write) and responses to (N)ACK.
*/
static inline void twim_write_handler(void)
{
TWI_t *const bus = transfer.bus;
twi_package_t *const pkg = transfer.pkg;
if (transfer.addr_count < pkg->addr_length) {
const uint8_t *const data = pkg->addr;
bus->MASTER.DATA = data[transfer.addr_count++];
} else if (transfer.data_count < pkg->length) {
if (transfer.read) {
/* Send repeated START condition (Address|R/W=1). */
bus->MASTER.ADDR |= 0x01;
} else {
const uint8_t *const data = pkg->buffer;
bus->MASTER.DATA = data[transfer.data_count++];
}
} else {
/* Send STOP condition to complete the transaction. */
bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
transfer.status = STATUS_OK;
}
}
/**
* \internal
*
* \brief TWI master read interrupt handler.
*
* This is the master read interrupt handler that takes care of
* reading bytes from the TWI slave.
*/
static inline void twim_read_handler(void)
{
TWI_t *const bus = transfer.bus;
twi_package_t *const pkg = transfer.pkg;
if (transfer.data_count < pkg->length) {
uint8_t *const data = pkg->buffer;
data[transfer.data_count++] = bus->MASTER.DATA;
/* If there is more to read, issue ACK and start a byte read.
* Otherwise, issue NACK and STOP to complete the transaction.
*/
if (transfer.data_count < pkg->length) {
bus->MASTER.CTRLC = TWI_MASTER_CMD_RECVTRANS_gc;
} else {
bus->MASTER.CTRLC = TWI_MASTER_ACKACT_bm | TWI_MASTER_CMD_STOP_gc;
transfer.status = STATUS_OK;
}
} else {
/* Issue STOP and buffer overflow condition. */
bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
transfer.status = ERR_NO_MEMORY;
}
}
/**
* \internal
*
* \brief Common TWI master interrupt service routine.
*
* Check current status and calls the appropriate handler.
*/
static void twim_interrupt_handler(void)
{
uint8_t const master_status = transfer.bus->MASTER.STATUS;
if (master_status & TWI_MASTER_ARBLOST_bm) {
transfer.bus->MASTER.STATUS = master_status | TWI_MASTER_ARBLOST_bm;
transfer.bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
transfer.status = ERR_BUSY;
} else if ((master_status & TWI_MASTER_BUSERR_bm) ||
(master_status & TWI_MASTER_RXACK_bm)) {
transfer.bus->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
transfer.status = ERR_IO_ERROR;
} else if (master_status & TWI_MASTER_WIF_bm) {
twim_write_handler();
} else if (master_status & TWI_MASTER_RIF_bm) {
twim_read_handler();
} else {
transfer.status = ERR_PROTOCOL;
}
}
/**
* \brief Initialize the twi master module
*
* \param twi Base address of the TWI (i.e. &TWIC).
* \param *opt Options for initializing the twi module
* (see \ref twi_options_t)
* \retval STATUS_OK Transaction is successful
* \retval ERR_INVALID_ARG Invalid arguments in \c opt.
*/
status_code_t twi_master_init(TWI_t * twi,
const twi_options_t * opt)
{
uint8_t const ctrla =
CONF_TWIM_INTLVL | TWI_MASTER_RIEN_bm | TWI_MASTER_WIEN_bm |
TWI_MASTER_ENABLE_bm;
twi->MASTER.BAUD = opt->speed_reg;
twi->MASTER.CTRLA = ctrla;
twi->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc;
transfer.locked = false;
transfer.status = STATUS_OK;
/* Enable configured PMIC interrupt level. */
PMIC.CTRL |= CONF_PMIC_INTLVL;
cpu_irq_enable();
return STATUS_OK;
}
/**
* \brief Perform a TWI master write or read transfer.
*
* This function is a TWI Master write or read transaction.
*
* \param twi Base address of the TWI (i.e. &TWI_t).
* \param package Package information and data
* (see \ref twi_package_t)
* \param read Selects the transfer direction
*
* \return status_code_t
* - STATUS_OK if the transfer completes
* - ERR_BUSY to indicate an unavailable bus
* - ERR_IO_ERROR to indicate a bus transaction error
* - ERR_NO_MEMORY to indicate buffer errors
* - ERR_PROTOCOL to indicate an unexpected bus state
* - ERR_INVALID_ARG to indicate invalid arguments.
*/
status_code_t twi_master_transfer(TWI_t * twi,
const twi_package_t * package,
bool read)
{
/* Do a sanity check on the arguments. */
if ((twi == NULL) || (package == NULL)) {
return ERR_INVALID_ARG;
}
/* Initiate a transaction when the bus is ready. */
status_code_t status = twim_acquire(package->no_wait);
if (STATUS_OK == status) {
transfer.bus = (TWI_t *) twi;
transfer.pkg = (twi_package_t *) package;
transfer.addr_count = 0;
transfer.data_count = 0;
transfer.read = read;
uint8_t const chip = (package->chip) << 1;
if (package->addr_length || (false == read)) {
transfer.bus->MASTER.ADDR = chip;
} else if (read) {
transfer.bus->MASTER.ADDR = chip | 0x01;
}
status = twim_release();
}
return status;
}
ports/xplained/ASF/xmega/drivers/twi/twim.h
+168
View File
@@ -0,0 +1,168 @@
/**
* \file
*
* \brief TWI driver for AVR.
*
* This file defines a useful set of functions for the TWI interface on AVR
* devices.
*
* Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _TWIM_H_
#define _TWIM_H_
/**
* \defgroup group_xmega_drivers_twi_twim TWI Master
*
* \ingroup group_xmega_drivers_twi
*
* \{
*/
#ifdef __cplusplus
extern "C"
{
#endif
#include <compiler.h>
#include <status_codes.h>
#include "conf_twim.h"
#include "twi_common.h"
/*! \brief Error Codes for the Module
*
* \deprecated
* This definition is provided for compatibility with existing ASF example
* applications. This module uses the \ref status_code_t values that will
* replace module-specific error codes in ASF drivers.
*/
#define TWI_SUCCESS (STATUS_OK)
/*! Baud register setting calculation. Formula described in datasheet. */
#define TWI_BAUD(F_SYS, F_TWI) ((F_SYS / (2 * F_TWI)) - 5)
/*! \brief Initialize the twi master module
*
* \param twi Base address of the TWI (i.e. &TWIC).
* \param *opt Options for initializing the twi module
* (see \ref twi_options_t)
* \retval STATUS_OK Transaction is successful
* \retval ERR_INVALID_ARG Invalid arguments in \c opt.
*/
status_code_t twi_master_init (TWI_t * twi, const twi_options_t * opt);
/*! \brief Perform a TWI master write or read transfer.
*
* This function is a TWI Master write or read transaction.
*
* \param twi Base address of the TWI (i.e. &TWI_t).
* \param package Package information and data
* (see \ref twi_package_t)
* \param read Selects the transfer direction
*
* \return status_code_t
* - STATUS_OK if the transfer completes
* - ERR_BUSY to indicate an unavailable bus
* - ERR_IO_ERROR to indicate a bus transaction error
* - ERR_NO_MEMORY to indicate buffer errors
* - ERR_PROTOCOL to indicate an unexpected bus state
* - ERR_INVALID_ARG to indicate invalid arguments.
*/
status_code_t twi_master_transfer (TWI_t * twi,
const twi_package_t * package,
bool read);
/*! \brief Read multiple bytes from a TWI compatible slave device
*
* \param twi Base address of the TWI (i.e. &TWI_t).
* \param package Package information and data
* (see \ref twi_package_t)
* \return STATUS_OK If all bytes were read, error code otherwise
*/
static inline status_code_t twi_master_read (TWI_t * twi,
const twi_package_t * package)
{
return twi_master_transfer (twi, package, true);
}
/*! \brief Write multiple bytes to a TWI compatible slave device
*
* \param twi Base address of the TWI (i.e. &TWI_t).
* \param package Package information and data
* (see \ref twi_package_t)
* \return STATUS_OK If all bytes were written, error code otherwise
*/
static inline status_code_t twi_master_write (TWI_t * twi,
const twi_package_t * package)
{
return twi_master_transfer (twi, package, false);
}
/*! \brief Enable Master Mode of the TWI.
*
* \param twi Base address of the TWI instance.
*/
static inline void twi_master_enable (TWI_t * twi)
{
twi->MASTER.CTRLA |= TWI_MASTER_ENABLE_bm;
}
/*! \brief Disable Master Mode of the TWI.
*
* \param twi Base address of the TWI instance.
*/
static inline void twi_master_disable (TWI_t * twi)
{
twi->MASTER.CTRLA &= (~TWI_MASTER_ENABLE_bm);
}
#ifdef __cplusplus
}
#endif
/**
* \}
*/
#endif // _TWIM_H_
ports/xplained/ASF/xmega/drivers/twi/twis.c
+330
View File
@@ -0,0 +1,330 @@
/**
* \file *********************************************************************
*
* \brief
* XMEGA TWI slave driver source file.
*
* This file contains the function implementations the XMEGA TWI slave
* driver.
*
* The driver is not intended for size and/or speed critical code, since
* most functions are just a few lines of code, and the function call
* overhead would decrease code performance. The driver is intended for
* rapid prototyping and documentation purposes for getting started with
* the XMEGA TWI slave module.
*
* For size and/or speed critical code, it is recommended to copy the
* function contents directly into your application instead of making
* a function call.
*
* Several functions use the following construct:
* "some_register = ... | (some_parameter ? SOME_BIT_bm : 0) | ..."
* Although the use of the ternary operator ( if ? then : else ) is
* discouraged, in some occasions the operator makes it possible to write
* pretty clean and neat code. In this driver, the construct is used to
* set or not set a configuration bit based on a boolean input parameter,
* such as the "some_parameter" in the example above.
*
* \par Application note:
* AVR1308: Using the XMEGA TWI
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* Atmel Corporation: http://www.atmel.com \n
*
* $Revision: 2660 $
* $Date: 2009-08-11 12:28:58 +0200 (Tue, 11 Aug 2009) $ \n
*
* Copyright (c) 2008 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*****************************************************************************/
#include "twis.h"
/*! \brief Initalizes TWI slave driver structure.
*
* Initialize the instance of the TWI Slave and set the appropriate values.
*
* \param twi The TWI_Slave_t struct instance.
* \param module Pointer to the TWI module.
* \param processDataFunction Pointer to the function that handles incoming data.
*/
void TWI_SlaveInitializeDriver(TWI_Slave_t * twi,
TWI_t * module,
void (*processDataFunction) (void))
{
twi->interface = module;
twi->Process_Data = processDataFunction;
twi->bytesReceived = 0;
twi->bytesSent = 0;
twi->status = TWIS_STATUS_READY;
twi->result = TWIS_RESULT_UNKNOWN;
twi->abort = false;
}
/*! \brief Initialize the TWI module.
*
* Enables interrupts on address recognition and data available.
* Remember to enable interrupts globally from the main application.
*
* \param twi The TWI_Slave_t struct instance.
* \param address Slave address for this module.
* \param intLevel Interrupt level for the TWI slave interrupt handler.
*/
void TWI_SlaveInitializeModule(TWI_Slave_t * twi,
uint8_t address,
TWI_SLAVE_INTLVL_t intLevel)
{
twi->interface->SLAVE.CTRLA =
intLevel | TWI_SLAVE_DIEN_bm | TWI_SLAVE_APIEN_bm |
TWI_SLAVE_ENABLE_bm;
twi->interface->SLAVE.ADDR = (address << 1);
}
/*! \brief Common TWI slave interrupt service routine.
*
* Handles all TWI transactions and responses to address match, data reception,
* data transmission, bus error and data collision.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveInterruptHandler(TWI_Slave_t * twi)
{
uint8_t currentStatus = twi->interface->SLAVE.STATUS;
/* If bus error. */
if (currentStatus & TWI_SLAVE_BUSERR_bm) {
twi->bytesReceived = 0;
twi->bytesSent = 0;
twi->result = TWIS_RESULT_BUS_ERROR;
twi->status = TWIS_STATUS_READY;
}
/* If transmit collision. */
else if (currentStatus & TWI_SLAVE_COLL_bm) {
twi->bytesReceived = 0;
twi->bytesSent = 0;
twi->result = TWIS_RESULT_TRANSMIT_COLLISION;
twi->status = TWIS_STATUS_READY;
}
/* If address match. */
else if ((currentStatus & TWI_SLAVE_APIF_bm) &&
(currentStatus & TWI_SLAVE_AP_bm)) {
TWI_SlaveAddressMatchHandler(twi);
}
/* If stop (only enabled through slave read transaction). */
else if (currentStatus & TWI_SLAVE_APIF_bm) {
TWI_SlaveStopHandler(twi);
}
/* If data interrupt. */
else if (currentStatus & TWI_SLAVE_DIF_bm) {
TWI_SlaveDataHandler(twi);
}
/* If unexpected state. */
else {
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_FAIL);
}
}
/*! \brief TWI address match interrupt handler.
*
* Prepares TWI module for transaction when an address match occurs.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveAddressMatchHandler(TWI_Slave_t * twi)
{
/* If application signalling need to abort (error occured). */
if (twi->abort) {
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_COMPTRANS_gc;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_ABORTED);
twi->abort = false;
} else {
twi->status = TWIS_STATUS_BUSY;
twi->result = TWIS_RESULT_UNKNOWN;
/* Disable stop interrupt. */
uint8_t currentCtrlA = twi->interface->SLAVE.CTRLA;
twi->interface->SLAVE.CTRLA = currentCtrlA & ~TWI_SLAVE_PIEN_bm;
twi->bytesReceived = 0;
twi->bytesSent = 0;
/* Send ACK, wait for data interrupt. */
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_RESPONSE_gc;
}
}
/*! \brief TWI stop condition interrupt handler.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveStopHandler(TWI_Slave_t * twi)
{
/* Disable stop interrupt. */
uint8_t currentCtrlA = twi->interface->SLAVE.CTRLA;
twi->interface->SLAVE.CTRLA = currentCtrlA & ~TWI_SLAVE_PIEN_bm;
/* Clear APIF, according to flowchart don't ACK or NACK */
uint8_t currentStatus = twi->interface->SLAVE.STATUS;
twi->interface->SLAVE.STATUS = currentStatus | TWI_SLAVE_APIF_bm;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_OK);
}
/*! \brief TWI data interrupt handler.
*
* Calls the appropriate slave read or write handler.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveDataHandler(TWI_Slave_t * twi)
{
if (twi->interface->SLAVE.STATUS & TWI_SLAVE_DIR_bm) {
TWI_SlaveWriteHandler(twi);
} else {
TWI_SlaveReadHandler(twi);
}
}
/*! \brief TWI slave read interrupt handler.
*
* Handles TWI slave read transactions and responses.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveReadHandler(TWI_Slave_t * twi)
{
/* Enable stop interrupt. */
uint8_t currentCtrlA = twi->interface->SLAVE.CTRLA;
twi->interface->SLAVE.CTRLA = currentCtrlA | TWI_SLAVE_PIEN_bm;
/* If free space in buffer. */
if (twi->bytesReceived < TWIS_RECEIVE_BUFFER_SIZE) {
/* Fetch data */
uint8_t data = twi->interface->SLAVE.DATA;
twi->receivedData[twi->bytesReceived] = data;
/* Process data. */
twi->Process_Data();
twi->bytesReceived++;
/* If application signalling need to abort (error occured),
* complete transaction and wait for next START. Otherwise
* send ACK and wait for data interrupt.
*/
if (twi->abort) {
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_COMPTRANS_gc;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_ABORTED);
twi->abort = false;
} else {
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_RESPONSE_gc;
}
}
/* If buffer overflow, send NACK and wait for next START. Set
* result buffer overflow.
*/
else {
twi->interface->SLAVE.CTRLB =
TWI_SLAVE_ACKACT_bm | TWI_SLAVE_CMD_COMPTRANS_gc;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_BUFFER_OVERFLOW);
}
}
/*! \brief TWI slave write interrupt handler.
*
* Handles TWI slave write transactions and responses.
*
* \param twi The TWI_Slave_t struct instance.
*/
void TWI_SlaveWriteHandler(TWI_Slave_t * twi)
{
/* If NACK, slave write transaction finished. */
if ((twi->bytesSent > 0) &&
(twi->interface->SLAVE.STATUS & TWI_SLAVE_RXACK_bm)) {
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_COMPTRANS_gc;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_OK);
}
/* If ACK, master expects more data. */
else {
if (twi->bytesSent < TWIS_SEND_BUFFER_SIZE) {
uint8_t data = twi->sendData[twi->bytesSent];
twi->interface->SLAVE.DATA = data;
twi->bytesSent++;
/* Send data, wait for data interrupt. */
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_RESPONSE_gc;
}
/* If buffer overflow. */
else {
twi->interface->SLAVE.CTRLB = TWI_SLAVE_CMD_COMPTRANS_gc;
TWI_SlaveTransactionFinished(twi, TWIS_RESULT_BUFFER_OVERFLOW);
}
}
}
/*! \brief TWI transaction finished function.
*
* Prepares module for new transaction.
*
* \param twi The TWI_Slave_t struct instance.
* \param result The result of the transaction.
*/
void TWI_SlaveTransactionFinished(TWI_Slave_t * twi,
uint8_t result)
{
twi->result = result;
twi->status = TWIS_STATUS_READY;
}
ports/xplained/ASF/xmega/drivers/twi/twis.h
+179
View File
@@ -0,0 +1,179 @@
/**
* \file *********************************************************************
*
* \brief XMEGA TWI slave driver header file.
*
* This file contains the function prototypes and enumerator definitions
* for various configuration parameters for the XMEGA TWI slave driver.
*
* The driver is not intended for size and/or speed critical code, since
* most functions are just a few lines of code, and the function call
* overhead would decrease code performance. The driver is intended for
* rapid prototyping and documentation purposes for getting started with
* the XMEGA TWI slave module.
*
* For size and/or speed critical code, it is recommended to copy the
* function contents directly into your application instead of making
* a function call.
*
* \par Application note:
* AVR1307: Using the XMEGA TWI
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* Atmel Corporation: http://www.atmel.com \n
*
* $Revision: 1569 $
* $Date: 2008-04-22 13:03:43 +0200 (Tue, 22 Apr 2008) $ \n
*
* Copyright (c) 2008 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*****************************************************************************/
#ifndef TWIS_H
#define TWIS_H
/**
* \defgroup group_xmega_drivers_twi_twis TWI Slave
*
* \ingroup group_xmega_drivers_twi
*
* \{
*/
#include "compiler.h"
#include "twi_common.h"
/*! Baud register setting calculation. Formula described in datasheet. */
#define TWI_BAUD(F_SYS, F_TWI) ((F_SYS / (2 * F_TWI)) - 5)
/* Transaction status defines.*/
#define TWIS_STATUS_READY 0
#define TWIS_STATUS_BUSY 1
/* Transaction result enumeration */
typedef enum TWIS_RESULT_enum
{
TWIS_RESULT_UNKNOWN = (0x00 << 0),
TWIS_RESULT_OK = (0x01 << 0),
TWIS_RESULT_BUFFER_OVERFLOW = (0x02 << 0),
TWIS_RESULT_TRANSMIT_COLLISION = (0x03 << 0),
TWIS_RESULT_BUS_ERROR = (0x04 << 0),
TWIS_RESULT_FAIL = (0x05 << 0),
TWIS_RESULT_ABORTED = (0x06 << 0),
}
TWIS_RESULT_t;
/* Buffer size defines. */
#define TWIS_RECEIVE_BUFFER_SIZE 8
#define TWIS_SEND_BUFFER_SIZE 8
/*! \brief TWI slave driver struct.
*
* TWI slave struct. Holds pointer to TWI module and data processing routine,
* buffers and necessary variables.
*/
typedef struct TWI_Slave
{
TWI_t *interface; /*!< Pointer to what interface to use */
void (*Process_Data) (void); /*!< Pointer to process data function */
register8_t receivedData[TWIS_RECEIVE_BUFFER_SIZE]; /*!< Read data */
register8_t sendData[TWIS_SEND_BUFFER_SIZE]; /*!< Data to write */
register8_t bytesReceived; /*!< Number of bytes received */
register8_t bytesSent; /*!< Number of bytes sent */
register8_t status; /*!< Status of transaction */
register8_t result; /*!< Result of transaction */
bool abort; /*!< Strobe to abort */
}
TWI_Slave_t;
void TWI_SlaveInitializeDriver (TWI_Slave_t * twi,
TWI_t * module,
void (*processDataFunction) (void));
void TWI_SlaveInitializeModule (TWI_Slave_t * twi,
uint8_t address, TWI_SLAVE_INTLVL_t intLevel);
void TWI_SlaveInterruptHandler (TWI_Slave_t * twi);
void TWI_SlaveAddressMatchHandler (TWI_Slave_t * twi);
void TWI_SlaveStopHandler (TWI_Slave_t * twi);
void TWI_SlaveDataHandler (TWI_Slave_t * twi);
void TWI_SlaveReadHandler (TWI_Slave_t * twi);
void TWI_SlaveWriteHandler (TWI_Slave_t * twi);
void TWI_SlaveTransactionFinished (TWI_Slave_t * twi, uint8_t result);
/*! TWI slave interrupt service routine.
*
* Interrupt service routine for the TWI slave. Copy the interrupt vector
* into your code if needed.
*
ISR(TWIC_TWIS_vect)
{
TWI_SlaveInterruptHandler(&twiSlaveC);
}
*
*/
/*! \brief Enable Slave Mode of the TWI.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_slave_enable (TWI_t * twi)
{
twi->SLAVE.CTRLA |= TWI_SLAVE_ENABLE_bm;
}
/*! \brief Disable Slave Mode of the TWI.
*
* \param twi Base address of the TWI instance.
*/
static inline void
twi_slave_disable (TWI_t * twi)
{
twi->SLAVE.CTRLA &= (~TWI_SLAVE_ENABLE_bm);
}
/**
* \}
*/
#endif /* TWIS_H */
ports/xplained/ASF/xmega/drivers/usart/usart.c
+464
View File
@@ -0,0 +1,464 @@
/**
* \file
*
* \brief USART driver for AVR XMEGA.
*
* Copyright (c) 2009-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <stdint.h>
#include "compiler.h"
#include "usart.h"
#include "sysclk.h"
#include "ioport.h"
#include "status_codes.h"
/*
* Fix XMEGA header files
* USART.CTRLC bit masks and bit positions
*/
#ifndef USART_UCPHA_bm
# define USART_UCPHA_bm 0x02
#endif
#ifndef USART_DORD_bm
# define USART_DORD_bm 0x04
#endif
/**
* \brief Initialize USART in RS232 mode.
*
* This function initializes the USART module in RS232 mode using the
* usart_rs232_options_t configuration structure and CPU frequency.
*
* \param usart The USART module.
* \param opt The RS232 configuration option.
*
* \retval true if the initialization was successfull
* \retval false if the initialization failed (error in baud rate calculation)
*/
bool usart_init_rs232(USART_t *usart, const usart_rs232_options_t *opt)
{
bool result;
sysclk_enable_peripheral_clock(usart);
usart_set_mode(usart, USART_CMODE_ASYNCHRONOUS_gc);
usart_format_set(usart, opt->charlength, opt->paritytype,
opt->stopbits);
result = usart_set_baudrate(usart, opt->baudrate, sysclk_get_per_hz());
usart_tx_enable(usart);
usart_rx_enable(usart);
return result;
}
/**
* \brief Initialize USART in SPI master mode.
*
* This function initializes the USART module in SPI master mode using the
* usart_spi_options_t configuration structure and CPU frequency.
*
* \param usart The USART module.
* \param opt The RS232 configuration option.
*/
void usart_init_spi(USART_t *usart, const usart_spi_options_t *opt)
{
ioport_pin_t sck_pin;
bool invert_sck;
sysclk_enable_peripheral_clock(usart);
usart_rx_disable(usart);
/* configure Clock polarity using INVEN bit of the correct SCK I/O port **/
invert_sck = (opt->spimode == 2) || (opt->spimode == 3);
UNUSED(invert_sck);
#ifdef USARTC0
if ((uint16_t)usart == (uint16_t)&USARTC0) {
# ifdef PORT_USART0_bm
if (PORTC.REMAP & PORT_USART0_bm) {
sck_pin = IOPORT_CREATE_PIN(PORTC, 5);
} else {
sck_pin = IOPORT_CREATE_PIN(PORTC, 1);
}
# else
sck_pin = IOPORT_CREATE_PIN(PORTC, 1);
# endif
}
#endif
#ifdef USARTC1
if ((uint16_t)usart == (uint16_t)&USARTC1) {
sck_pin = IOPORT_CREATE_PIN(PORTC, 5);
}
#endif
#ifdef USARTD0
if ((uint16_t)usart == (uint16_t)&USARTD0) {
# ifdef PORT_USART0_bm
if (PORTD.REMAP & PORT_USART0_bm) {
sck_pin = IOPORT_CREATE_PIN(PORTD, 5);
} else {
sck_pin = IOPORT_CREATE_PIN(PORTD, 1);
}
# else
sck_pin = IOPORT_CREATE_PIN(PORTD, 1);
# endif
}
#endif
#ifdef USARTD1
if ((uint16_t)usart == (uint16_t)&USARTD1) {
sck_pin = IOPORT_CREATE_PIN(PORTD, 5);
}
#endif
#ifdef USARTE0
if ((uint16_t)usart == (uint16_t)&USARTE0) {
# ifdef PORT_USART0_bm
if(PORTE.REMAP & PORT_USART0_bm) {
sck_pin = IOPORT_CREATE_PIN(PORTE, 5);
} else {
sck_pin = IOPORT_CREATE_PIN(PORTE, 1);
}
# else
sck_pin = IOPORT_CREATE_PIN(PORTE, 1);
# endif
}
#endif
#ifdef USARTE1
if ((uint16_t)usart == (uint16_t)&USARTE1) {
sck_pin = IOPORT_CREATE_PIN(PORTE, 5);
}
#endif
#ifdef USARTF0
if ((uint16_t)usart == (uint16_t)&USARTF0) {
# ifdef PORT_USART0_bm
if(PORTF.REMAP & PORT_USART0_bm) {
sck_pin = IOPORT_CREATE_PIN(PORTF, 5);
} else {
sck_pin = IOPORT_CREATE_PIN(PORTF, 1);
}
# else
sck_pin = IOPORT_CREATE_PIN(PORTF, 1);
# endif
}
#endif
#ifdef USARTF1
if ((uint16_t)usart == (uint16_t)&USARTF1) {
sck_pin = IOPORT_CREATE_PIN(PORTF, 5);
}
#endif
/* Configure the USART output pin */
ioport_set_pin_dir(sck_pin, IOPORT_DIR_OUTPUT);
ioport_set_pin_mode(sck_pin,
IOPORT_MODE_TOTEM | (invert_sck? IOPORT_MODE_INVERT_PIN : 0));
ioport_set_pin_level(sck_pin, IOPORT_PIN_LEVEL_HIGH);
usart_set_mode(usart, USART_CMODE_MSPI_gc);
if (opt->spimode == 1 || opt->spimode == 3) {
usart->CTRLC |= USART_UCPHA_bm;
} else {
usart->CTRLC &= ~USART_UCPHA_bm;
}
if (opt->data_order) {
(usart)->CTRLC |= USART_DORD_bm;
} else {
(usart)->CTRLC &= ~USART_DORD_bm;
}
usart_spi_set_baudrate(usart, opt->baudrate, sysclk_get_per_hz());
usart_tx_enable(usart);
usart_rx_enable(usart);
}
/**
* \brief Send a data with the USART module
*
* This function outputs a data using the USART module.
*
* \param usart The USART module.
* \param c The data to send.
*
* \return STATUS_OK
*/
status_code_t usart_putchar(USART_t *usart, uint8_t c)
{
while (usart_data_register_is_empty(usart) == false) {
}
(usart)->DATA = c;
return STATUS_OK;
}
/**
* \brief Receive a data with the USART module
*
* This function returns the received data from the USART module.
*
* \param usart The USART module.
*
* \return The received data.
*/
uint8_t usart_getchar(USART_t *usart)
{
while (usart_rx_is_complete(usart) == false) {
}
return ((uint8_t)(usart)->DATA);
}
/**
* \brief Get the offset for lookup in the baudrate table
*
* \param baud The requested baudrate
*
* \return The baudrate offset in PROGMEM table
* \retval USART_BAUD_UNDEFINED for baudrates not in lookup table
*/
static uint8_t usart_get_baud_offset(uint32_t baud)
{
switch (baud) {
case 1200:
return (uint8_t)USART_BAUD_1200;
case 2400:
return (uint8_t)USART_BAUD_2400;
case 4800:
return (uint8_t)USART_BAUD_4800;
case 9600:
return (uint8_t)USART_BAUD_9600;
case 19200:
return (uint8_t)USART_BAUD_19200;
case 38400:
return (uint8_t)USART_BAUD_38400;
case 57600:
return (uint8_t)USART_BAUD_57600;
default:
return (uint8_t)USART_BAUD_UNDEFINED;
}
}
/**
* \brief Set the baudrate by setting the BSEL and BSCALE values in the USART
*
* This function sets the selected BSEL and BSCALE value in the BAUDCTRL
* registers with BSCALE 0. For calculation options, see table 21-1 in XMEGA A
* manual.
*
* \param usart The USART module.
* \param bsel Calculated BSEL value.
* \param bscale Calculated BSEL value.
*
*/
void usart_set_bsel_bscale_value(USART_t *usart, uint16_t bsel, uint8_t bscale)
{
(usart)->BAUDCTRLA = (uint8_t)(bsel);
(usart)->BAUDCTRLB = (uint8_t)(((bsel >> 8) & 0X0F) | (bscale << 4));
}
/**
* \brief Set the baudrate using precalculated BAUDCTRL values from PROGMEM
*
* \note This function only works for cpu_hz 2Mhz or 32Mhz and baudrate values
* 1200, 2400, 4800, 9600, 19200, 38400 and 57600.
*
* \param usart The USART module.
* \param baud The baudrate.
* \param cpu_hz The CPU frequency.
*
*/
void usart_set_baudrate_precalculated(USART_t *usart, uint32_t baud,
uint32_t cpu_hz)
{
uint8_t baud_offset;
uint16_t baudctrl = 0;
baud_offset = usart_get_baud_offset(baud);
if (cpu_hz == 2000000UL) {
baudctrl = PROGMEM_READ_WORD(baudctrl_2mhz + baud_offset);
} else if (cpu_hz == 32000000UL) {
baudctrl = PROGMEM_READ_WORD(baudctrl_32mhz + baud_offset);
} else {
/* Error, system clock speed or USART baud rate is not supported
* by the look-up table */
Assert(false);
}
if (baud_offset != USART_BAUD_UNDEFINED) {
(usart)->BAUDCTRLB = (uint8_t)((uint16_t)baudctrl);
(usart)->BAUDCTRLA = (uint8_t)((uint16_t)baudctrl >> 8);
}
}
/**
* \brief Set the baudrate value in the USART module
*
* This function sets the baudrate register with scaling regarding the CPU
* frequency and makes sure the baud rate is supported by the hardware.
* The function can be used if you don't want to calculate the settings
* yourself or changes to baudrate at runtime is required.
*
* \param usart The USART module.
* \param baud The baudrate.
* \param cpu_hz The CPU frequency.
*
* \retval true if the hardware supports the baud rate
* \retval false if the hardware does not support the baud rate (i.e. it's
* either too high or too low.)
*/
bool usart_set_baudrate(USART_t *usart, uint32_t baud, uint32_t cpu_hz)
{
int8_t exp;
uint32_t div;
uint32_t limit;
uint32_t ratio;
uint32_t min_rate;
uint32_t max_rate;
/*
* Check if the hardware supports the given baud rate
*/
/* 8 = (2^0) * 8 * (2^0) = (2^BSCALE_MIN) * 8 * (BSEL_MIN) */
max_rate = cpu_hz / 8;
/* 4194304 = (2^7) * 8 * (2^12) = (2^BSCALE_MAX) * 8 * (BSEL_MAX+1) */
min_rate = cpu_hz / 4194304;
if (!((usart)->CTRLB & USART_CLK2X_bm)) {
max_rate /= 2;
min_rate /= 2;
}
if ((baud > max_rate) || (baud < min_rate)) {
return false;
}
/* Check if double speed is enabled. */
if (!((usart)->CTRLB & USART_CLK2X_bm)) {
baud *= 2;
}
/* Find the lowest possible exponent. */
limit = 0xfffU >> 4;
ratio = cpu_hz / baud;
for (exp = -7; exp < 7; exp++) {
if (ratio < limit) {
break;
}
limit <<= 1;
if (exp < -3) {
limit |= 1;
}
}
/*
* Depending on the value of exp, scale either the input frequency or
* the target baud rate. By always scaling upwards, we never introduce
* any additional inaccuracy.
*
* We are including the final divide-by-8 (aka. right-shift-by-3) in
* this operation as it ensures that we never exceeed 2**32 at any
* point.
*
* The formula for calculating BSEL is slightly different when exp is
* negative than it is when exp is positive.
*/
if (exp < 0) {
/* We are supposed to subtract 1, then apply BSCALE. We want to
* apply BSCALE first, so we need to turn everything inside the
* parenthesis into a single fractional expression.
*/
cpu_hz -= 8 * baud;
/* If we end up with a left-shift after taking the final
* divide-by-8 into account, do the shift before the divide.
* Otherwise, left-shift the denominator instead (effectively
* resulting in an overall right shift.)
*/
if (exp <= -3) {
div = ((cpu_hz << (-exp - 3)) + baud / 2) / baud;
} else {
baud <<= exp + 3;
div = (cpu_hz + baud / 2) / baud;
}
} else {
/* We will always do a right shift in this case, but we need to
* shift three extra positions because of the divide-by-8.
*/
baud <<= exp + 3;
div = (cpu_hz + baud / 2) / baud - 1;
}
(usart)->BAUDCTRLB = (uint8_t)(((div >> 8) & 0X0F) | (exp << 4));
(usart)->BAUDCTRLA = (uint8_t)div;
return true;
}
/**
* \brief Set the baudrate value in the USART_SPI module
*
* This function sets the baudrate register regarding the CPU frequency.
*
* \param usart The USART(SPI) module.
* \param baud The baudrate.
* \param cpu_hz The CPU frequency.
*/
void usart_spi_set_baudrate(USART_t *usart, uint32_t baud, uint32_t cpu_hz)
{
uint16_t bsel_value;
/* Check if baudrate is less than the maximim limit specified in
* datasheet */
if (baud < (cpu_hz / 2)) {
bsel_value = (cpu_hz / (baud * 2)) - 1;
} else {
/* If baudrate is not within the specfication in datasheet,
* assign maximum baudrate possible for the current CPU frequency */
bsel_value = 0;
}
(usart)->BAUDCTRLB = (uint8_t)((~USART_BSCALE_gm) & (bsel_value >> 8));
(usart)->BAUDCTRLA = (uint8_t)(bsel_value);
}
ports/xplained/ASF/xmega/drivers/usart/usart.h
+556
View File
@@ -0,0 +1,556 @@
/**
* \file
*
* \brief USART driver for AVR XMEGA.
*
* This file contains basic functions for the AVR XMEGA USART, with support for all
* modes, settings and clock speeds.
*
* Copyright (c) 2009-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _USART_H_
#define _USART_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "compiler.h"
#include "pmic.h"
#include "status_codes.h"
/**
* \defgroup usart_group USART module (USART)
*
* See \ref xmega_usart_quickstart.
*
* This is a driver for configuring, enabling, disabling and use of the on-chip
* USART.
*
* \section dependencies Dependencies
*
* The USART module depends on the following modules:
* - \ref sysclk_group for peripheral clock control.
* - \ref port_driver_group for peripheral io port control.
*
* @{
*/
//! Offset in lookup table for baudrate 1200
#define USART_BAUD_1200 0x00
//! Offset in lookup table for baudrate 2400
#define USART_BAUD_2400 0x01
//! Offset in lookup table for baudrate 4800
#define USART_BAUD_4800 0x02
//! Offset in lookup table for baudrate 9600
#define USART_BAUD_9600 0x03
//! Offset in lookup table for baudrate 19200
#define USART_BAUD_19200 0x04
//! Offset in lookup table for baudrate 38400
#define USART_BAUD_38400 0x05
//! Offset in lookup table for baudrate 57600
#define USART_BAUD_57600 0x06
//! Baudrate not in lookup table
#define USART_BAUD_UNDEFINED 0xFF
//! Lookup table containing baudctrl values for CPU frequency 2 Mhz
static PROGMEM_DECLARE(uint16_t, baudctrl_2mhz[]) = {
0xE5BC, // Baud: 1200
0xC5AC, // Baud: 2400
0x859C, // Baud: 4800
0x0396, // Baud: 9600
0xC192, // Baud: 19200
0x2191, // Baud: 38400
0x9690, // Baud: 57600
};
//! Lookup table containing baudctrl values for CPU frequency 32 Mhz
static PROGMEM_DECLARE(uint16_t, baudctrl_32mhz[]) = {
0x031D, // Baud: 1200
0x01ED, // Baud: 2400
0xFDDC, // Baud: 4800
0xF5CC, // Baud: 9600
0xE5BC, // Baud: 19200
0xC5AC, // Baud: 38400
0x6EA8, // Baud: 57600
};
//! @}
//! Input parameters when initializing RS232 and similar modes.
typedef struct usart_rs232_options {
//! Set baud rate of the USART (unused in slave modes).
uint32_t baudrate;
//! Number of bits to transmit as a character (5 to 9).
USART_CHSIZE_t charlength;
//! Parity type: USART_PMODE_DISABLED_gc, USART_PMODE_EVEN_gc,
//! USART_PMODE_ODD_gc.
USART_PMODE_t paritytype;
//! Number of stop bits between two characters:
//! true: 2 stop bits
//! false: 1 stop bit
bool stopbits;
} usart_rs232_options_t;
//! Input parameters when initializing SPI master mode.
typedef struct usart_spi_options {
//! Set baud rate of the USART in SPI mode.
uint32_t baudrate;
//! SPI transmission mode.
uint8_t spimode;
uint8_t data_order;
} usart_spi_options_t;
//! USART interrupt levels
enum usart_int_level_t {
USART_INT_LVL_OFF = 0x00,
USART_INT_LVL_LO = 0x01,
USART_INT_LVL_MED = 0x02,
USART_INT_LVL_HI = 0x03,
};
/**
* \brief Enable USART receiver.
*
* \param usart Pointer to the USART module
*/
static inline void usart_rx_enable(USART_t *usart)
{
(usart)->CTRLB |= USART_RXEN_bm;
}
/**
* \brief Disable USART receiver.
*
* \param usart Pointer to the USART module.
*/
static inline void usart_rx_disable(USART_t *usart)
{
(usart)->CTRLB &= ~USART_RXEN_bm;
}
/**
* \brief Configure the USART frame format.
*
* Sets the frame format, Frame Size, parity mode and number of stop bits.
*
* \param usart Pointer to the USART module
* \param charSize The character size. Use USART_CHSIZE_t type.
* \param parityMode The parity Mode. Use USART_PMODE_t type.
* \param twoStopBits Enable two stop bit mode. Use bool type.
*/
static inline void usart_format_set(USART_t *usart, USART_CHSIZE_t charSize,
USART_PMODE_t parityMode, bool twoStopBits)
{
(usart)->CTRLC = (uint8_t)charSize | parityMode
| (twoStopBits ? USART_SBMODE_bm : 0);
}
/**
* \brief Enable USART transmitter.
*
* \param usart Pointer to the USART module.
*/
static inline void usart_tx_enable(USART_t *usart)
{
(usart)->CTRLB |= USART_TXEN_bm;
}
/**
* \brief Disable USART transmitter.
*
* \param usart Pointer to the USART module.
*/
static inline void usart_tx_disable(USART_t *usart)
{
(usart)->CTRLB &= ~USART_TXEN_bm;
}
/**
* \brief Set USART RXD interrupt level.
*
* Sets the interrupt level on RX Complete interrupt.
*
* \param usart Pointer to the USART module.
* \param level Interrupt level of the RXD interrupt.
*/
static inline void usart_set_rx_interrupt_level(USART_t *usart,
enum usart_int_level_t level)
{
(usart)->CTRLA = ((usart)->CTRLA & ~USART_RXCINTLVL_gm) |
(level << USART_RXCINTLVL_gp);
}
/**
* \brief Set USART TXD interrupt level.
*
* Sets the interrupt level on TX Complete interrupt.
*
* \param usart Pointer to the USART module.
* \param level Interrupt level of the TXD interrupt.
*/
static inline void usart_set_tx_interrupt_level(USART_t *usart,
enum usart_int_level_t level)
{
(usart)->CTRLA = ((usart)->CTRLA & ~USART_TXCINTLVL_gm) |
(level << USART_TXCINTLVL_gp);
}
/**
* \brief Set USART DRE interrupt level.
*
* Sets the interrupt level on Data Register interrupt.
*
* \param usart Pointer to the USART module.
* \param level Interrupt level of the DRE interrupt.
* Use USART_DREINTLVL_t type.
*/
static inline void usart_set_dre_interrupt_level(USART_t *usart,
enum usart_int_level_t level)
{
(usart)->CTRLA = ((usart)->CTRLA & ~USART_DREINTLVL_gm) |
(level << USART_DREINTLVL_gp);
}
/**
* \brief Set the mode the USART run in.
*
* Set the mode the USART run in. The default mode is asynchronous mode.
*
* \param usart Pointer to the USART module register section.
* \param usartmode Selects the USART mode. Use USART_CMODE_t type.
*
* USART modes:
* - 0x0 : Asynchronous mode.
* - 0x1 : Synchronous mode.
* - 0x2 : IrDA mode.
* - 0x3 : Master SPI mode.
*/
static inline void usart_set_mode(USART_t *usart, USART_CMODE_t usartmode)
{
(usart)->CTRLC = ((usart)->CTRLC & (~USART_CMODE_gm)) | usartmode;
}
/**
* \brief Check if data register empty flag is set.
*
* \param usart The USART module.
*/
static inline bool usart_data_register_is_empty(USART_t * usart)
{
return (usart)->STATUS & USART_DREIF_bm;
}
/**
* \brief Checks if the RX complete interrupt flag is set.
*
* Checks if the RX complete interrupt flag is set.
*
* \param usart The USART module.
*/
static inline bool usart_rx_is_complete(USART_t * usart)
{
return (usart)->STATUS & USART_RXCIF_bm;
}
/**
* \brief Checks if the TX complete interrupt flag is set.
*
* Checks if the TX complete interrupt flag is set.
*
* \param usart The USART module.
*/
static inline bool usart_tx_is_complete(USART_t * usart)
{
return (usart)->STATUS & USART_TXCIF_bm;
}
/**
* \brief Clear TX complete interrupt flag.
*
* \param usart The USART module.
*/
static inline void usart_clear_tx_complete(USART_t * usart)
{
(usart)->STATUS = USART_TXCIF_bm;
}
/**
* \brief Clear RX complete interrupt flag.
*
* \param usart The USART module.
*/
static inline void usart_clear_rx_complete(USART_t *usart)
{
(usart)->STATUS = USART_RXCIF_bm;
}
/**
* \brief Write a data to the USART data register.
*
* \param usart The USART module.
* \param txdata The data to be transmitted.
*/
static inline void usart_put(USART_t * usart, uint8_t txdata)
{
(usart)->DATA = txdata;
}
/**
* \brief Read a data to the USART data register.
*
* \param usart The USART module.
*
* \return The received data
*/
static inline uint8_t usart_get(USART_t * usart)
{
return (usart)->DATA;
}
/**
* \brief Performs a data transfer on the USART in SPI mode.
*
* \param usart The USART module.
* \param txdata The data to be transmitted.
*
* \return The received data
*/
static inline uint8_t usart_spi_transmit(USART_t * usart,
uint8_t txdata)
{
while (usart_data_register_is_empty(usart) == false);
usart_put(usart, txdata);
while (!usart_tx_is_complete(usart));
usart_clear_tx_complete(usart);
return usart_get(usart);
}
bool usart_init_rs232(USART_t *usart, const usart_rs232_options_t *opt);
void usart_init_spi(USART_t * usart, const usart_spi_options_t * opt);
status_code_t usart_putchar(USART_t * usart, uint8_t c);
uint8_t usart_getchar(USART_t * usart);
void usart_set_bsel_bscale_value(USART_t *usart, uint16_t bsel, uint8_t bscale);
void usart_set_baudrate_precalculated(USART_t *usart, uint32_t baud,
uint32_t cpu_hz);
bool usart_set_baudrate(USART_t *usart, uint32_t baud, uint32_t cpu_hz);
void usart_spi_set_baudrate(USART_t * usart, uint32_t baud, uint32_t cpu_hz);
//! @}
#ifdef __cplusplus
}
#endif
/**
* \page xmega_usart_quickstart Quick start guide for USART module
*
* This is the quick start guide for the \ref usart_group "USART module", with
* step-by-step instructions on how to configure and use the driver in a
* selection of use cases.
*
* The use cases contain several code fragments. The code fragments in the
* steps for setup can be copied into a custom initialization function, while
* the steps for usage can be copied into, e.g., the main application function.
*
* \section usart_basic_use_case Basic use case
* \section usart_use_cases USART use cases
* - \ref usart_basic_use_case
* - \subpage usart_use_case_1
*
* \section usart_basic_use_case Basic use case - transmit a character
* In this use case, the USART module is configured for:
* - Using USARTD0
* - Baudrate: 9600
* - Character length: 8 bit
* - Parity mode: Disabled
* - Stop bit: None
* - RS232 mode
*
* \section usart_basic_use_case_setup Setup steps
*
* \subsection usart_basic_use_case_setup_prereq Prerequisites
* -# \ref sysclk_group
* \subsection usart_basic_use_case_setup_code Example code
* The following configuration must be added to the project (typically to a
* conf_usart.h file, but it can also be added to your main application file.)
* \code
* #define USART_SERIAL &USARTD0
* #define USART_SERIAL_BAUDRATE 9600
* #define USART_SERIAL_CHAR_LENGTH USART_CHSIZE_8BIT_gc
* #define USART_SERIAL_PARITY USART_PMODE_DISABLED_gc
* #define USART_SERIAL_STOP_BIT false
* \endcode
*
* Add to application initialization:
* \code
* sysclk_init();
* static usart_rs232_options_t USART_SERIAL_OPTIONS = {
* .baudrate = USART_SERIAL_BAUDRATE,
* .charlength = USART_SERIAL_CHAR_LENGTH,
* .paritytype = USART_SERIAL_PARITY,
* .stopbits = USART_SERIAL_STOP_BIT
* };
* sysclk_enable_module(SYSCLK_PORT_D, PR_USART0_bm);
* usart_init_rs232(USART_SERIAL, &USART_SERIAL_OPTIONS);
* \endcode
*
* \subsection usart_basic_use_case_setup_flow Workflow
* -# Initialize system clock:
* - \code sysclk_init(); \endcode
* - \note Not always required, but since the \ref usart_group driver is
* dependent on \ref sysclk_group it is good practise to initialize
* this module.
* -# Create USART options struct:
* - \code
* static usart_rs232_options_t USART_SERIAL_OPTIONS = {
* .baudrate = USART_SERIAL_BAUDRATE,
* .charlength = USART_SERIAL_CHAR_LENGTH,
* .paritytype = USART_SERIAL_PARITY,
* .stopbits = USART_SERIAL_STOP_BIT
* };
* \endcode
* -# Enable the clock for the USART module:
* - \code sysclk_enable_module(SYSCLK_PORT_D, PR_USART0_bm); \endcode
* -# Initialize in RS232 mode:
* - \code usart_init_rs232(USART_SERIAL, &USART_SERIAL_OPTIONS);
* \endcode
*
* \section usart_basic_use_case_usage Usage steps
*
* \subsection usart_basic_use_case_usage_code Example code
* Add to application C-file:
* \code
* usart_putchar(USART_SERIAL, 'a');
* \endcode
*
* \subsection usart_basic_use_case_usage_flow Workflow
* -# Send an 'a' character via USART
* - \code usart_putchar(USART_SERIAL, 'a'); \endcode
*/
/**
* \page usart_use_case_1 USART receive character and echo back
*
* In this use case, the USART module is configured for:
* - Using USARTD0
* - Baudrate: 9600
* - Character length: 8 bit
* - Parity mode: Disabled
* - Stop bit: None
* - RS232 mode
*
* The use case waits for a received character on the configured USART and
* echoes the character back to the same USART.
*
* \section usart_use_case_1_setup Setup steps
*
* \subsection usart_use_case_1_setup_prereq Prerequisites
* -# \ref sysclk_group
*
* \subsection usart_use_case_1_setup_code Example code
* -# The following configuration must be added to the project (typically to a
* conf_usart.h file, but it can also be added to your main application file.):
* \code
* #define USART_SERIAL &USARTD0
* #define USART_SERIAL_BAUDRATE 9600
* #define USART_SERIAL_CHAR_LENGTH USART_CHSIZE_8BIT_gc
* #define USART_SERIAL_PARITY USART_PMODE_DISABLED_gc
* #define USART_SERIAL_STOP_BIT false
* \endcode
*
* A variable for the received byte must be added:
* \code uint8_t received_byte; \endcode
*
* Add to application initialization:
* \code
* sysclk_init();
* static usart_rs232_options_t USART_SERIAL_OPTIONS = {
* .baudrate = USART_SERIAL_BAUDRATE,
* .charlength = USART_SERIAL_CHAR_LENGTH,
* .paritytype = USART_SERIAL_PARITY,
* .stopbits = USART_SERIAL_STOP_BIT
* };
* sysclk_enable_module(SYSCLK_PORT_D, PR_USART0_bm);
* usart_init_rs232(USART_SERIAL, &USART_SERIAL_OPTIONS);
* \endcode
*
* \subsection usart_use_case_1_setup_flow Workflow
* -# Initialize system clock:
* - \code sysclk_init(); \endcode
* - \note Not always required, but since the \ref usart_group driver is
* dependent on \ref sysclk_group it is good practise to initialize
* this module.
* -# Create USART options struct:
* - \code
* static usart_rs232_options_t USART_SERIAL_OPTIONS = {
* .baudrate = USART_SERIAL_BAUDRATE,
* .charlength = USART_SERIAL_CHAR_LENGTH,
* .paritytype = USART_SERIAL_PARITY,
* .stopbits = USART_SERIAL_STOP_BIT
* };
* \endcode
* -# Enable the clock for the USART module:
* - \code sysclk_enable_module(SYSCLK_PORT_D, PR_USART0_bm); \endcode
* -# Initialize in RS232 mode:
* - \code usart_init_rs232(USART_SERIAL, &USART_SERIAL_OPTIONS);
* \endcode
*
* \section usart_use_case_1_usage Usage steps
*
* \subsection usart_use_case_1_usage_code Example code
* Add to, e.g., main loop in application C-file:
* \code
* received_byte = usart_getchar(USART_SERIAL);
* usart_putchar(USART_SERIAL, received_byte);
* \endcode
*
* \subsection usart_use_case_1_usage_flow Workflow
* -# Wait for reception of a character:
* - \code received_byte = usart_getchar(USART_SERIAL); \endcode
* -# Echo the character back:
* - \code usart_putchar(USART_SERIAL, received_byte); \endcode
*/
#endif // _USART_H_
ports/xplained/ASF/xmega/drivers/wdt/wdt.c
+216
View File
@@ -0,0 +1,216 @@
/**
* \file
*
* \brief AVR XMEGA WatchDog Timer driver.
*
* Copyright (c) 2011 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "compiler.h"
#include "ccp.h"
#include "wdt.h"
/*! \brief Set Watchdog timeout period.
*
* This function sets the coded field of the WDT timeout period.
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the CTRL register. Interrupts are
* automatically ignored during the change enable period. The function will
* wait for the WDT to be synchronized to the WDT clock domain before
* proceeding
*
* \param to_period WDT timeout coded period
*/
void wdt_set_timeout_period(enum wdt_timeout_period_t to_period)
{
uint8_t temp = (WDT_PER_gm & (to_period << WDT_PER_gp)) |
(WDT.CTRL & WDT_ENABLE_bm) | (1 << WDT_CEN_bp);
ccp_write_io((void *)&WDT.CTRL, temp);
wdt_wait_while_busy();
}
/*! \brief Set Watchdog window period.
*
* This function sets the coded field of the WDT closed window period.
* Note that this setting is available only if the WDT is enabled (hardware
* behaviour relayed by software).
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the WINCTRL register. Interrupts
* are automatically ignored during the change enable period. The function will
* wait for the WDT to be synchronized to the WDT clock domain before
* proceeding
*
* \param win_period Window coded period
*
* \retval true The WDT was enabled and the setting is done.
* false The WDT is disabled and the setting is discarded.
*/
bool wdt_set_window_period(enum wdt_window_period_t win_period)
{
if (!(wdt_is_enabled())) {
return false;
}
uint8_t temp = (WDT_WPER_gm & (win_period << WDT_WPER_gp)) |
(WDT.WINCTRL & WDT_WEN_bm) | (1 << WDT_WCEN_bp);
ccp_write_io((void *)&WDT.WINCTRL, temp);
wdt_wait_while_busy();
return true;
}
/*! \brief Disable Watchdog.
*
* This function disables the WDT without changing period settings.
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the CTRL register. Interrupts are
* automatically ignored during the change enable period. Disable functions
* operate asynchronously with immediate effect.
*/
void wdt_disable(void)
{
uint8_t temp = (WDT.CTRL & ~WDT_ENABLE_bm) | (1 << WDT_CEN_bp);
ccp_write_io((void *)&WDT.CTRL, temp);
}
/*! \brief Enable Watchdog.
*
* This function enables the WDT without changing period settings.
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the CTRL register. Interrupts are
* automatically ignored during the change enable period. The function will
* wait for the WDT to be synchronized to the WDT clock domain before
* proceeding
*/
void wdt_enable(void)
{
uint8_t temp = (WDT.CTRL & WDT_PER_gm) |
(1 << WDT_ENABLE_bp) | (1 << WDT_CEN_bp);
ccp_write_io((void *)&WDT.CTRL, temp);
wdt_wait_while_busy();
}
/*! \brief Disable Watchdog window mode without changing period settings.
*
* This function disables the WDT window mode without changing period settings.
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the WINCTRL register. Interrupts
* are automatically ignored during the change enable period. Disable functions
* operate asynchronously with immediate effect.
*
* \retval true The WDT was enabled and the window mode is disabled.
* false The WDT (& the window mode) is already disabled.
*/
bool wdt_disable_window_mode(void)
{
if (!(wdt_is_enabled())) {
return false;
}
uint8_t temp = (WDT.WINCTRL & ~WDT_WEN_bm) | (1 << WDT_WCEN_bp);
ccp_write_io((void *)&WDT.WINCTRL, temp);
return true;
}
/*! \brief Enable Watchdog window mode.
*
* This function enables the WDT window mode without changing period settings.
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the WINCTRL register. Interrupts
* are automatically ignored during the change enable period. The function will
* wait for the WDT to be synchronized to the WDT clock domain before
* proceeding
*
* \retval true The WDT was enabled and the setting is done.
* false The WDT is disabled and the setting is discarded.
*/
bool wdt_enable_window_mode(void)
{
if (!(wdt_is_enabled())) {
return false;
}
uint8_t temp = (WDT.WINCTRL & WDT_WPER_gm) |
(1 << WDT_WEN_bp) | (1 << WDT_WCEN_bp);
ccp_write_io((void *)&WDT.WINCTRL, temp);
wdt_wait_while_busy();
return true;
}
/*! \brief Reset MCU via Watchdog.
*
* This function generates an hardware microcontroller reset using the WDT.
*
* The function loads enables the WDT in window mode. Executing a "wdr" asm
* instruction when the windows is closed, provides a quick mcu reset.
*
*/
void wdt_reset_mcu(void)
{
uint8_t temp;
/*
* WDT enabled (minimum timeout period for max. security)
*/
temp = WDT_PER_8CLK_gc | (1 << WDT_ENABLE_bp) | (1 << WDT_CEN_bp);
ccp_write_io((void *)&WDT.CTRL, temp);
wdt_wait_while_busy();
/*
* WDT enabled (maximum window period for max. security)
*/
temp = WDT_WPER_8KCLK_gc | (1 << WDT_WEN_bp) | (1 << WDT_WCEN_bp);
ccp_write_io((void *)&WDT.WINCTRL, temp);
wdt_wait_while_busy();
/*
* WDT Reset during window => WDT generates an Hard Reset.
*/
wdt_reset();
/*
* No exit to prevent the execution of the following instructions.
*/
while (true) {
/* Wait for Watchdog reset. */
}
}
ports/xplained/ASF/xmega/drivers/wdt/wdt.h
+420
View File
@@ -0,0 +1,420 @@
/**
* \file
*
* \brief AVR XMEGA WatchDog Timer driver.
*
* Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _WDT_H_
#define _WDT_H_
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
extern "C" {
#endif
/**INDENT-ON**/
/// @endcond
#include "compiler.h"
/**
* \defgroup wdt_group Watchdog Timer (WDT)
*
* See \ref wdt_quickstart.
*
* This is a driver for configuring, enabling, disabling and use of the on-chip
* WDT.
*
* \section dependencies Dependencies
*
* The WDT module depends on the following modules:
* - \ref ccp_group for writing in a CCP-protected 8-bit I/O register.
*
* @{
*/
//! Watchdog timeout period setting
enum wdt_timeout_period_t {
//! Timeout period = 8 cycles or 8 ms @ 3.3V
WDT_TIMEOUT_PERIOD_8CLK = (0x00),
//! Timeout period = 16 cycles or 16 ms @ 3.3V
WDT_TIMEOUT_PERIOD_16CLK = (0x01),
//! Timeout period = 32 cycles or 32m s @ 3.3V
WDT_TIMEOUT_PERIOD_32CLK = (0x02),
//! Timeout period = 64 cycles or 64ms @ 3.3V
WDT_TIMEOUT_PERIOD_64CLK = (0x03),
//! Timeout period = 125 cycles or 125ms @ 3.3V
WDT_TIMEOUT_PERIOD_125CLK = (0x04),
//! 250 cycles or 250ms @ 3.3V)
WDT_TIMEOUT_PERIOD_250CLK = (0x05),
//! Timeout period = 500 cycles or 500ms @ 3.3V
WDT_TIMEOUT_PERIOD_500CLK = (0x06),
//! Timeout period =1K cycles or 1s @ 3.3V
WDT_TIMEOUT_PERIOD_1KCLK = (0x07),
//! Timeout period = 2K cycles or 2s @ 3.3V
WDT_TIMEOUT_PERIOD_2KCLK = (0x08),
//! Timeout period = 4K cycles or 4s @ 3.3V
WDT_TIMEOUT_PERIOD_4KCLK = (0x09),
//! Timeout period = 8K cycles or 8s @ 3.3V
WDT_TIMEOUT_PERIOD_8KCLK = (0x0A),
};
//! Watchdog window period setting
enum wdt_window_period_t {
//! Window period = 8 cycles or 8 ms @ 3.3V
WDT_WINDOW_PERIOD_8CLK = (0x00),
//! Window period = 16 cycles or 16 ms @ 3.3V
WDT_WINDOW_PERIOD_16CLK = (0x01),
//! Window period = 32 cycles or 32m s @ 3.3V
WDT_WINDOW_PERIOD_32CLK = (0x02),
//! Window period = 64 cycles or 64ms @ 3.3V
WDT_WINDOW_PERIOD_64CLK = (0x03),
//! Window period = 125 cycles or 125ms @ 3.3V
WDT_WINDOW_PERIOD_125CLK = (0x04),
//! 250 cycles or 250ms @ 3.3V)
WDT_WINDOW_PERIOD_250CLK = (0x05),
//! Window period = 500 cycles or 500ms @ 3.3V
WDT_WINDOW_PERIOD_500CLK = (0x06),
//! Window period =1K cycles or 1s @ 3.3V
WDT_WINDOW_PERIOD_1KCLK = (0x07),
//! Window period = 2K cycles or 2s @ 3.3V
WDT_WINDOW_PERIOD_2KCLK = (0x08),
//! Window period = 4K cycles or 4s @ 3.3V
WDT_WINDOW_PERIOD_4KCLK = (0x09),
//! Window period = 8K cycles or 8s @ 3.3V
WDT_WINDOW_PERIOD_8KCLK = (0x0A),
};
/*! \brief This macro resets (clears/refreshes) the Watchdog Timer.
*/
#if defined(__GNUC__)
#define wdt_reset() __asm__ __volatile__("wdr");
#elif defined(__ICCAVR__)
#define wdt_reset() __watchdog_reset();
#else
#error Unsupported compiler.
#endif
/*! \brief Wait until WD settings are synchronized to the WD clock domain.
*
*/
static inline void wdt_wait_while_busy(void)
{
while ((WDT.STATUS & WDT_SYNCBUSY_bm) == WDT_SYNCBUSY_bm) {
// Wait until synchronization
}
}
/*! \brief Check if the Watchdog Enable flag is set.
*
* \retval false WDT disabled
* true WDT enabled
*/
static inline bool wdt_is_enabled(void)
{
return ((WDT.CTRL & WDT_ENABLE_bm) == WDT_ENABLE_bm);
}
/*! \brief Check if the Watchdog Window mode flag is set.
*
* \retval false WDT Window disabled
* true WDT Window enabled
*/
static inline bool wdt_window_mode_is_enabled(void)
{
return ((WDT.WINCTRL & WDT_WEN_bm) == WDT_WEN_bm);
}
/*! \brief Gets the Watchdog timeout period.
*
* This function reads the value of the WDT timeout period.
*
* \retval The WDT timeout period.
*/
static inline enum wdt_timeout_period_t wdt_get_timeout_period(void)
{
return ((enum wdt_timeout_period_t)
((WDT.CTRL & WDT_PER_gm) >> WDT_PER_gp));
}
/*! \brief Gets the Watchdog window period.
*
* This function reads the value of the WDT closed window coded period.
*
* \retval The WDT window period.
*/
static inline enum wdt_window_period_t wdt_get_window_period(void)
{
return ((enum wdt_window_period_t)
((WDT.WINCTRL & WDT_WPER_gm) >> WDT_WPER_gp));
}
/*! \brief Set Watchdog timeout period.
*
* This function sets the coded field of the WDT timeout period.
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the CTRL register. Interrupts are
* automatically ignored during the change enable period. The function will
* wait for the WDT to be synchronized to the WDT clock domain before
* proceeding
*
* \param to_period WDT timeout coded period
*/
void wdt_set_timeout_period(enum wdt_timeout_period_t to_period);
/*! \brief Set Watchdog window period.
*
* This function sets the coded field of the WDT closed window period.
* Note that this setting is available only if the WDT is enabled (hardware
* behaviour relayed by software).
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the WINCTRL register. Interrupts
* are automatically ignored during the change enable period. The function will
* wait for the WDT to be synchronized to the WDT clock domain before
* proceeding
*
* \param win_period Window coded period
*
* \retval true The WDT was enabled and the setting is done.
* false The WDT is disabled and the setting is discarded.
*/
bool wdt_set_window_period(enum wdt_window_period_t win_period);
/*! \brief Disable Watchdog.
*
* This function disables the WDT without changing period settings.
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the CTRL register. Interrupts are
* automatically ignored during the change enable period. Disable functions
* operate asynchronously with immediate effect.
*/
void wdt_disable(void);
/*! \brief Enable Watchdog.
*
* This function enables the WDT without changing period settings.
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the CTRL register. Interrupts are
* automatically ignored during the change enable period. The function will
* wait for the WDT to be synchronized to the WDT clock domain before
* proceeding
*/
void wdt_enable(void);
/*! \brief Disable Watchdog window mode without changing period settings.
*
* This function disables the WDT window mode without changing period settings.
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the WINCTRL register. Interrupts
* are automatically ignored during the change enable period. Disable functions
* operate asynchronously with immediate effect.
*
* \retval true The WDT was enabled and the window mode is disabled.
* false The WDT (& the window mode) is already disabled.
*/
bool wdt_disable_window_mode(void);
/*! \brief Enable Watchdog window mode.
*
* This function enables the WDT window mode without changing period settings.
*
* The function writes the correct signature to the Configuration
* Change Protection register before writing the WINCTRL register. Interrupts
* are automatically ignored during the change enable period. The function will
* wait for the WDT to be synchronized to the WDT clock domain before
* proceeding
*
* \retval true The WDT was enabled and the setting is done.
* false The WDT is disabled and the setting is discarded.
*/
bool wdt_enable_window_mode(void);
/*! \brief Reset MCU via Watchdog.
*
* This function generates an hardware microcontroller reset using the WDT.
*
* The function loads enables the WDT in window mode. Executing a "wdr" asm
* instruction when the windows is closed, provides a quick mcu reset.
*
*/
void wdt_reset_mcu(void);
//! @}
/// @cond 0
/**INDENT-OFF**/
#ifdef __cplusplus
}
#endif
/**INDENT-ON**/
/// @endcond
/**
* \page wdt_quickstart Quick start guide for WDT driver
*
* This is the quick start guide for the \ref wdt_group, with
* step-by-step instructions on how to configure and use the driver in a
* selection of use cases.
*
* The use cases contain several code fragments. The code fragments in the
* steps for setup can be copied into a custom initialization function, while
* the steps for usage can be copied into, e.g., the main application function.
*
* \section wdt_basic_use_case Basic use case
* \section wdt_use_cases WDT use cases
* - \ref wdt_basic_use_case
* - \subpage wdt_use_case_1
*
* \section wdt_basic_use_case Basic use case - Reset WDT in standard mode
* In this use case, the WDT is configured for:
* - Standard mode
* - Timeout period of 8 ms
*
* The use case enables the WDT, and resets it after 5 ms to prevent system
* reset after time out period of 8 ms.
*
* \section wdt_basic_use_case_setup Setup steps
*
* \subsection wdt_basic_use_case_setup_prereq Prerequisites
* For the setup code of this use case to work, the following must
* be added to the project:
* -# \ref group_common_services_delay "Busy-Wait Delay Routines"
*
* \subsection wdt_basic_use_case_setup_code Example code
* Add to application initialization:
* \code
* wdt_set_timeout_period(WDT_TIMEOUT_PERIOD_8CLK);
* wdt_enable();
* \endcode
*
* \subsection wdt_basic_use_case_setup_flow Workflow
* -# Set timeout period to 8 cycles or 8 ms:
* - \code wdt_set_timeout_period(WDT_TIMEOUT_PERIOD_8CLK); \endcode
* -# Enable WDT:
* - \code wdt_enable(); \endcode
* \section wdt_basic_use_case_usage Usage steps
*
* \subsection wdt_basic_use_case_usage_code Example code
* Add to, e.g., main loop in application C-file:
* \code
* delay_ms(5);
* wdt_reset();
* \endcode
*
* \subsection wdt_basic_use_case_usage_flow Workflow
* -# Wait for 5 ms:
* - \code delay_ms(5); \endcode
* -# Reset the WDT before the timeout period is over to prevent system reset:
* - \code wdt_reset(); \endcode
*/
/**
* \page wdt_use_case_1 Reset WDT in window mode
*
* In this use case, the WDT is configured for:
* - Window mode
* - Timeout period of 16 ms
*
* The use case enables the WDT in window mode, and resets it after 10 ms to
* prevent system reset before window timeout after 8 ms and after time out
* period of 16 ms.
*
* \section wdt_use_case_1_setup Setup steps
*
* \subsection usart_use_case_1_setup_prereq Prerequisites
* For the setup code of this use case to work, the following must
* be added to the project:
* -# \ref group_common_services_delay "Busy-Wait Delay Routines"
*
* \subsection wdt_use_case_1_setup_code Example code
* Add to application initialization:
* \code
* wdt_set_timeout_period(WDT_TIMEOUT_PERIOD_16CLK);
* wdt_enable();
* wdt_set_window_period(WDT_TIMEOUT_PERIOD_8CLK);
* wdt_enable_window_mode();
* \endcode
*
* \subsection wdt_use_case_1_setup_flow Workflow
* -# Set timeout period to 16 cycles or 16 ms:
* - \code wdt_set_timeout_period(WDT_TIMEOUT_PERIOD_16CLK); \endcode
* -# Enable WDT:
* - \code wdt_enable(); \endcode
* -# Set window period to 8 cycles or 8 ms:
* - \code wdt_set_window_period(WDT_TIMEOUT_PERIOD_8CLK); \endcode
* -# Enable window mode:
* - \code wdt_enable_window_mode(); \endcode
*
* \section wdt_use_case_1_usage Usage steps
*
* \subsection wdt_use_case_1_usage_code Example code
* Add to, e.g., main loop in application C-file:
* \code
* delay_ms(10);
* wdt_reset();
* \endcode
*
* \subsection wdt_use_case_1_usage_flow Workflow
* -# Wait for 10 ms to not reset the WDT before window timeout:
* - \code delay_ms(10); \endcode
* -# Reset the WDT before the timeout period is over to prevent system reset:
* - \code wdt_reset(); \endcode
*/
#endif // _WDT_H_