adjust root folder
This commit is contained in:
Steve Karg
@@ -0,0 +1,516 @@
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/**************************************************************************
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*
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* Copyright (C) 2009 Steve Karg <skarg@users.sourceforge.net>
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* Used algorithm and code from Joerg Wunsch and Ruwan Jayanetti.
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* http://www.nongnu.org/avr-libc/user-manual/group__twi__demo.html
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*********************************************************************/
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "hardware.h"
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/* me */
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#include "seeprom.h"
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/* the SEEPROM chip select bits A2, A1, and A0 are grounded */
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/* control byte is 0xAx */
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#ifndef SEEPROM_I2C_ADDRESS
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#define SEEPROM_I2C_ADDRESS 0xA0
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#endif
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/* SEEPROM Clock Frequency */
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#ifndef SEEPROM_I2C_CLOCK
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#define SEEPROM_I2C_CLOCK 400000UL
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#endif
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/* max number of bytes that can be written in a single write */
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#ifndef SEEPROM_PAGE_SIZE
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#define SEEPROM_PAGE_SIZE 128
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#endif
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/* word addressing - is it 8-bit or 16-bit */
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#ifndef SEEPROM_WORD_ADDRESS_16BIT
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#define SEEPROM_WORD_ADDRESS_16BIT 1
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#endif
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/* maximum write cycle time in milliseconds - see datasheet */
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#ifndef EEPROM_WRITE_CYCLE
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#define EEPROM_WRITE_CYCLE 5
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#endif
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/* The lower 3 bits of TWSR are reserved on the ATmega163 */
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#define TW_STATUS_MASK (_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|_BV(TWS3))
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/* start condition transmitted */
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#define TW_START 0x08
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/* repeated start condition transmitted */
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#define TW_REP_START 0x10
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/* ***Master Transmitter*** */
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/* SLA+W transmitted, ACK received */
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#define TW_MT_SLA_ACK 0x18
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/* SLA+W transmitted, NACK received */
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#define TW_MT_SLA_NACK 0x20
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/* data transmitted, ACK received */
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#define TW_MT_DATA_ACK 0x28
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/* data transmitted, NACK received */
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#define TW_MT_DATA_NACK 0x30
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/* arbitration lost in SLA+W or data */
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#define TW_MT_ARB_LOST 0x38
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/* ***Master Receiver*** */
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/* arbitration lost in SLA+R or NACK */
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#define TW_MR_ARB_LOST 0x38
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/* SLA+R transmitted, ACK received */
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#define TW_MR_SLA_ACK 0x40
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/* SLA+R transmitted, NACK received */
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#define TW_MR_SLA_NACK 0x48
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/* data received, ACK returned */
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#define TW_MR_DATA_ACK 0x50
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/* data received, NACK returned */
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#define TW_MR_DATA_NACK 0x58
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/* SLA+R address */
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#define TW_READ 1
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/* SLA+W address */
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#define TW_WRITE 0
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/* Number of iterations is the max amount to wait for write cycle
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to complete a full page write */
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/* .005s/.000025=200 */
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#define MAX_ITER (((SEEPROM_I2C_CLOCK/1000)/10)*SEEPROM_WRITE_CYCLE)
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/*************************************************************************
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* DESCRIPTION: Return bytes from SEEPROM memory at address
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* RETURN: number of bytes read, or -1 on error
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* NOTES: none
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**************************************************************************/
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int seeprom_bytes_read(
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uint16_t eeaddr, /* SEEPROM starting memory address */
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uint8_t * buf, /* data to store */
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int len)
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{ /* number of bytes of data to read */
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uint8_t sla, twcr, n = 0;
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int rv = 0;
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uint8_t twst; /* status - only valid while TWINT is set. */
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uint16_t timeout = 0xFFFF;
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#if SEEPROM_WORD_ADDRESS_16BIT
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/* 16bit address devices need only TWI Device Address */
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sla = SEEPROM_I2C_ADDRESS;
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#else
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/* patch high bits of EEPROM address into SLA */
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sla = SEEPROM_I2C_ADDRESS | (((eeaddr >> 8) & 0x07) << 1);
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#endif
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/* First cycle: master transmitter mode */
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restart:
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if (n++ >= MAX_ITER) {
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return -1;
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}
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begin:
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/* send start condition */
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TWCR = _BV(TWINT) | _BV(TWSTA) | _BV(TWEN);
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/* wait for transmission */
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while ((TWCR & _BV(TWINT)) == 0) {
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timeout--;
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if (timeout == 0) {
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return -1;
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}
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}
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twst = TWSR & TW_STATUS_MASK;
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switch (twst) {
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case TW_REP_START:
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/* OK, but should not happen */
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case TW_START:
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break;
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case TW_MT_ARB_LOST:
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/* Since the TWI bus is multi-master capable,
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there is potential for a bus contention when
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one master starts to access the bus. */
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goto begin;
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default:
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/* error: not in start condition */
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/* NB: do /not/ send stop condition */
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return -1;
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}
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/* Next, the device slave is going to be reselected using a repeated
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start condition which is meant to guarantee that the bus arbitration
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will remain at the current master. This uses the same slave address
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(SLA), but this time with read intent (R/~W bit set to 1) in order
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to request the device slave to start transfering data from the slave
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to the master in the next packet. */
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/* send SLA+W */
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TWDR = sla | TW_WRITE;
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/* clear interrupt to start transmission */
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TWCR = _BV(TWINT) | _BV(TWEN);
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/* wait for transmission */
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while ((TWCR & _BV(TWINT)) == 0);
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twst = TWSR & TW_STATUS_MASK;
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switch (twst) {
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case TW_MT_SLA_ACK:
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break;
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case TW_MT_SLA_NACK:
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/* nack during select: device busy writing */
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/* If the EEPROM device is still busy writing one or more cells
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after a previous write request, it will simply leave its bus
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interface drivers at high impedance, and does not respond to
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a selection in any way at all. */
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goto restart;
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case TW_MT_ARB_LOST:
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/* re-arbitrate */
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goto begin;
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default:
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/* must send stop condition */
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goto error;
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}
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#if SEEPROM_WORD_ADDRESS_16BIT
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/* 16 bit word address device, send high 8 bits of addr */
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TWDR = (eeaddr >> 8);
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/* clear interrupt to start transmission */
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TWCR = _BV(TWINT) | _BV(TWEN);
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/* wait for transmission */
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while ((TWCR & _BV(TWINT)) == 0);
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twst = TWSR & TW_STATUS_MASK;
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switch (twst) {
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case TW_MT_DATA_ACK:
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break;
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case TW_MT_DATA_NACK:
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goto quit;
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case TW_MT_ARB_LOST:
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goto begin;
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default:
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/* must send stop condition */
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goto error;
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}
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#endif
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/* low 8 bits of addr */
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TWDR = eeaddr;
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/* clear interrupt to start transmission */
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TWCR = _BV(TWINT) | _BV(TWEN);
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/* wait for transmission */
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while ((TWCR & _BV(TWINT)) == 0);
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twst = TWSR & TW_STATUS_MASK;
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switch (twst) {
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case TW_MT_DATA_ACK:
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break;
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case TW_MT_DATA_NACK:
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goto quit;
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case TW_MT_ARB_LOST:
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goto begin;
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default:
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/* must send stop condition */
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goto error;
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}
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/* This is called master receiver mode: the bus master still supplies
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the SCL clock, but the device slave drives the SDA line with the
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appropriate data. After 8 data bits, the master responds with an ACK
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bit (SDA driven low) in order to request another data transfer from
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the slave, or it can leave the SDA line high (NACK), indicating to
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the slave that it is going to stop the transfer now.
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Assertion of ACK is handled by setting the TWEA bit in TWCR when
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starting the current transfer. */
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/* Next cycle(s): master receiver mode */
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/* send repeated start condition */
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TWCR = _BV(TWINT) | _BV(TWSTA) | _BV(TWEN);
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/* wait for transmission */
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while ((TWCR & _BV(TWINT)) == 0);
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twst = TWSR & TW_STATUS_MASK;
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switch (twst) {
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case TW_START:
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/* OK, but should not happen */
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case TW_REP_START:
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break;
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case TW_MT_ARB_LOST:
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goto begin;
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default:
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goto error;
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}
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/* send SLA+R */
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TWDR = sla | TW_READ;
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/* clear interrupt to start transmission */
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TWCR = _BV(TWINT) | _BV(TWEN);
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/* wait for transmission */
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while ((TWCR & _BV(TWINT)) == 0);
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twst = TWSR & TW_STATUS_MASK;
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switch (twst) {
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case TW_MR_SLA_ACK:
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break;
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case TW_MR_SLA_NACK:
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goto quit;
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case TW_MR_ARB_LOST:
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goto begin;
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default:
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goto error;
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}
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/* The control word sent out in order to initiate the transfer of the
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next data packet is initially set up to assert the TWEA bit.
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During the last loop iteration, TWEA is de-asserted so the client
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will get informed that no further transfer is desired. */
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twcr = _BV(TWINT) | _BV(TWEN) | _BV(TWEA);
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for (; len > 0; len--) {
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if (len == 1) {
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/* send NAK this time */
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twcr = _BV(TWINT) | _BV(TWEN);
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}
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/* clear int to start transmission */
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TWCR = twcr;
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/* wait for transmission */
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while ((TWCR & _BV(TWINT)) == 0);
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twst = TWSR & TW_STATUS_MASK;
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switch (twst) {
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case TW_MR_DATA_NACK:
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/* force end of loop */
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len = 0;
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/* FALLTHROUGH */
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case TW_MR_DATA_ACK:
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*buf = TWDR;
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buf++;
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rv++;
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break;
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default:
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goto error;
|
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}
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||||
}
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quit:
|
||||
/* Except in the case of lost arbitration, all bus transactions
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must properly be terminated by the master initiating a
|
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stop condition. */
|
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/* send stop condition */
|
||||
TWCR = _BV(TWINT) | _BV(TWSTO) | _BV(TWEN);
|
||||
return rv;
|
||||
error:
|
||||
rv = -1;
|
||||
goto quit;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* DESCRIPTION: Write some data and wait until it is sent
|
||||
* RETURN: number of bytes written, or -1 on error
|
||||
* NOTES: only writes from offset to end of page.
|
||||
**************************************************************************/
|
||||
static int seeprom_bytes_write_page(
|
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uint16_t eeaddr, /* SEEPROM starting memory address */
|
||||
uint8_t * buf, /* data to send */
|
||||
int len)
|
||||
{ /* number of bytes of data */
|
||||
uint8_t sla, n = 0;
|
||||
int rv = 0;
|
||||
uint16_t endaddr;
|
||||
uint8_t twst; /* status - only valid while TWINT is set. */
|
||||
uint16_t page_end_addr;
|
||||
uint16_t timeout = 0xFFFF;
|
||||
|
||||
/* limit the length to end of the EEPROM page */
|
||||
page_end_addr = eeaddr | (SEEPROM_PAGE_SIZE - 1);
|
||||
if ((eeaddr + len) > page_end_addr) {
|
||||
endaddr = page_end_addr + 1;
|
||||
len = endaddr - eeaddr;
|
||||
}
|
||||
#if SEEPROM_WORD_ADDRESS_16BIT
|
||||
/* 16bit address devices need only TWI Device Address */
|
||||
sla = SEEPROM_I2C_ADDRESS;
|
||||
#else
|
||||
/* patch high bits of EEPROM address into SLA */
|
||||
sla = SEEPROM_I2C_ADDRESS | (((eeaddr >> 8) & 0x07) << 1);
|
||||
#endif
|
||||
restart:
|
||||
if (n++ >= MAX_ITER) {
|
||||
return -1;
|
||||
}
|
||||
begin:
|
||||
/* Writing to the EEPROM device is simpler than reading,
|
||||
since only a master transmitter mode transfer is needed.
|
||||
Note that the first packet after the SLA+W selection is
|
||||
always considered to be the EEPROM address for the next operation.
|
||||
This packet is exactly the same as the one above sent before
|
||||
starting to read the device.
|
||||
In case a master transmitter mode transfer is going to send
|
||||
more than one data packet, all following packets will be considered
|
||||
data bytes to write at the indicated address.
|
||||
The internal address pointer will be incremented after each
|
||||
write operation. */
|
||||
/* send start condition */
|
||||
TWCR = _BV(TWINT) | _BV(TWSTA) | _BV(TWEN);
|
||||
/* wait for transmission */
|
||||
while ((TWCR & _BV(TWINT)) == 0) {
|
||||
timeout--;
|
||||
if (timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
twst = TWSR & TW_STATUS_MASK;
|
||||
switch (twst) {
|
||||
case TW_REP_START:
|
||||
/* OK, but should not happen */
|
||||
case TW_START:
|
||||
break;
|
||||
case TW_MT_ARB_LOST:
|
||||
goto begin;
|
||||
default:
|
||||
/* error: not in start condition */
|
||||
/* NB: do /not/ send stop condition */
|
||||
return -1;
|
||||
}
|
||||
/* send SLA+W */
|
||||
TWDR = sla | TW_WRITE;
|
||||
/* clear interrupt to start transmission */
|
||||
TWCR = _BV(TWINT) | _BV(TWEN);
|
||||
/* wait for transmission */
|
||||
while ((TWCR & _BV(TWINT)) == 0);
|
||||
twst = TWSR & TW_STATUS_MASK;
|
||||
switch (twst) {
|
||||
case TW_MT_SLA_ACK:
|
||||
break;
|
||||
case TW_MT_SLA_NACK:
|
||||
/* nack during select: device busy writing */
|
||||
goto restart;
|
||||
case TW_MT_ARB_LOST:
|
||||
/* re-arbitrate */
|
||||
goto begin;
|
||||
default:
|
||||
/* must send stop condition */
|
||||
goto error;
|
||||
}
|
||||
#if SEEPROM_WORD_ADDRESS_16BIT
|
||||
/* 16 bit word address device, send high 8 bits of addr */
|
||||
TWDR = (eeaddr >> 8);
|
||||
/* clear interrupt to start transmission */
|
||||
TWCR = _BV(TWINT) | _BV(TWEN);
|
||||
/* wait for transmission */
|
||||
while ((TWCR & _BV(TWINT)) == 0);
|
||||
twst = TWSR & TW_STATUS_MASK;
|
||||
switch (twst) {
|
||||
case TW_MT_DATA_ACK:
|
||||
break;
|
||||
case TW_MT_DATA_NACK:
|
||||
goto quit;
|
||||
case TW_MT_ARB_LOST:
|
||||
goto begin;
|
||||
default:
|
||||
/* must send stop condition */
|
||||
goto error;
|
||||
}
|
||||
#endif
|
||||
/* low 8 bits of addr */
|
||||
TWDR = eeaddr;
|
||||
/* clear interrupt to start transmission */
|
||||
TWCR = _BV(TWINT) | _BV(TWEN);
|
||||
/* wait for transmission */
|
||||
while ((TWCR & _BV(TWINT)) == 0) {
|
||||
};
|
||||
twst = TWSR & TW_STATUS_MASK;
|
||||
switch (twst) {
|
||||
case TW_MT_DATA_ACK:
|
||||
break;
|
||||
case TW_MT_DATA_NACK:
|
||||
goto quit;
|
||||
case TW_MT_ARB_LOST:
|
||||
goto begin;
|
||||
default:
|
||||
/* must send stop condition */
|
||||
goto error;
|
||||
}
|
||||
for (; len > 0; len--) {
|
||||
TWDR = *buf;
|
||||
/* start transmission */
|
||||
TWCR = _BV(TWINT) | _BV(TWEN);
|
||||
/* wait for transmission */
|
||||
while ((TWCR & _BV(TWINT)) == 0);
|
||||
twst = TWSR & TW_STATUS_MASK;
|
||||
switch (twst) {
|
||||
case TW_MT_DATA_NACK:
|
||||
/* device write protected -- Note [16] */
|
||||
goto error;
|
||||
case TW_MT_DATA_ACK:
|
||||
buf++;
|
||||
rv++;
|
||||
break;
|
||||
default:
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
quit:
|
||||
/* send stop condition */
|
||||
TWCR = _BV(TWINT) | _BV(TWSTO) | _BV(TWEN);
|
||||
|
||||
return rv;
|
||||
|
||||
error:
|
||||
rv = -1;
|
||||
goto quit;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* DESCRIPTION: Write some data and wait until it is sent
|
||||
* RETURN: number of bytes written, or -1 on error
|
||||
* NOTES:
|
||||
* When the word address, internally generated,
|
||||
* reaches the page boundary, the following
|
||||
* byte is placed at the beginning of the same
|
||||
* page. If more than 64 data words are
|
||||
* transmitted to the EEPROM, the data word
|
||||
* address will "roll over" and previous data will be
|
||||
* overwritten. The address "roll over" during write
|
||||
* is from the last byte of the current page to the
|
||||
* first byte of the same page.
|
||||
**************************************************************************/
|
||||
int seeprom_bytes_write(
|
||||
uint16_t off, /* SEEPROM starting memory address */
|
||||
uint8_t * buf, /* data to send */
|
||||
int len)
|
||||
{ /* number of bytes of data */
|
||||
int status = 0;
|
||||
int rv = 0;
|
||||
|
||||
while (len) {
|
||||
status = seeprom_bytes_write_page(off, buf, len);
|
||||
if (status <= 0) {
|
||||
if (rv == 0) {
|
||||
rv = status;
|
||||
}
|
||||
break;
|
||||
}
|
||||
buf += status;
|
||||
off += status;
|
||||
len -= status;
|
||||
rv += status;
|
||||
}
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* Description: Initialize the SEEPROM TWI connection
|
||||
* Returns: none
|
||||
* Notes: none
|
||||
**************************************************************************/
|
||||
void seeprom_init(
|
||||
void)
|
||||
{
|
||||
/* bit rate prescaler */
|
||||
TWSR = 0;
|
||||
TWCR = _BV(TWEN) | _BV(TWEA);
|
||||
/* bit rate */
|
||||
/* SCL freq = F_CPU/(16+2*TWBR*4^TWPS) */
|
||||
/* since TWPS in TWSR is set to zero, 4^TWPS resolves to 1 */
|
||||
TWBR = (F_CPU / SEEPROM_I2C_CLOCK - 16) / 2;
|
||||
/* my address */
|
||||
TWAR = 0;
|
||||
}
|
||||
Reference in New Issue
Block a user