Added clear to power reduction registers, but still no timer interrupt under simulation.

This commit is contained in:
skarg
2007-08-15 18:27:43 +00:00
parent 1b364d6df1
commit 7e1b95d18f
4 changed files with 32 additions and 11 deletions
+3 -1
View File
@@ -50,7 +50,9 @@ void init(void)
DDRD = 0;
PORTD = 0;
/* Configure the watchdog timer */
/* Configure the watchdog timer - Disabled for testing */
BIT_CLEAR(MCUSR,WDRF);
WDTCSR = 0;
/* Configure USART */
RS485_Set_Baud_Rate(38400);